Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Freescale Semiconductor |
Yangbo Lu | bb32e68 | 2021-06-03 10:51:19 +0800 | [diff] [blame] | 4 | * Copyright 2019-2021 NXP |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __LS1043A_COMMON_H |
| 8 | #define __LS1043A_COMMON_H |
| 9 | |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 10 | /* SPL build */ |
| 11 | #ifdef CONFIG_SPL_BUILD |
| 12 | #define SPL_NO_FMAN |
| 13 | #define SPL_NO_DSPI |
| 14 | #define SPL_NO_PCIE |
| 15 | #define SPL_NO_ENV |
| 16 | #define SPL_NO_MISC |
| 17 | #define SPL_NO_USB |
| 18 | #define SPL_NO_SATA |
| 19 | #define SPL_NO_QE |
| 20 | #define SPL_NO_EEPROM |
| 21 | #endif |
| 22 | #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) |
| 23 | #define SPL_NO_MMC |
| 24 | #endif |
Yangbo Lu | 83c4ece | 2017-09-15 09:51:58 +0800 | [diff] [blame] | 25 | #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 26 | #define SPL_NO_IFC |
| 27 | #endif |
| 28 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 29 | #define CONFIG_REMAKE_ELF |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 30 | #define CONFIG_GICV2 |
| 31 | |
Bharat Bhushan | 882b632 | 2017-03-22 12:06:27 +0530 | [diff] [blame] | 32 | #include <asm/arch/stream_id_lsch2.h> |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 33 | #include <asm/arch/config.h> |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 34 | |
| 35 | /* Link Definitions */ |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 36 | #ifdef CONFIG_TFABOOT |
| 37 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE |
| 38 | #else |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 39 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 40 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 41 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 42 | #define CONFIG_SKIP_LOWLEVEL_INIT |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 43 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 44 | #define CONFIG_VERY_BIG_RAM |
| 45 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 |
| 46 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |
| 47 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Shaohui Xie | f6c8395 | 2015-11-23 15:23:48 +0800 | [diff] [blame] | 48 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 49 | |
Michael Walle | f056e0f | 2020-06-01 21:53:26 +0200 | [diff] [blame] | 50 | #define CPU_RELEASE_ADDR secondary_boot_addr |
Hou Zhiqiang | c7098fa | 2015-10-26 19:47:57 +0800 | [diff] [blame] | 51 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 52 | /* Generic Timer Definitions */ |
| 53 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ |
| 54 | |
| 55 | /* Size of malloc() pool */ |
| 56 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) |
| 57 | |
| 58 | /* Serial Port */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 59 | #define CONFIG_SYS_NS16550_SERIAL |
| 60 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 61 | #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 62 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 63 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 64 | |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 65 | /* SD boot SPL */ |
| 66 | #ifdef CONFIG_SD_BOOT |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 67 | |
Ruchika Gupta | d6b8920 | 2017-04-17 18:07:17 +0530 | [diff] [blame] | 68 | #define CONFIG_SPL_MAX_SIZE 0x17000 |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 69 | #define CONFIG_SPL_STACK 0x1001e000 |
| 70 | #define CONFIG_SPL_PAD_TO 0x1d000 |
| 71 | |
York Sun | f7eed6b | 2017-09-28 08:42:16 -0700 | [diff] [blame] | 72 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ |
| 73 | CONFIG_SPL_BSS_MAX_SIZE) |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 74 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
York Sun | f7eed6b | 2017-09-28 08:42:16 -0700 | [diff] [blame] | 75 | #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 76 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
Ruchika Gupta | d6b8920 | 2017-04-17 18:07:17 +0530 | [diff] [blame] | 77 | |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 78 | #ifdef CONFIG_NXP_ESBC |
Ruchika Gupta | d6b8920 | 2017-04-17 18:07:17 +0530 | [diff] [blame] | 79 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
| 80 | /* |
| 81 | * HDR would be appended at end of image and copied to DDR along |
| 82 | * with U-Boot image. Here u-boot max. size is 512K. So if binary |
| 83 | * size increases then increase this size in case of secure boot as |
| 84 | * it uses raw u-boot image instead of fit image. |
| 85 | */ |
| 86 | #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) |
| 87 | #else |
| 88 | #define CONFIG_SYS_MONITOR_LEN 0x100000 |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 89 | #endif /* ifdef CONFIG_NXP_ESBC */ |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 90 | #endif |
| 91 | |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 92 | /* NAND SPL */ |
| 93 | #ifdef CONFIG_NAND_BOOT |
| 94 | #define CONFIG_SPL_PBL_PAD |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 95 | #define CONFIG_SPL_MAX_SIZE 0x1a000 |
| 96 | #define CONFIG_SPL_STACK 0x1001d000 |
| 97 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE |
| 98 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
| 99 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 |
| 100 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
| 101 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 102 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
Ruchika Gupta | ba68875 | 2017-04-17 18:07:18 +0530 | [diff] [blame] | 103 | |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 104 | #ifdef CONFIG_NXP_ESBC |
Ruchika Gupta | ba68875 | 2017-04-17 18:07:18 +0530 | [diff] [blame] | 105 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 106 | #endif /* ifdef CONFIG_NXP_ESBC */ |
Ruchika Gupta | ba68875 | 2017-04-17 18:07:18 +0530 | [diff] [blame] | 107 | |
| 108 | #ifdef CONFIG_U_BOOT_HDR_SIZE |
| 109 | /* |
| 110 | * HDR would be appended at end of image and copied to DDR along |
| 111 | * with U-Boot image. Here u-boot max. size is 512K. So if binary |
| 112 | * size increases then increase this size in case of secure boot as |
| 113 | * it uses raw u-boot image instead of fit image. |
| 114 | */ |
| 115 | #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) |
| 116 | #else |
| 117 | #define CONFIG_SYS_MONITOR_LEN 0x100000 |
| 118 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ |
| 119 | |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 120 | #endif |
| 121 | |
Biwen Li | 46de400 | 2021-02-05 19:01:56 +0800 | [diff] [blame] | 122 | /* GPIO */ |
| 123 | #ifdef CONFIG_DM_GPIO |
| 124 | #ifndef CONFIG_MPC8XXX_GPIO |
| 125 | #define CONFIG_MPC8XXX_GPIO |
| 126 | #endif |
| 127 | #endif |
| 128 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 129 | /* IFC */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 130 | #ifndef SPL_NO_IFC |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 131 | #if defined(CONFIG_TFABOOT) || \ |
| 132 | (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 133 | #define CONFIG_FSL_IFC |
| 134 | /* |
| 135 | * CONFIG_SYS_FLASH_BASE has the final address (core view) |
| 136 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) |
| 137 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address |
| 138 | * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting |
| 139 | */ |
| 140 | #define CONFIG_SYS_FLASH_BASE 0x60000000 |
| 141 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 142 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 |
| 143 | |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 144 | #ifdef CONFIG_MTD_NOR_FLASH |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 145 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 146 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 147 | #endif |
Gong Qianyu | 760df89 | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 148 | #endif |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 149 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 150 | |
| 151 | /* I2C */ |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 152 | #if !CONFIG_IS_ENABLED(DM_I2C) |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 153 | #define CONFIG_SYS_I2C |
Biwen Li | 014460b | 2020-02-05 22:02:16 +0800 | [diff] [blame] | 154 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
| 155 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
| 156 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
| 157 | #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ |
| 158 | #else |
| 159 | #define CONFIG_I2C_SET_DEFAULT_BUS_NUM |
| 160 | #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 |
| 161 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 162 | |
| 163 | /* PCIe */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 164 | #ifndef SPL_NO_PCIE |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 165 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 166 | #define CONFIG_PCIE2 /* PCIE controller 2 */ |
| 167 | #define CONFIG_PCIE3 /* PCIE controller 3 */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 168 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 169 | #ifdef CONFIG_PCI |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 170 | #define CONFIG_PCI_SCAN_SHOW |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 171 | #endif |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 172 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 173 | |
Gong Qianyu | 51c18dc | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 174 | /* DSPI */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 175 | #ifndef SPL_NO_DSPI |
Gong Qianyu | 51c18dc | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 176 | #ifdef CONFIG_FSL_DSPI |
Gong Qianyu | 51c18dc | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 177 | #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ |
| 178 | #define CONFIG_SPI_FLASH_SST /* cs1 */ |
| 179 | #define CONFIG_SPI_FLASH_EON /* cs2 */ |
Gong Qianyu | 760df89 | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 180 | #endif |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 181 | #endif |
Gong Qianyu | 51c18dc | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 182 | |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 183 | /* FMan ucode */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 184 | #ifndef SPL_NO_FMAN |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 185 | #define CONFIG_SYS_DPAA_FMAN |
| 186 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 187 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 |
| 188 | |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 189 | #ifdef CONFIG_TFABOOT |
| 190 | #define CONFIG_SYS_FMAN_FW_ADDR 0x900000 |
| 191 | #define CONFIG_SYS_QE_FW_ADDR 0x940000 |
| 192 | |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 193 | |
| 194 | #else |
Qianyu Gong | c80a20c | 2016-04-01 17:52:52 +0800 | [diff] [blame] | 195 | #ifdef CONFIG_NAND_BOOT |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 196 | /* Store Fman ucode at offeset 0x900000(72 blocks). */ |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 197 | #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) |
Qianyu Gong | 9a207ca | 2016-04-01 17:52:53 +0800 | [diff] [blame] | 198 | #elif defined(CONFIG_SD_BOOT) |
| 199 | /* |
| 200 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is |
| 201 | * about 1MB (2040 blocks), Env is stored after the image, and the env size is |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 202 | * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). |
Qianyu Gong | 9a207ca | 2016-04-01 17:52:53 +0800 | [diff] [blame] | 203 | */ |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 204 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) |
Zhao Qiang | ff12438 | 2018-12-05 17:01:42 +0800 | [diff] [blame] | 205 | #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00) |
Qianyu Gong | 9a207ca | 2016-04-01 17:52:53 +0800 | [diff] [blame] | 206 | #elif defined(CONFIG_QSPI_BOOT) |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 207 | #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 |
Gong Qianyu | 760df89 | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 208 | #else |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 209 | /* FMan fireware Pre-load address */ |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 210 | #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 |
Zhao Qiang | 82cd8c6 | 2017-05-25 09:47:40 +0800 | [diff] [blame] | 211 | #define CONFIG_SYS_QE_FW_ADDR 0x60940000 |
Gong Qianyu | 760df89 | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 212 | #endif |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 213 | #endif |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 214 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 215 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
| 216 | #endif |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 217 | #endif |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 218 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 219 | /* Miscellaneous configurable options */ |
| 220 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 221 | |
| 222 | #define CONFIG_HWCONFIG |
| 223 | #define HWCONFIG_BUFFER_SIZE 128 |
| 224 | |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 225 | #ifndef SPL_NO_MISC |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 226 | #ifndef CONFIG_SPL_BUILD |
| 227 | #define BOOT_TARGET_DEVICES(func) \ |
| 228 | func(MMC, mmc, 0) \ |
Mian Yousaf Kaukab | 6519df7 | 2019-01-29 16:38:40 +0100 | [diff] [blame] | 229 | func(USB, usb, 0) \ |
| 230 | func(DHCP, dhcp, na) |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 231 | #include <config_distro_bootcmd.h> |
| 232 | #endif |
| 233 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 234 | /* Initial environment variables */ |
| 235 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 236 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 237 | "fdt_high=0xffffffffffffffff\0" \ |
| 238 | "initrd_high=0xffffffffffffffff\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 239 | "fdt_addr=0x64f00000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 240 | "kernel_addr=0x61000000\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 241 | "scriptaddr=0x80000000\0" \ |
Sumit Garg | 9cbcc4d | 2017-06-05 23:51:51 +0530 | [diff] [blame] | 242 | "scripthdraddr=0x80080000\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 243 | "fdtheader_addr_r=0x80100000\0" \ |
| 244 | "kernelheader_addr_r=0x80200000\0" \ |
| 245 | "kernel_addr_r=0x81000000\0" \ |
Wen He | 335b386 | 2018-11-20 16:55:25 +0800 | [diff] [blame] | 246 | "kernel_start=0x1000000\0" \ |
| 247 | "kernelheader_start=0x800000\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 248 | "fdt_addr_r=0x90000000\0" \ |
| 249 | "load_addr=0xa0000000\0" \ |
Manish Tomar | 8d38801 | 2020-11-05 14:08:55 +0530 | [diff] [blame] | 250 | "kernelheader_addr=0x60600000\0" \ |
Qianyu Gong | 2758edf | 2016-03-15 16:35:57 +0800 | [diff] [blame] | 251 | "kernel_size=0x2800000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 252 | "kernelheader_size=0x40000\0" \ |
Shengzhou Liu | 4286275 | 2017-11-09 17:57:55 +0800 | [diff] [blame] | 253 | "kernel_addr_sd=0x8000\0" \ |
| 254 | "kernel_size_sd=0x14000\0" \ |
Manish Tomar | 8d38801 | 2020-11-05 14:08:55 +0530 | [diff] [blame] | 255 | "kernelhdr_addr_sd=0x3000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 256 | "kernelhdr_size_sd=0x10\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 257 | "console=ttyS0,115200\0" \ |
York Sun | f7eed6b | 2017-09-28 08:42:16 -0700 | [diff] [blame] | 258 | "boot_os=y\0" \ |
Tom Rini | 5ad8e11 | 2017-10-22 17:55:07 -0400 | [diff] [blame] | 259 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 260 | BOOTENV \ |
| 261 | "boot_scripts=ls1043ardb_boot.scr\0" \ |
Sumit Garg | 9cbcc4d | 2017-06-05 23:51:51 +0530 | [diff] [blame] | 262 | "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 263 | "scan_dev_for_boot_part=" \ |
| 264 | "part list ${devtype} ${devnum} devplist; " \ |
| 265 | "env exists devplist || setenv devplist 1; " \ |
| 266 | "for distro_bootpart in ${devplist}; do " \ |
| 267 | "if fstype ${devtype} " \ |
| 268 | "${devnum}:${distro_bootpart} " \ |
| 269 | "bootfstype; then " \ |
| 270 | "run scan_dev_for_boot; " \ |
| 271 | "fi; " \ |
| 272 | "done\0" \ |
Sumit Garg | 9cbcc4d | 2017-06-05 23:51:51 +0530 | [diff] [blame] | 273 | "boot_a_script=" \ |
| 274 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 275 | "${scriptaddr} ${prefix}${script}; " \ |
| 276 | "env exists secureboot && load ${devtype} " \ |
| 277 | "${devnum}:${distro_bootpart} " \ |
Vinitha V Pillai | 25355ec | 2019-04-23 05:52:17 +0000 | [diff] [blame] | 278 | "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ |
| 279 | "env exists secureboot " \ |
Sumit Garg | 9cbcc4d | 2017-06-05 23:51:51 +0530 | [diff] [blame] | 280 | "&& esbc_validate ${scripthdraddr};" \ |
| 281 | "source ${scriptaddr}\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 282 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
| 283 | "sf probe && sf read $load_addr " \ |
Wen He | cabe55c | 2019-11-14 15:08:15 +0800 | [diff] [blame] | 284 | "$kernel_start $kernel_size; env exists secureboot " \ |
| 285 | "&& sf read $kernelheader_addr_r $kernelheader_start " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 286 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 287 | "bootm $load_addr#$board\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 288 | "nor_bootcmd=echo Trying load from nor..;" \ |
| 289 | "cp.b $kernel_addr $load_addr " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 290 | "$kernel_size; env exists secureboot " \ |
| 291 | "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ |
| 292 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 293 | "bootm $load_addr#$board\0" \ |
Wen He | 335b386 | 2018-11-20 16:55:25 +0800 | [diff] [blame] | 294 | "nand_bootcmd=echo Trying load from NAND..;" \ |
| 295 | "nand info; nand read $load_addr " \ |
| 296 | "$kernel_start $kernel_size; env exists secureboot " \ |
| 297 | "&& nand read $kernelheader_addr_r $kernelheader_start " \ |
| 298 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 299 | "bootm $load_addr#$board\0" \ |
Shengzhou Liu | 4286275 | 2017-11-09 17:57:55 +0800 | [diff] [blame] | 300 | "sd_bootcmd=echo Trying load from SD ..;" \ |
| 301 | "mmcinfo; mmc read $load_addr " \ |
| 302 | "$kernel_addr_sd $kernel_size_sd && " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 303 | "env exists secureboot && mmc read $kernelheader_addr_r " \ |
| 304 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ |
| 305 | " && esbc_validate ${kernelheader_addr_r};" \ |
Shengzhou Liu | 4286275 | 2017-11-09 17:57:55 +0800 | [diff] [blame] | 306 | "bootm $load_addr#$board\0" |
| 307 | |
Wenbin Song | 1738ca7 | 2016-07-21 18:55:16 +0800 | [diff] [blame] | 308 | |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 309 | #undef CONFIG_BOOTCOMMAND |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 310 | #ifdef CONFIG_TFABOOT |
| 311 | #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ |
| 312 | "env exists secureboot && esbc_halt;" |
| 313 | #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ |
| 314 | "env exists secureboot && esbc_halt;" |
| 315 | #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ |
| 316 | "env exists secureboot && esbc_halt;" |
Pankit Garg | 6921072 | 2018-12-27 04:37:53 +0000 | [diff] [blame] | 317 | #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ |
| 318 | "env exists secureboot && esbc_halt;" |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 319 | #else |
Qianyu Gong | baacecb | 2016-04-25 16:53:53 +0800 | [diff] [blame] | 320 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 321 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ |
| 322 | "env exists secureboot && esbc_halt;" |
Shengzhou Liu | 4286275 | 2017-11-09 17:57:55 +0800 | [diff] [blame] | 323 | #elif defined(CONFIG_SD_BOOT) |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 324 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ |
| 325 | "env exists secureboot && esbc_halt;" |
Qianyu Gong | baacecb | 2016-04-25 16:53:53 +0800 | [diff] [blame] | 326 | #else |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 327 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ |
| 328 | "env exists secureboot && esbc_halt;" |
Qianyu Gong | baacecb | 2016-04-25 16:53:53 +0800 | [diff] [blame] | 329 | #endif |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 330 | #endif |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 331 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 332 | |
| 333 | /* Monitor Command Prompt */ |
| 334 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 335 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 336 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
| 337 | |
| 338 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 339 | |
Simon Glass | 89e0a3a | 2017-05-17 08:23:10 -0600 | [diff] [blame] | 340 | #include <asm/arch/soc.h> |
| 341 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 342 | #endif /* __LS1043A_COMMON_H */ |