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git01.mediatek.com / filogic / uboot / 1a7b055adb2907385ed8804c5942217e2343c9ba / . / board / gateworks / gw_ventana / common.h
blob: 8019e27f6e04224a54fe775e0d2dea9ad830610c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]2/*
3 * Copyright (C) 2013 Gateworks Corporation
4 *
5 * Author: Tim Harvey <tharvey@gateworks.com>
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]6 */
7
8#ifndef _GWVENTANA_COMMON_H_
9#define _GWVENTANA_COMMON_H_
10
11#include "ventana_eeprom.h"
12
13/* GPIO's common to all baseboards */
14#define GP_PHY_RST IMX_GPIO_NR(1, 30)
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]15#define GP_RS232_EN IMX_GPIO_NR(2, 11)
16#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
17
18#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
19 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
20 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
21
22#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
23 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
24 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
25
26#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
28 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
29
30#define SPI_PAD_CTRL (PAD_CTL_HYS | \
31 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
33
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]34#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
35 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
36 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
37
38#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
40 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
41
Tim Harveydb7edfa2015-05-26 11:04:54 -0700[diff] [blame]42#define DIO_PAD_CFG (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION)
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]43
44#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
45
46/*
Tim Harvey41595b52016-07-15 07:14:23 -0700[diff] [blame]47 * each baseboard has an optional set user configurable Digital IO lines which
48 * can be pinmuxed as a GPIO or in some cases a PWM
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]49 */
50struct dio_cfg {
51 iomux_v3_cfg_t gpio_padmux[2];
52 unsigned gpio_param;
53 iomux_v3_cfg_t pwm_padmux[2];
54 unsigned pwm_param;
55};
56
57struct ventana {
58 /* pinmux */
59 iomux_v3_cfg_t const *gpio_pads;
60 int num_pads;
61 /* DIO pinmux/val */
Tim Harvey41595b52016-07-15 07:14:23 -0700[diff] [blame]62 struct dio_cfg *dio_cfg;
63 int dio_num;
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]64 /* various gpios (0 if non-existent) */
65 int leds[3];
66 int pcie_rst;
67 int mezz_pwren;
68 int mezz_irq;
69 int rs485en;
70 int gps_shdn;
71 int vidin_en;
72 int dioi2c_en;
73 int pcie_sson;
74 int usb_sel;
75 int wdis;
Tim Harvey86b75322016-05-24 11:03:56 -0700[diff] [blame]76 int msata_en;
Tim Harvey2cb61c12016-07-15 07:14:22 -0700[diff] [blame]77 int rs232_en;
Tim Harvey9b9e75f2017-03-13 08:51:07 -0700[diff] [blame]78 int otgpwr_en;
Tim Harveyd7babd42017-03-13 08:51:08 -0700[diff] [blame]79 int vsel_pin;
Tim Harvey63537792017-03-17 07:30:38 -0700[diff] [blame]80 int mmc_cd;
Tim Harvey2cb61c12016-07-15 07:14:22 -0700[diff] [blame]81 /* various features */
Tim Harvey147b5762016-05-24 11:03:59 -0700[diff] [blame]82 bool usd_vsel;
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]83};
84
85extern struct ventana gpio_cfg[GW_UNKNOWN];
86
87/* configure i2c iomux */
88void setup_ventana_i2c(void);
89/* configure uart iomux */
90void setup_iomux_uart(void);
91/* conifgure PMIC */
Tim Harvey195bc972015-05-08 18:28:37 -0700[diff] [blame]92void setup_pmic(void);
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]93/* configure gpio iomux/defaults */
94void setup_iomux_gpio(int board, struct ventana_board_info *);
95/* late setup of GPIO (configuration per baseboard and env) */
96void setup_board_gpio(int board, struct ventana_board_info *);
97
98#endif /* #ifndef _GWVENTANA_COMMON_H_ */