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git01.mediatek.com / filogic / uboot / 1a3732cb2575df75dcf83479a7d69266eff9745a / . / drivers / clk / sunxi / clk_a83t.c
blob: d6f23ddc77815048c5bc08e30cf180d6c1c3dbb6 [file] [log] [blame]
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-a83t-ccu.h>
13#include <dt-bindings/reset/sun8i-a83t-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]15
16static struct ccu_clk_gate a83t_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]23 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
25 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
26 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
27
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]28 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
29 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
30 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
31 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
32 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
33
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]34 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
35 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
36
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]37 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
38 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
39 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
40 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
41 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
42};
43
44static struct ccu_reset a83t_resets[] = {
45 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
46 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
47 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
48
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]49 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
50 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
51 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]52 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]53 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
54 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]55 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
56 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
57 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
58 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]59
60 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
61 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
62 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
63 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
64 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]65};
66
67static const struct ccu_desc a83t_ccu_desc = {
68 .gates = a83t_gates,
69 .resets = a83t_resets,
70};
71
72static int a83t_clk_bind(struct udevice *dev)
73{
74 return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets));
75}
76
77static const struct udevice_id a83t_clk_ids[] = {
78 { .compatible = "allwinner,sun8i-a83t-ccu",
79 .data = (ulong)&a83t_ccu_desc },
80 { }
81};
82
83U_BOOT_DRIVER(clk_sun8i_a83t) = {
84 .name = "sun8i_a83t_ccu",
85 .id = UCLASS_CLK,
86 .of_match = a83t_clk_ids,
87 .priv_auto_alloc_size = sizeof(struct ccu_priv),
88 .ops = &sunxi_clk_ops,
89 .probe = sunxi_clk_probe,
90 .bind = a83t_clk_bind,
91};