Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 1 | # |
| 2 | # USB Host Controller Drivers |
| 3 | # |
| 4 | comment "USB Host Controller Drivers" |
| 5 | |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 6 | config USB_HOST |
| 7 | bool |
Tom Rini | 5b9e616 | 2021-07-09 10:11:56 -0400 | [diff] [blame] | 8 | select DM_USB |
Marek Vasut | 1d5c59c | 2023-05-06 16:42:37 +0200 | [diff] [blame] | 9 | help |
| 10 | Enable access to USB (Universal Serial Bus) host devices so that |
| 11 | SPL can load U-Boot from a connected USB peripheral, such as a USB |
| 12 | flash stick. While USB takes a little longer to start up than most |
| 13 | buses, it is very flexible since many different types of storage |
| 14 | device can be attached. |
| 15 | |
| 16 | config SPL_USB_HOST |
| 17 | bool "Support USB host drivers" |
| 18 | depends on SPL |
| 19 | help |
| 20 | For detailed help see USB_HOST Kconfig symbol. This option enables |
| 21 | the drivers in drivers/usb/host as part of an SPL build. |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 22 | |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 23 | config USB_XHCI_HCD |
| 24 | bool "xHCI HCD (USB 3.0) support" |
Tom Rini | 5b9e616 | 2021-07-09 10:11:56 -0400 | [diff] [blame] | 25 | depends on DM && OF_CONTROL |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 26 | select USB_HOST |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 27 | ---help--- |
| 28 | The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 |
| 29 | "SuperSpeed" host controller hardware. |
| 30 | |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 31 | if USB_XHCI_HCD |
| 32 | |
Masahiro Yamada | d3b72ca | 2016-06-04 07:35:04 +0900 | [diff] [blame] | 33 | config USB_XHCI_DWC3 |
| 34 | bool "DesignWare USB3 DRD Core Support" |
| 35 | help |
| 36 | Say Y or if your system has a Dual Role SuperSpeed |
| 37 | USB controller based on the DesignWare USB3 IP Core. |
| 38 | |
Neil Armstrong | 069421e | 2018-04-11 17:08:00 +0200 | [diff] [blame] | 39 | config USB_XHCI_DWC3_OF_SIMPLE |
| 40 | bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" |
Jean-Jacques Hiblot | 74d9a9d | 2018-04-12 10:41:10 +0200 | [diff] [blame] | 41 | depends on DM_USB |
Mark Kettenis | 06ec913 | 2019-06-30 18:01:54 +0200 | [diff] [blame] | 42 | default y if ARCH_ROCKCHIP |
Jean-Jacques Hiblot | 6c705f4 | 2018-04-12 10:41:11 +0200 | [diff] [blame] | 43 | default y if DRA7XX |
Neil Armstrong | 069421e | 2018-04-11 17:08:00 +0200 | [diff] [blame] | 44 | help |
| 45 | Support USB2/3 functionality in simple SoC integrations with |
| 46 | USB controller based on the DesignWare USB3 IP Core. |
| 47 | |
Tom Rini | 6d772e5 | 2022-06-10 23:03:00 -0400 | [diff] [blame] | 48 | config USB_XHCI_EXYNOS |
| 49 | bool "Support for Samsung Exynos5 family on-chip xHCI USB controller" |
| 50 | depends on ARCH_EXYNOS5 |
| 51 | default y |
| 52 | help |
| 53 | Enables support for he on-chip xHCI controller on Samsung Exynos5 |
| 54 | SoCs. |
| 55 | |
developer | 507fc9b | 2020-05-02 11:35:18 +0200 | [diff] [blame] | 56 | config USB_XHCI_MTK |
| 57 | bool "Support for MediaTek on-chip xHCI USB controller" |
developer | 4adcdca | 2022-05-20 11:22:56 +0800 | [diff] [blame] | 58 | depends on ARCH_MEDIATEK || SOC_MT7621 |
developer | 507fc9b | 2020-05-02 11:35:18 +0200 | [diff] [blame] | 59 | help |
| 60 | Enables support for the on-chip xHCI controller on MediaTek SoCs. |
| 61 | |
Stefan Roese | 07faf11 | 2016-07-14 11:39:20 +0200 | [diff] [blame] | 62 | config USB_XHCI_MVEBU |
| 63 | bool "MVEBU USB 3.0 support" |
| 64 | default y |
| 65 | depends on ARCH_MVEBU |
Konstantin Porotchkin | 1b5ed4d | 2017-02-12 11:10:30 +0200 | [diff] [blame] | 66 | select DM_REGULATOR |
Stefan Roese | 07faf11 | 2016-07-14 11:39:20 +0200 | [diff] [blame] | 67 | help |
| 68 | Choose this option to add support for USB 3.0 driver on mvebu |
| 69 | SoCs, which includes Armada8K, Armada3700 and other Armada |
| 70 | family SoCs. |
| 71 | |
Stefan Roese | df33b57 | 2020-08-24 13:04:38 +0200 | [diff] [blame] | 72 | config USB_XHCI_OCTEON |
| 73 | bool "Support for Marvell Octeon family on-chip xHCI USB controller" |
| 74 | depends on ARCH_OCTEON |
| 75 | default y |
| 76 | help |
| 77 | Enables support for the on-chip xHCI controller on Marvell Octeon |
| 78 | family SoCs. This is a driver for the dwc3 to provide the glue logic |
| 79 | to configure the controller. |
| 80 | |
Tom Rini | ebc1c84 | 2021-09-12 20:32:22 -0400 | [diff] [blame] | 81 | config USB_XHCI_OMAP |
| 82 | bool "Support for TI OMAP family xHCI USB controller" |
| 83 | depends on ARCH_OMAP2PLUS |
| 84 | help |
| 85 | Enables support for the on-chip xHCI controller found on some TI SoC |
| 86 | families. Note that some families have multiple contollers while |
| 87 | others only have something such as DesignWare-based controllers. |
| 88 | Consult the SoC documentation to determine if this option applies |
| 89 | to your hardware. |
| 90 | |
Bin Meng | d34d6fc | 2017-07-19 21:50:08 +0800 | [diff] [blame] | 91 | config USB_XHCI_PCI |
| 92 | bool "Support for PCI-based xHCI USB controller" |
Heinrich Schuchardt | 9c83bad | 2023-11-20 15:56:36 +0100 | [diff] [blame] | 93 | depends on DM_USB && PCI |
Bin Meng | d34d6fc | 2017-07-19 21:50:08 +0800 | [diff] [blame] | 94 | default y if X86 |
| 95 | help |
| 96 | Enables support for the PCI-based xHCI controller. |
| 97 | |
Marek Vasut | 2425727 | 2017-10-15 15:01:29 +0200 | [diff] [blame] | 98 | config USB_XHCI_RCAR |
| 99 | bool "Renesas RCar USB 3.0 support" |
| 100 | default y |
| 101 | depends on ARCH_RMOBILE |
| 102 | help |
| 103 | Choose this option to add support for USB 3.0 driver on Renesas |
| 104 | RCar Gen3 SoCs. |
| 105 | |
Patrice Chotard | f2505b1 | 2017-09-05 11:04:24 +0200 | [diff] [blame] | 106 | config USB_XHCI_STI |
| 107 | bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" |
| 108 | depends on ARCH_STI |
| 109 | default y |
| 110 | help |
| 111 | Enables support for the on-chip xHCI controller on STMicroelectronics |
| 112 | STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic |
| 113 | to configure the controller. |
| 114 | |
Uri Mashiach | f6ff74e | 2017-02-23 15:39:36 +0200 | [diff] [blame] | 115 | config USB_XHCI_DRA7XX_INDEX |
| 116 | int "DRA7XX xHCI USB index" |
| 117 | range 0 1 |
| 118 | default 0 |
| 119 | depends on DRA7XX |
| 120 | help |
| 121 | Select the DRA7XX xHCI USB index. |
| 122 | Current supported values: 0, 1. |
| 123 | |
Ran Wang | a5a9735 | 2017-10-23 10:09:22 +0800 | [diff] [blame] | 124 | config USB_XHCI_FSL |
| 125 | bool "Support for NXP Layerscape on-chip xHCI USB controller" |
| 126 | default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2 |
| 127 | depends on !SPL_NO_USB |
| 128 | help |
| 129 | Enables support for the on-chip xHCI controller on NXP Layerscape SoCs. |
Rayagonda Kokatanur | f59d24e | 2020-04-09 09:23:15 +0530 | [diff] [blame] | 130 | |
| 131 | config USB_XHCI_BRCM |
| 132 | bool "Broadcom USB3 Host XHCI controller" |
| 133 | depends on DM_USB |
| 134 | help |
| 135 | USB controller based on the Broadcom USB3 IP Core. |
| 136 | Supports USB2/3 functionality. |
| 137 | |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 138 | endif # USB_XHCI_HCD |
Alexey Brodkin | 83fd312 | 2015-12-14 17:18:50 +0300 | [diff] [blame] | 139 | |
Tom Rini | 21ad280 | 2022-06-08 08:24:26 -0400 | [diff] [blame] | 140 | config EHCI_DESC_BIG_ENDIAN |
| 141 | bool |
| 142 | |
| 143 | config EHCI_MMIO_BIG_ENDIAN |
| 144 | bool |
| 145 | |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 146 | config USB_EHCI_HCD |
| 147 | bool "EHCI HCD (USB 2.0) support" |
Tom Rini | 7716cd6 | 2017-05-12 22:33:28 -0400 | [diff] [blame] | 148 | default y if ARCH_MX5 || ARCH_MX6 |
Tom Rini | 5b9e616 | 2021-07-09 10:11:56 -0400 | [diff] [blame] | 149 | depends on DM && OF_CONTROL |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 150 | select USB_HOST |
Tom Rini | 21ad280 | 2022-06-08 08:24:26 -0400 | [diff] [blame] | 151 | select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN |
| 152 | select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 153 | ---help--- |
| 154 | The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 |
| 155 | "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. |
| 156 | If your USB host controller supports USB 2.0, you will likely want to |
| 157 | configure this Host Controller Driver. |
| 158 | |
| 159 | EHCI controllers are packaged with "companion" host controllers (OHCI |
| 160 | or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports |
| 161 | will connect to EHCI if the device is high speed, otherwise they |
| 162 | connect to a companion controller. If you configure EHCI, you should |
| 163 | probably configure the OHCI (for NEC and some other vendors) USB Host |
| 164 | Controller Driver or UHCI (for Via motherboards) Host Controller |
| 165 | Driver too. |
| 166 | |
| 167 | You may want to read <file:Documentation/usb/ehci.txt>. |
| 168 | |
Masahiro Yamada | 1b0a06b | 2014-11-07 18:48:31 +0900 | [diff] [blame] | 169 | if USB_EHCI_HCD |
| 170 | |
Marek Behún | e148926 | 2021-10-09 15:27:35 +0200 | [diff] [blame] | 171 | config USB_EHCI_IS_TDI |
| 172 | bool |
| 173 | |
Wenyou Yang | 11e2665 | 2016-08-05 08:57:35 +0800 | [diff] [blame] | 174 | config USB_EHCI_ATMEL |
| 175 | bool "Support for Atmel on-chip EHCI USB controller" |
| 176 | depends on ARCH_AT91 |
| 177 | default y |
| 178 | ---help--- |
| 179 | Enables support for the on-chip EHCI controller on Atmel chips. |
| 180 | |
Tom Rini | 6d772e5 | 2022-06-10 23:03:00 -0400 | [diff] [blame] | 181 | config USB_EHCI_EXYNOS |
| 182 | bool "Support for Samsung Exynos EHCI USB controller" |
| 183 | depends on ARCH_EXYNOS |
| 184 | default y |
| 185 | ---help--- |
| 186 | Enables support for the on-chip EHCI controller on Samsung Exynos |
| 187 | SoCs. |
| 188 | |
Stefan Roese | 0390102 | 2015-09-01 11:39:44 +0200 | [diff] [blame] | 189 | config USB_EHCI_MARVELL |
Tom Rini | 496a417 | 2017-05-12 22:33:29 -0400 | [diff] [blame] | 190 | bool "Support for Marvell on-chip EHCI USB controller" |
Trevor Woerner | bb7ab07 | 2020-05-06 08:02:40 -0400 | [diff] [blame] | 191 | depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X |
Stefan Roese | 0390102 | 2015-09-01 11:39:44 +0200 | [diff] [blame] | 192 | default y |
Marek Behún | e148926 | 2021-10-09 15:27:35 +0200 | [diff] [blame] | 193 | select USB_EHCI_IS_TDI if !ARM64 |
Chris Packham | 927671e | 2022-11-05 17:23:57 +1300 | [diff] [blame] | 194 | select USB_EHCI_IS_TDI if ALLEYCAT_5 |
Stefan Roese | 0390102 | 2015-09-01 11:39:44 +0200 | [diff] [blame] | 195 | ---help--- |
| 196 | Enables support for the on-chip EHCI controller on MVEBU SoCs. |
| 197 | |
Lukasz Majewski | 6fccaf2 | 2019-04-04 12:26:55 +0200 | [diff] [blame] | 198 | config USB_EHCI_MX5 |
| 199 | bool "Support for i.MX5 on-chip EHCI USB controller" |
| 200 | depends on ARCH_MX5 |
Lukasz Majewski | 6fccaf2 | 2019-04-04 12:26:55 +0200 | [diff] [blame] | 201 | help |
| 202 | Enables support for the on-chip EHCI controller on i.MX5 SoCs. |
| 203 | |
Nikita Kiryanov | 9924103 | 2015-07-23 17:19:35 +0300 | [diff] [blame] | 204 | config USB_EHCI_MX6 |
Ye Li | 9da57ea | 2019-10-24 10:29:32 -0300 | [diff] [blame] | 205 | bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller" |
Giulio Benetti | 13ded2c | 2021-05-20 16:10:15 +0200 | [diff] [blame] | 206 | depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT |
Tom Rini | 21ad280 | 2022-06-08 08:24:26 -0400 | [diff] [blame] | 207 | select EHCI_HCD_INIT_AFTER_RESET |
Nikita Kiryanov | 9924103 | 2015-07-23 17:19:35 +0300 | [diff] [blame] | 208 | default y |
| 209 | ---help--- |
| 210 | Enables support for the on-chip EHCI controller on i.MX6 SoCs. |
| 211 | |
Stefan Agner | 100fe07 | 2016-07-13 00:25:36 -0700 | [diff] [blame] | 212 | config USB_EHCI_MX7 |
| 213 | bool "Support for i.MX7 on-chip EHCI USB controller" |
Marek Vasut | e15971f | 2021-04-02 14:07:22 +0200 | [diff] [blame] | 214 | depends on ARCH_MX7 || IMX8M |
Tom Rini | 21ad280 | 2022-06-08 08:24:26 -0400 | [diff] [blame] | 215 | select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7 |
Marek Vasut | e15971f | 2021-04-02 14:07:22 +0200 | [diff] [blame] | 216 | select PHY if IMX8M |
| 217 | select NOP_PHY if IMX8M |
Stefan Agner | 100fe07 | 2016-07-13 00:25:36 -0700 | [diff] [blame] | 218 | default y |
| 219 | ---help--- |
| 220 | Enables support for the on-chip EHCI controller on i.MX7 SoCs. |
| 221 | |
Marek Behún | 53d5351 | 2021-10-09 15:27:33 +0200 | [diff] [blame] | 222 | config USB_EHCI_MXS |
Lukasz Majewski | 7a4aba6 | 2021-12-22 10:55:06 +0100 | [diff] [blame] | 223 | bool "Support for i.MX23/i.MX28 EHCI USB controller" |
| 224 | depends on ARCH_MX23 || ARCH_MX28 |
Marek Behún | 53d5351 | 2021-10-09 15:27:33 +0200 | [diff] [blame] | 225 | default y |
Marek Behún | e148926 | 2021-10-09 15:27:35 +0200 | [diff] [blame] | 226 | select USB_EHCI_IS_TDI |
Marek Behún | 53d5351 | 2021-10-09 15:27:33 +0200 | [diff] [blame] | 227 | help |
Lukasz Majewski | 7a4aba6 | 2021-12-22 10:55:06 +0100 | [diff] [blame] | 228 | Enables support for the on-chip EHCI controller on i.MX23 and |
| 229 | i.MX28 SoCs. |
Marek Behún | 53d5351 | 2021-10-09 15:27:33 +0200 | [diff] [blame] | 230 | |
Jim Liu | 1fd3b3d | 2022-06-21 17:09:02 +0800 | [diff] [blame] | 231 | config USB_EHCI_NPCM |
| 232 | bool "Support for Nuvoton NPCM on-chip EHCI USB controller" |
| 233 | depends on ARCH_NPCM |
Jim Liu | 1fd3b3d | 2022-06-21 17:09:02 +0800 | [diff] [blame] | 234 | ---help--- |
| 235 | Enables support for the on-chip EHCI controller on |
| 236 | Nuvoton NPCM chips. |
| 237 | |
Tom Rini | 639a840 | 2017-05-12 22:33:30 -0400 | [diff] [blame] | 238 | config USB_EHCI_OMAP |
| 239 | bool "Support for OMAP3+ on-chip EHCI USB controller" |
| 240 | depends on ARCH_OMAP2PLUS |
Adam Ford | cb9a356 | 2022-02-19 17:08:44 -0600 | [diff] [blame] | 241 | select PHY |
| 242 | imply NOP_PHY |
Tom Rini | 639a840 | 2017-05-12 22:33:30 -0400 | [diff] [blame] | 243 | default y |
| 244 | ---help--- |
| 245 | Enables support for the on-chip EHCI controller on OMAP3 and later |
| 246 | SoCs. |
| 247 | |
Marcel Ziswiler | 31f4495 | 2019-03-25 17:24:54 +0100 | [diff] [blame] | 248 | config USB_EHCI_VF |
| 249 | bool "Support for Vybrid on-chip EHCI USB controller" |
| 250 | depends on ARCH_VF610 |
| 251 | default y |
| 252 | help |
| 253 | Enables support for the on-chip EHCI controller on Vybrid SoCs. |
| 254 | |
Ye Li | 9da57ea | 2019-10-24 10:29:32 -0300 | [diff] [blame] | 255 | if USB_EHCI_MX6 || USB_EHCI_MX7 |
Stefan Agner | 8652ce9 | 2016-07-13 00:25:38 -0700 | [diff] [blame] | 256 | |
| 257 | config MXC_USB_OTG_HACTIVE |
| 258 | bool "USB Power pin high active" |
| 259 | ---help--- |
| 260 | Set the USB Power pin polarity to be high active (PWR_POL) |
| 261 | |
| 262 | endif |
| 263 | |
Mateusz Kulikowski | dc38117 | 2016-03-31 23:12:26 +0200 | [diff] [blame] | 264 | config USB_EHCI_MSM |
| 265 | bool "Support for Qualcomm on-chip EHCI USB controller" |
| 266 | depends on DM_USB |
| 267 | select USB_ULPI_VIEWPORT |
Ramon Fried | 7e36596 | 2018-09-21 13:35:50 +0300 | [diff] [blame] | 268 | select MSM8916_USB_PHY |
Mateusz Kulikowski | dc38117 | 2016-03-31 23:12:26 +0200 | [diff] [blame] | 269 | ---help--- |
| 270 | Enables support for the on-chip EHCI controller on Qualcomm |
| 271 | Snapdragon SoCs. |
Mateusz Kulikowski | dc38117 | 2016-03-31 23:12:26 +0200 | [diff] [blame] | 272 | |
Bin Meng | ec4b573 | 2017-08-09 00:21:54 -0700 | [diff] [blame] | 273 | config USB_EHCI_PCI |
| 274 | bool "Support for PCI-based EHCI USB controller" |
| 275 | default y if X86 |
| 276 | help |
| 277 | Enables support for the PCI-based EHCI controller. |
| 278 | |
Peter Robinson | 43ecef4 | 2019-02-20 12:17:27 +0000 | [diff] [blame] | 279 | config USB_EHCI_TEGRA |
| 280 | bool "Support for NVIDIA Tegra on-chip EHCI USB controller" |
Trevor Woerner | 513f640 | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 281 | depends on ARCH_TEGRA |
Marek Behún | e148926 | 2021-10-09 15:27:35 +0200 | [diff] [blame] | 282 | select USB_EHCI_IS_TDI |
Peter Robinson | 43ecef4 | 2019-02-20 12:17:27 +0000 | [diff] [blame] | 283 | ---help--- |
| 284 | Enable support for Tegra on-chip EHCI USB controller |
| 285 | |
Siva Durga Prasad Paladugu | 42fcc18 | 2016-07-22 14:51:51 +0530 | [diff] [blame] | 286 | config USB_EHCI_ZYNQ |
| 287 | bool "Support for Xilinx Zynq on-chip EHCI USB controller" |
Michal Simek | 3239d71 | 2020-08-24 14:41:51 +0200 | [diff] [blame] | 288 | default y if ARCH_ZYNQ |
Marek Behún | e148926 | 2021-10-09 15:27:35 +0200 | [diff] [blame] | 289 | select USB_EHCI_IS_TDI |
Siva Durga Prasad Paladugu | 42fcc18 | 2016-07-22 14:51:51 +0530 | [diff] [blame] | 290 | ---help--- |
| 291 | Enable support for Zynq on-chip EHCI USB controller |
| 292 | |
Alexey Brodkin | a6aff43 | 2015-12-02 12:32:02 +0300 | [diff] [blame] | 293 | config USB_EHCI_GENERIC |
| 294 | bool "Support for generic EHCI USB controller" |
Alexey Brodkin | a6aff43 | 2015-12-02 12:32:02 +0300 | [diff] [blame] | 295 | depends on DM_USB |
Jagan Teki | 1ba41e1 | 2018-12-22 18:18:10 +0530 | [diff] [blame] | 296 | default ARCH_SUNXI |
Alexey Brodkin | a6aff43 | 2015-12-02 12:32:02 +0300 | [diff] [blame] | 297 | ---help--- |
| 298 | Enables support for generic EHCI controller. |
| 299 | |
Tom Rini | 30fd3d9 | 2022-06-08 08:24:27 -0400 | [diff] [blame] | 300 | config EHCI_HCD_INIT_AFTER_RESET |
| 301 | bool |
| 302 | |
Ran Wang | 9798b66 | 2017-12-20 10:34:20 +0800 | [diff] [blame] | 303 | config USB_EHCI_FSL |
| 304 | bool "Support for FSL on-chip EHCI USB controller" |
Tom Rini | 30fd3d9 | 2022-06-08 08:24:27 -0400 | [diff] [blame] | 305 | select EHCI_HCD_INIT_AFTER_RESET |
Tom Rini | 8d7aa57 | 2022-07-31 21:08:29 -0400 | [diff] [blame] | 306 | select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \ |
| 307 | !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020) |
Ran Wang | 9798b66 | 2017-12-20 10:34:20 +0800 | [diff] [blame] | 308 | ---help--- |
| 309 | Enables support for the on-chip EHCI controller on FSL chips. |
Tom Rini | c85a792 | 2022-06-08 08:24:31 -0400 | [diff] [blame] | 310 | |
Tom Rini | 8d7aa57 | 2022-07-31 21:08:29 -0400 | [diff] [blame] | 311 | config SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 312 | bool |
| 313 | depends on USB_EHCI_FSL |
| 314 | |
Tom Rini | c85a792 | 2022-06-08 08:24:31 -0400 | [diff] [blame] | 315 | config USB_EHCI_TXFIFO_THRESH |
| 316 | hex |
| 317 | depends on USB_EHCI_TEGRA |
| 318 | default 0x10 |
| 319 | help |
| 320 | This parameter affects a TXFILLTUNING field that controls how much |
| 321 | data is sent to the latency fifo before it is sent to the wire. |
| 322 | Without this parameter, the default (2) causes occasional Data Buffer |
| 323 | Errors in OUT packets depending on the buffer address and size. |
| 324 | |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 325 | endif # USB_EHCI_HCD |
| 326 | |
Tom Rini | 112d2e0 | 2022-06-25 11:02:31 -0400 | [diff] [blame] | 327 | config USB_OHCI_NEW |
| 328 | bool |
| 329 | |
| 330 | config SYS_USB_OHCI_CPU_INIT |
| 331 | bool |
| 332 | |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 333 | config USB_OHCI_HCD |
| 334 | bool "OHCI HCD (USB 1.1) support" |
Tom Rini | 5b9e616 | 2021-07-09 10:11:56 -0400 | [diff] [blame] | 335 | depends on DM && OF_CONTROL |
| 336 | select USB_HOST |
Tom Rini | 112d2e0 | 2022-06-25 11:02:31 -0400 | [diff] [blame] | 337 | select USB_OHCI_NEW |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 338 | ---help--- |
| 339 | The Open Host Controller Interface (OHCI) is a standard for accessing |
| 340 | USB 1.1 host controller hardware. It does more in hardware than Intel's |
| 341 | UHCI specification. If your USB host controller follows the OHCI spec, |
| 342 | say Y. On most non-x86 systems, and on x86 hardware that's not using a |
| 343 | USB controller from Intel or VIA, this is appropriate. If your host |
| 344 | controller doesn't use PCI, this is probably appropriate. For a PCI |
| 345 | based system where you're not sure, the "lspci -v" entry will list the |
| 346 | right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI. |
| 347 | |
Tom Rini | 5b9e616 | 2021-07-09 10:11:56 -0400 | [diff] [blame] | 348 | if USB_OHCI_HCD |
| 349 | |
Heiko Schocher | 124f947 | 2019-07-16 10:49:07 +0200 | [diff] [blame] | 350 | config USB_OHCI_PCI |
| 351 | bool "Support for PCI-based OHCI USB controller" |
Tom Rini | 5b9e616 | 2021-07-09 10:11:56 -0400 | [diff] [blame] | 352 | depends on PCI |
Heiko Schocher | 124f947 | 2019-07-16 10:49:07 +0200 | [diff] [blame] | 353 | help |
| 354 | Enables support for the PCI-based OHCI controller. |
| 355 | |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 356 | config USB_OHCI_GENERIC |
| 357 | bool "Support for generic OHCI USB controller" |
Jagan Teki | 1ba41e1 | 2018-12-22 18:18:10 +0530 | [diff] [blame] | 358 | default ARCH_SUNXI |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 359 | ---help--- |
| 360 | Enables support for generic OHCI controller. |
| 361 | |
Adam Ford | 5f364f5 | 2019-04-30 05:21:41 -0500 | [diff] [blame] | 362 | config USB_OHCI_DA8XX |
| 363 | bool "Support for da850 OHCI USB controller" |
| 364 | help |
| 365 | Enable support for the da850 USB controller. |
| 366 | |
Jim Liu | 1fd3b3d | 2022-06-21 17:09:02 +0800 | [diff] [blame] | 367 | config USB_OHCI_NPCM |
| 368 | bool "Support for Nuvoton NPCM on-chip OHCI USB controller" |
| 369 | depends on ARCH_NPCM |
Jim Liu | 1fd3b3d | 2022-06-21 17:09:02 +0800 | [diff] [blame] | 370 | ---help--- |
| 371 | Enables support for the on-chip OHCI controller on |
| 372 | Nuvoton NPCM chips. |
| 373 | |
Masahiro Yamada | 78a9c79 | 2016-08-01 00:16:32 +0900 | [diff] [blame] | 374 | endif # USB_OHCI_HCD |
Masahiro Yamada | 718ba3c | 2016-08-01 00:16:33 +0900 | [diff] [blame] | 375 | |
Tom Rini | 112d2e0 | 2022-06-25 11:02:31 -0400 | [diff] [blame] | 376 | config SYS_USB_OHCI_SLOT_NAME |
| 377 | string "Display name for the OHCI controller" |
| 378 | depends on USB_OHCI_NEW && !DM_USB |
| 379 | |
Tom Rini | 112d2e0 | 2022-06-25 11:02:31 -0400 | [diff] [blame] | 380 | config SYS_OHCI_SWAP_REG_ACCESS |
| 381 | bool "Perform byte swapping on OHCI controller register accesses" |
| 382 | depends on USB_OHCI_NEW |
| 383 | |
Masahiro Yamada | 718ba3c | 2016-08-01 00:16:33 +0900 | [diff] [blame] | 384 | config USB_UHCI_HCD |
| 385 | bool "UHCI HCD (most Intel and VIA) support" |
Masahiro Yamada | 59cfdc0 | 2016-08-01 00:16:34 +0900 | [diff] [blame] | 386 | select USB_HOST |
Masahiro Yamada | 718ba3c | 2016-08-01 00:16:33 +0900 | [diff] [blame] | 387 | ---help--- |
| 388 | The Universal Host Controller Interface is a standard by Intel for |
| 389 | accessing the USB hardware in the PC (which is also called the USB |
| 390 | host controller). If your USB host controller conforms to this |
| 391 | standard, you may want to say Y, but see below. All recent boards |
| 392 | with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, |
| 393 | i810, i820) conform to this standard. Also all VIA PCI chipsets |
| 394 | (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro |
| 395 | 133) and LEON/GRLIB SoCs with the GRUSBHC controller. |
| 396 | If unsure, say Y. |
| 397 | |
| 398 | if USB_UHCI_HCD |
| 399 | |
| 400 | endif # USB_UHCI_HCD |
Philipp Tomsich | 5498381 | 2017-07-03 18:30:06 +0200 | [diff] [blame] | 401 | |
| 402 | config USB_DWC2 |
| 403 | bool "DesignWare USB2 Core support" |
Tom Rini | 5b9e616 | 2021-07-09 10:11:56 -0400 | [diff] [blame] | 404 | depends on DM && OF_CONTROL |
Philipp Tomsich | 5498381 | 2017-07-03 18:30:06 +0200 | [diff] [blame] | 405 | select USB_HOST |
| 406 | ---help--- |
| 407 | The DesignWare USB 2.0 controller is compliant with the |
| 408 | USB-Implementers Forum (USB-IF) USB 2.0 specifications. |
| 409 | Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) |
| 410 | operation is compliant to the controller Supplement. If you want to |
| 411 | enable this controller in host mode, say Y. |
Alexey Brodkin | f19414b | 2018-02-28 16:16:58 +0300 | [diff] [blame] | 412 | |
| 413 | if USB_DWC2 |
| 414 | config USB_DWC2_BUFFER_SIZE |
| 415 | int "Data buffer size in kB" |
| 416 | default 64 |
| 417 | ---help--- |
| 418 | By default 64 kB buffer is used but if amount of RAM avaialble on |
| 419 | the target is not enough to accommodate allocation of buffer of |
| 420 | that size it is possible to shrink it. Smaller sizes should be fine |
| 421 | because larger transactions could be split in smaller ones. |
| 422 | |
| 423 | endif # USB_DWC2 |
Marek Vasut | 8801603 | 2019-08-11 13:23:43 +0200 | [diff] [blame] | 424 | |
| 425 | config USB_R8A66597_HCD |
| 426 | bool "Renesas R8A66597 USB Core support" |
Tom Rini | 5b9e616 | 2021-07-09 10:11:56 -0400 | [diff] [blame] | 427 | depends on DM && OF_CONTROL |
Marek Vasut | 8801603 | 2019-08-11 13:23:43 +0200 | [diff] [blame] | 428 | select USB_HOST |
| 429 | ---help--- |
| 430 | This enables support for the on-chip Renesas R8A66597 USB 2.0 |
| 431 | controller, present in various RZ and SH SoCs. |
Tom Rini | bde2170 | 2022-06-12 20:02:04 -0400 | [diff] [blame] | 432 | |
Tom Rini | 112d2e0 | 2022-06-25 11:02:31 -0400 | [diff] [blame] | 433 | config USB_ATMEL |
| 434 | bool "AT91 OHCI USB support" |
| 435 | depends on ARCH_AT91 |
| 436 | select SYS_USB_OHCI_CPU_INIT |
| 437 | select USB_OHCI_NEW |
| 438 | |
| 439 | choice |
| 440 | prompt "Clock for OHCI" |
| 441 | depends on USB_ATMEL |
| 442 | |
| 443 | config USB_ATMEL_CLK_SEL_PLLB |
| 444 | bool "PLLB" |
| 445 | |
| 446 | config USB_ATMEL_CLK_SEL_UPLL |
| 447 | bool "UPLL" |
| 448 | |
| 449 | endchoice |
| 450 | |
| 451 | config USB_OHCI_LPC32XX |
| 452 | bool "LPC32xx USB OHCI support" |
| 453 | depends on ARCH_LPC32XX |
| 454 | select SYS_USB_OHCI_CPU_INIT |
| 455 | select USB_OHCI_NEW |
| 456 | |
Tom Rini | bde2170 | 2022-06-12 20:02:04 -0400 | [diff] [blame] | 457 | config USB_MAX_CONTROLLER_COUNT |
| 458 | int "Maximum number of USB host controllers" |
| 459 | depends on USB_EHCI_FSL || USB_XHCI_FSL || \ |
| 460 | (SPL_USB_HOST && !DM_SPL_USB) || (USB_HOST && !DM_USB) |
| 461 | default 1 |