Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 2 | /* |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 3 | * (C) Copyright 2009 Industrie Dial Face S.p.A. |
| 4 | * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> |
| 5 | * |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 6 | * (C) Copyright 2001 |
| 7 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * This provides a bit-banged interface to the ethernet MII management |
| 12 | * channel. |
| 13 | */ |
| 14 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 15 | #include <ioports.h> |
| 16 | #include <ppc_asm.tmpl> |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 17 | #include <miiphy.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 18 | #include <asm/global_data.h> |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 19 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 20 | /***************************************************************************** |
| 21 | * |
| 22 | * Utility to send the preamble, address, and register (common to read |
| 23 | * and write). |
| 24 | */ |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 25 | static void miiphy_pre(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, |
Marek Vasut | 3d5149c | 2025-03-02 02:24:42 +0100 | [diff] [blame] | 26 | char read, unsigned char addr, unsigned char reg) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 27 | { |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 28 | int j; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 29 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 30 | /* |
| 31 | * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure. |
| 32 | * The IEEE spec says this is a PHY optional requirement. The AMD |
| 33 | * 79C874 requires one after power up and one after a MII communications |
| 34 | * error. This means that we are doing more preambles than we need, |
| 35 | * but it is safer and will be much more robust. |
| 36 | */ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 37 | |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 38 | ops->mdio_active(miidev); |
| 39 | ops->set_mdio(miidev, 1); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 40 | for (j = 0; j < 32; j++) { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 41 | ops->set_mdc(miidev, 0); |
| 42 | ops->delay(miidev); |
| 43 | ops->set_mdc(miidev, 1); |
| 44 | ops->delay(miidev); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 45 | } |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 46 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 47 | /* send the start bit (01) and the read opcode (10) or write (10) */ |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 48 | ops->set_mdc(miidev, 0); |
| 49 | ops->set_mdio(miidev, 0); |
| 50 | ops->delay(miidev); |
| 51 | ops->set_mdc(miidev, 1); |
| 52 | ops->delay(miidev); |
| 53 | ops->set_mdc(miidev, 0); |
| 54 | ops->set_mdio(miidev, 1); |
| 55 | ops->delay(miidev); |
| 56 | ops->set_mdc(miidev, 1); |
| 57 | ops->delay(miidev); |
| 58 | ops->set_mdc(miidev, 0); |
| 59 | ops->set_mdio(miidev, read); |
| 60 | ops->delay(miidev); |
| 61 | ops->set_mdc(miidev, 1); |
| 62 | ops->delay(miidev); |
| 63 | ops->set_mdc(miidev, 0); |
| 64 | ops->set_mdio(miidev, !read); |
| 65 | ops->delay(miidev); |
| 66 | ops->set_mdc(miidev, 1); |
| 67 | ops->delay(miidev); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 68 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 69 | /* send the PHY address */ |
| 70 | for (j = 0; j < 5; j++) { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 71 | ops->set_mdc(miidev, 0); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 72 | if ((addr & 0x10) == 0) { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 73 | ops->set_mdio(miidev, 0); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 74 | } else { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 75 | ops->set_mdio(miidev, 1); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 76 | } |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 77 | ops->delay(miidev); |
| 78 | ops->set_mdc(miidev, 1); |
| 79 | ops->delay(miidev); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 80 | addr <<= 1; |
| 81 | } |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 82 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 83 | /* send the register address */ |
| 84 | for (j = 0; j < 5; j++) { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 85 | ops->set_mdc(miidev, 0); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 86 | if ((reg & 0x10) == 0) { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 87 | ops->set_mdio(miidev, 0); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 88 | } else { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 89 | ops->set_mdio(miidev, 1); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 90 | } |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 91 | ops->delay(miidev); |
| 92 | ops->set_mdc(miidev, 1); |
| 93 | ops->delay(miidev); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 94 | reg <<= 1; |
| 95 | } |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 96 | } |
| 97 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 98 | /***************************************************************************** |
| 99 | * |
| 100 | * Read a MII PHY register. |
| 101 | * |
| 102 | * Returns: |
| 103 | * 0 on success |
| 104 | */ |
Marek Vasut | 65867d3 | 2025-03-02 02:24:44 +0100 | [diff] [blame] | 105 | int bb_miiphy_read(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, |
| 106 | int addr, int devad, int reg) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 107 | { |
Chris Brandt | 7e4d4d1 | 2017-11-03 08:30:13 -0500 | [diff] [blame] | 108 | unsigned short rdreg; /* register working value */ |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 109 | int v; |
| 110 | int j; /* counter */ |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 111 | |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 112 | miiphy_pre(miidev, ops, 1, addr, reg); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 113 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 114 | /* tri-state our MDIO I/O pin so we can read */ |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 115 | ops->set_mdc(miidev, 0); |
| 116 | ops->mdio_tristate(miidev); |
| 117 | ops->delay(miidev); |
| 118 | ops->set_mdc(miidev, 1); |
| 119 | ops->delay(miidev); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 120 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 121 | /* check the turnaround bit: the PHY should be driving it to zero */ |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 122 | ops->get_mdio(miidev, &v); |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 123 | if (v != 0) { |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 124 | /* puts ("PHY didn't drive TA low\n"); */ |
| 125 | for (j = 0; j < 32; j++) { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 126 | ops->set_mdc(miidev, 0); |
| 127 | ops->delay(miidev); |
| 128 | ops->set_mdc(miidev, 1); |
| 129 | ops->delay(miidev); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 130 | } |
Joe Hershberger | 0c33319 | 2016-08-08 11:28:39 -0500 | [diff] [blame] | 131 | /* There is no PHY, return */ |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 132 | return -1; |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 133 | } |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 134 | |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 135 | ops->set_mdc(miidev, 0); |
| 136 | ops->delay(miidev); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 137 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 138 | /* read 16 bits of register data, MSB first */ |
| 139 | rdreg = 0; |
| 140 | for (j = 0; j < 16; j++) { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 141 | ops->set_mdc(miidev, 1); |
| 142 | ops->delay(miidev); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 143 | rdreg <<= 1; |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 144 | ops->get_mdio(miidev, &v); |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 145 | rdreg |= (v & 0x1); |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 146 | ops->set_mdc(miidev, 0); |
| 147 | ops->delay(miidev); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 148 | } |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 149 | |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 150 | ops->set_mdc(miidev, 1); |
| 151 | ops->delay(miidev); |
| 152 | ops->set_mdc(miidev, 0); |
| 153 | ops->delay(miidev); |
| 154 | ops->set_mdc(miidev, 1); |
| 155 | ops->delay(miidev); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 156 | |
Marek Vasut | 06effa2 | 2025-01-25 13:28:30 +0100 | [diff] [blame] | 157 | debug("%s[%s](0x%x) @ 0x%x = 0x%04x\n", __func__, miidev->name, reg, addr, rdreg); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 158 | |
Joe Hershberger | 0c33319 | 2016-08-08 11:28:39 -0500 | [diff] [blame] | 159 | return rdreg; |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 160 | } |
| 161 | |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 162 | /***************************************************************************** |
| 163 | * |
| 164 | * Write a MII PHY register. |
| 165 | * |
| 166 | * Returns: |
| 167 | * 0 on success |
| 168 | */ |
Marek Vasut | 65867d3 | 2025-03-02 02:24:44 +0100 | [diff] [blame] | 169 | int bb_miiphy_write(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, |
| 170 | int addr, int devad, int reg, u16 value) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 171 | { |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 172 | int j; /* counter */ |
Luigi 'Comio' Mantellini | 466827e | 2009-10-10 12:42:20 +0200 | [diff] [blame] | 173 | |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 174 | miiphy_pre(miidev, ops, 0, addr, reg); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 175 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 176 | /* send the turnaround (10) */ |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 177 | ops->set_mdc(miidev, 0); |
| 178 | ops->set_mdio(miidev, 1); |
| 179 | ops->delay(miidev); |
| 180 | ops->set_mdc(miidev, 1); |
| 181 | ops->delay(miidev); |
| 182 | ops->set_mdc(miidev, 0); |
| 183 | ops->set_mdio(miidev, 0); |
| 184 | ops->delay(miidev); |
| 185 | ops->set_mdc(miidev, 1); |
| 186 | ops->delay(miidev); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 187 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 188 | /* write 16 bits of register data, MSB first */ |
| 189 | for (j = 0; j < 16; j++) { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 190 | ops->set_mdc(miidev, 0); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 191 | if ((value & 0x00008000) == 0) { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 192 | ops->set_mdio(miidev, 0); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 193 | } else { |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 194 | ops->set_mdio(miidev, 1); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 195 | } |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 196 | ops->delay(miidev); |
| 197 | ops->set_mdc(miidev, 1); |
| 198 | ops->delay(miidev); |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 199 | value <<= 1; |
| 200 | } |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 201 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 202 | /* |
| 203 | * Tri-state the MDIO line. |
| 204 | */ |
Marek Vasut | 183c10a | 2025-03-02 02:24:45 +0100 | [diff] [blame] | 205 | ops->mdio_tristate(miidev); |
| 206 | ops->set_mdc(miidev, 0); |
| 207 | ops->delay(miidev); |
| 208 | ops->set_mdc(miidev, 1); |
| 209 | ops->delay(miidev); |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 210 | |
Wolfgang Denk | 7b4e347 | 2005-08-13 02:04:37 +0200 | [diff] [blame] | 211 | return 0; |
Wolfgang Denk | 9235e0c | 2009-10-25 23:00:09 +0100 | [diff] [blame] | 212 | } |