net: miiphybb: Split off struct bb_miiphy_bus_ops
Move miiphybb operations into separate struct bb_miiphy_bus_ops
structure, add pointer to struct bb_miiphy_bus_ops into the base
struct bb_miiphy_bus and access the ops through this pointer in
miiphybb generic code. The variable reshuffling in miiphybb.c
cannot be easily avoided.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index 553af2c..e610634 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -46,8 +46,8 @@
* Utility to send the preamble, address, and register (common to read
* and write).
*/
-static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
- unsigned char addr, unsigned char reg)
+static void miiphy_pre(struct bb_miiphy_bus *bus, const struct bb_miiphy_bus_ops *ops,
+ char read, unsigned char addr, unsigned char reg)
{
int j;
@@ -59,62 +59,62 @@
* but it is safer and will be much more robust.
*/
- bus->mdio_active(bus);
- bus->set_mdio(bus, 1);
+ ops->mdio_active(bus);
+ ops->set_mdio(bus, 1);
for (j = 0; j < 32; j++) {
- bus->set_mdc(bus, 0);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
}
/* send the start bit (01) and the read opcode (10) or write (10) */
- bus->set_mdc(bus, 0);
- bus->set_mdio(bus, 0);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
- bus->set_mdc(bus, 0);
- bus->set_mdio(bus, 1);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
- bus->set_mdc(bus, 0);
- bus->set_mdio(bus, read);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
- bus->set_mdc(bus, 0);
- bus->set_mdio(bus, !read);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->set_mdio(bus, 0);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->set_mdio(bus, 1);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->set_mdio(bus, read);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->set_mdio(bus, !read);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
/* send the PHY address */
for (j = 0; j < 5; j++) {
- bus->set_mdc(bus, 0);
+ ops->set_mdc(bus, 0);
if ((addr & 0x10) == 0) {
- bus->set_mdio(bus, 0);
+ ops->set_mdio(bus, 0);
} else {
- bus->set_mdio(bus, 1);
+ ops->set_mdio(bus, 1);
}
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
addr <<= 1;
}
/* send the register address */
for (j = 0; j < 5; j++) {
- bus->set_mdc(bus, 0);
+ ops->set_mdc(bus, 0);
if ((reg & 0x10) == 0) {
- bus->set_mdio(bus, 0);
+ ops->set_mdio(bus, 0);
} else {
- bus->set_mdio(bus, 1);
+ ops->set_mdio(bus, 1);
}
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
reg <<= 1;
}
}
@@ -132,56 +132,59 @@
int v;
int j; /* counter */
struct bb_miiphy_bus *bus;
+ const struct bb_miiphy_bus_ops *ops;
bus = bb_miiphy_getbus(miidev);
if (bus == NULL) {
return -1;
}
- miiphy_pre (bus, 1, addr, reg);
+ ops = bus->ops;
+
+ miiphy_pre(bus, ops, 1, addr, reg);
/* tri-state our MDIO I/O pin so we can read */
- bus->set_mdc(bus, 0);
- bus->mdio_tristate(bus);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->mdio_tristate(bus);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
/* check the turnaround bit: the PHY should be driving it to zero */
- bus->get_mdio(bus, &v);
+ ops->get_mdio(bus, &v);
if (v != 0) {
/* puts ("PHY didn't drive TA low\n"); */
for (j = 0; j < 32; j++) {
- bus->set_mdc(bus, 0);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
}
/* There is no PHY, return */
return -1;
}
- bus->set_mdc(bus, 0);
- bus->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->delay(bus);
/* read 16 bits of register data, MSB first */
rdreg = 0;
for (j = 0; j < 16; j++) {
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
rdreg <<= 1;
- bus->get_mdio(bus, &v);
+ ops->get_mdio(bus, &v);
rdreg |= (v & 0x1);
- bus->set_mdc(bus, 0);
- bus->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->delay(bus);
}
- bus->set_mdc(bus, 1);
- bus->delay(bus);
- bus->set_mdc(bus, 0);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
debug("%s[%s](0x%x) @ 0x%x = 0x%04x\n", __func__, miidev->name, reg, addr, rdreg);
@@ -199,6 +202,7 @@
u16 value)
{
struct bb_miiphy_bus *bus;
+ const struct bb_miiphy_bus_ops *ops;
int j; /* counter */
bus = bb_miiphy_getbus(miidev);
@@ -207,42 +211,44 @@
return -1;
}
- miiphy_pre (bus, 0, addr, reg);
+ ops = bus->ops;
+
+ miiphy_pre(bus, ops, 0, addr, reg);
/* send the turnaround (10) */
- bus->set_mdc(bus, 0);
- bus->set_mdio(bus, 1);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
- bus->set_mdc(bus, 0);
- bus->set_mdio(bus, 0);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->set_mdio(bus, 1);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
+ ops->set_mdc(bus, 0);
+ ops->set_mdio(bus, 0);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
/* write 16 bits of register data, MSB first */
for (j = 0; j < 16; j++) {
- bus->set_mdc(bus, 0);
+ ops->set_mdc(bus, 0);
if ((value & 0x00008000) == 0) {
- bus->set_mdio(bus, 0);
+ ops->set_mdio(bus, 0);
} else {
- bus->set_mdio(bus, 1);
+ ops->set_mdio(bus, 1);
}
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
value <<= 1;
}
/*
* Tri-state the MDIO line.
*/
- bus->mdio_tristate(bus);
- bus->set_mdc(bus, 0);
- bus->delay(bus);
- bus->set_mdc(bus, 1);
- bus->delay(bus);
+ ops->mdio_tristate(bus);
+ ops->set_mdc(bus, 0);
+ ops->delay(bus);
+ ops->set_mdc(bus, 1);
+ ops->delay(bus);
return 0;
}