net: miiphybb: Pass struct mii_dev directly to bb_miiphy_read/write()
Access to MDIO bus private data can be provided by both
struct mii_dev .priv member and struct bb_miiphy_bus .priv
member, use the former directly and remove .priv from the
later. Drop unused bb_miiphy_getbus(). This removes any
dependency on struct bb_miiphy_bus from the miiphybb code,
except for helper functions which will be removed later.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index 9481ba7..60c791b 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -18,11 +18,6 @@
#include <miiphy.h>
#include <asm/global_data.h>
-static inline struct bb_miiphy_bus *bb_miiphy_getbus(struct mii_dev *miidev)
-{
- return container_of(miidev, struct bb_miiphy_bus, mii);
-}
-
struct bb_miiphy_bus *bb_miiphy_alloc(void)
{
struct bb_miiphy_bus *bus;
@@ -46,7 +41,7 @@
* Utility to send the preamble, address, and register (common to read
* and write).
*/
-static void miiphy_pre(struct bb_miiphy_bus *bus, const struct bb_miiphy_bus_ops *ops,
+static void miiphy_pre(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops,
char read, unsigned char addr, unsigned char reg)
{
int j;
@@ -59,62 +54,62 @@
* but it is safer and will be much more robust.
*/
- ops->mdio_active(bus);
- ops->set_mdio(bus, 1);
+ ops->mdio_active(miidev);
+ ops->set_mdio(miidev, 1);
for (j = 0; j < 32; j++) {
- ops->set_mdc(bus, 0);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->set_mdc(miidev, 0);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
}
/* send the start bit (01) and the read opcode (10) or write (10) */
- ops->set_mdc(bus, 0);
- ops->set_mdio(bus, 0);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
- ops->set_mdc(bus, 0);
- ops->set_mdio(bus, 1);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
- ops->set_mdc(bus, 0);
- ops->set_mdio(bus, read);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
- ops->set_mdc(bus, 0);
- ops->set_mdio(bus, !read);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->set_mdc(miidev, 0);
+ ops->set_mdio(miidev, 0);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 0);
+ ops->set_mdio(miidev, 1);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 0);
+ ops->set_mdio(miidev, read);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 0);
+ ops->set_mdio(miidev, !read);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
/* send the PHY address */
for (j = 0; j < 5; j++) {
- ops->set_mdc(bus, 0);
+ ops->set_mdc(miidev, 0);
if ((addr & 0x10) == 0) {
- ops->set_mdio(bus, 0);
+ ops->set_mdio(miidev, 0);
} else {
- ops->set_mdio(bus, 1);
+ ops->set_mdio(miidev, 1);
}
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
addr <<= 1;
}
/* send the register address */
for (j = 0; j < 5; j++) {
- ops->set_mdc(bus, 0);
+ ops->set_mdc(miidev, 0);
if ((reg & 0x10) == 0) {
- ops->set_mdio(bus, 0);
+ ops->set_mdio(miidev, 0);
} else {
- ops->set_mdio(bus, 1);
+ ops->set_mdio(miidev, 1);
}
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
reg <<= 1;
}
}
@@ -132,57 +127,51 @@
unsigned short rdreg; /* register working value */
int v;
int j; /* counter */
- struct bb_miiphy_bus *bus;
- bus = bb_miiphy_getbus(miidev);
- if (bus == NULL) {
- return -1;
- }
-
- miiphy_pre(bus, ops, 1, addr, reg);
+ miiphy_pre(miidev, ops, 1, addr, reg);
/* tri-state our MDIO I/O pin so we can read */
- ops->set_mdc(bus, 0);
- ops->mdio_tristate(bus);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->set_mdc(miidev, 0);
+ ops->mdio_tristate(miidev);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
/* check the turnaround bit: the PHY should be driving it to zero */
- ops->get_mdio(bus, &v);
+ ops->get_mdio(miidev, &v);
if (v != 0) {
/* puts ("PHY didn't drive TA low\n"); */
for (j = 0; j < 32; j++) {
- ops->set_mdc(bus, 0);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->set_mdc(miidev, 0);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
}
/* There is no PHY, return */
return -1;
}
- ops->set_mdc(bus, 0);
- ops->delay(bus);
+ ops->set_mdc(miidev, 0);
+ ops->delay(miidev);
/* read 16 bits of register data, MSB first */
rdreg = 0;
for (j = 0; j < 16; j++) {
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
rdreg <<= 1;
- ops->get_mdio(bus, &v);
+ ops->get_mdio(miidev, &v);
rdreg |= (v & 0x1);
- ops->set_mdc(bus, 0);
- ops->delay(bus);
+ ops->set_mdc(miidev, 0);
+ ops->delay(miidev);
}
- ops->set_mdc(bus, 1);
- ops->delay(bus);
- ops->set_mdc(bus, 0);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 0);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
debug("%s[%s](0x%x) @ 0x%x = 0x%04x\n", __func__, miidev->name, reg, addr, rdreg);
@@ -199,51 +188,44 @@
int bb_miiphy_write(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops,
int addr, int devad, int reg, u16 value)
{
- struct bb_miiphy_bus *bus;
int j; /* counter */
- bus = bb_miiphy_getbus(miidev);
- if (bus == NULL) {
- /* Bus not found! */
- return -1;
- }
-
- miiphy_pre(bus, ops, 0, addr, reg);
+ miiphy_pre(miidev, ops, 0, addr, reg);
/* send the turnaround (10) */
- ops->set_mdc(bus, 0);
- ops->set_mdio(bus, 1);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
- ops->set_mdc(bus, 0);
- ops->set_mdio(bus, 0);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->set_mdc(miidev, 0);
+ ops->set_mdio(miidev, 1);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 0);
+ ops->set_mdio(miidev, 0);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
/* write 16 bits of register data, MSB first */
for (j = 0; j < 16; j++) {
- ops->set_mdc(bus, 0);
+ ops->set_mdc(miidev, 0);
if ((value & 0x00008000) == 0) {
- ops->set_mdio(bus, 0);
+ ops->set_mdio(miidev, 0);
} else {
- ops->set_mdio(bus, 1);
+ ops->set_mdio(miidev, 1);
}
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
value <<= 1;
}
/*
* Tri-state the MDIO line.
*/
- ops->mdio_tristate(bus);
- ops->set_mdc(bus, 0);
- ops->delay(bus);
- ops->set_mdc(bus, 1);
- ops->delay(bus);
+ ops->mdio_tristate(miidev);
+ ops->set_mdc(miidev, 0);
+ ops->delay(miidev);
+ ops->set_mdc(miidev, 1);
+ ops->delay(miidev);
return 0;
}