blob: 5a6f979f91bc5521544c8ca56eb119a543656358 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Christophe Kerello275f7062017-09-13 18:00:08 +02002/*
Patrice Chotard789ee0e2017-10-23 09:53:58 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
Patrice Chotard5d9950d2020-12-02 18:47:30 +01004 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
Christophe Kerello275f7062017-09-13 18:00:08 +02005 */
6
Patrick Delaunayeec21f32020-11-06 19:01:43 +01007#define LOG_CATEGORY UCLASS_NOP
8
Christophe Kerello275f7062017-09-13 18:00:08 +02009#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Christophe Kerello275f7062017-09-13 18:00:08 +020011#include <misc.h>
Patrice Chotard03f10a12017-11-15 13:14:51 +010012#include <stm32_rcc.h>
13#include <dm/device-internal.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <dm/device_compat.h>
Christophe Kerello275f7062017-09-13 18:00:08 +020015#include <dm/lists.h>
16
Patrice Chotard7264aae2018-04-11 17:07:45 +020017struct stm32_rcc_clk stm32_rcc_clk_f42x = {
Patrice Chotard03f10a12017-11-15 13:14:51 +010018 .drv_name = "stm32fx_rcc_clock",
Patrice Chotard7264aae2018-04-11 17:07:45 +020019 .soc = STM32F42X,
Patrice Chotard03f10a12017-11-15 13:14:51 +010020};
21
Patrice Chotard7264aae2018-04-11 17:07:45 +020022struct stm32_rcc_clk stm32_rcc_clk_f469 = {
23 .drv_name = "stm32fx_rcc_clock",
24 .soc = STM32F469,
25};
26
Patrice Chotard03f10a12017-11-15 13:14:51 +010027struct stm32_rcc_clk stm32_rcc_clk_f7 = {
28 .drv_name = "stm32fx_rcc_clock",
29 .soc = STM32F7,
30};
31
32struct stm32_rcc_clk stm32_rcc_clk_h7 = {
33 .drv_name = "stm32h7_rcc_clock",
34};
35
Patrick Delaunayb139a5b2018-07-09 15:17:20 +020036struct stm32_rcc_clk stm32_rcc_clk_mp1 = {
37 .drv_name = "stm32mp1_clk",
38 .soc = STM32MP1,
39};
40
Patrick Delaunay6b4490c2022-05-19 17:56:46 +020041struct stm32_rcc_clk stm32_rcc_clk_mp13 = {
42 .drv_name = "stm32mp13_clk",
43 .soc = STM32MP1,
44};
45
Christophe Kerello275f7062017-09-13 18:00:08 +020046static int stm32_rcc_bind(struct udevice *dev)
47{
Christophe Kerello275f7062017-09-13 18:00:08 +020048 struct udevice *child;
Patrice Chotard03f10a12017-11-15 13:14:51 +010049 struct driver *drv;
50 struct stm32_rcc_clk *rcc_clk =
51 (struct stm32_rcc_clk *)dev_get_driver_data(dev);
52 int ret;
Christophe Kerello275f7062017-09-13 18:00:08 +020053
Patrick Delaunayeec21f32020-11-06 19:01:43 +010054 dev_dbg(dev, "RCC bind\n");
Patrice Chotard03f10a12017-11-15 13:14:51 +010055 drv = lists_driver_lookup_name(rcc_clk->drv_name);
56 if (!drv) {
Patrick Delaunayeec21f32020-11-06 19:01:43 +010057 dev_err(dev, "Cannot find driver '%s'\n", rcc_clk->drv_name);
Patrice Chotard03f10a12017-11-15 13:14:51 +010058 return -ENOENT;
59 }
60
Patrick Delaunay78075bb2020-11-06 19:01:44 +010061 ret = device_bind_with_driver_data(dev, drv, dev->name,
Patrice Chotard03f10a12017-11-15 13:14:51 +010062 rcc_clk->soc,
63 dev_ofnode(dev), &child);
64
Christophe Kerello275f7062017-09-13 18:00:08 +020065 if (ret)
66 return ret;
67
Patrick Delaunayb139a5b2018-07-09 15:17:20 +020068 drv = lists_driver_lookup_name("stm32_rcc_reset");
69 if (!drv) {
70 dev_err(dev, "Cannot find driver stm32_rcc_reset'\n");
71 return -ENOENT;
72 }
73
Patrick Delaunay78075bb2020-11-06 19:01:44 +010074 return device_bind_with_driver_data(dev, drv, dev->name,
Patrick Delaunayb139a5b2018-07-09 15:17:20 +020075 rcc_clk->soc,
76 dev_ofnode(dev), &child);
Christophe Kerello275f7062017-09-13 18:00:08 +020077}
78
Christophe Kerello275f7062017-09-13 18:00:08 +020079static const struct udevice_id stm32_rcc_ids[] = {
Patrice Chotard7264aae2018-04-11 17:07:45 +020080 {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x },
81 {.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_clk_f469 },
Patrice Chotard03f10a12017-11-15 13:14:51 +010082 {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
83 {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
Patrick Delaunayb139a5b2018-07-09 15:17:20 +020084 {.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
Patrick Delaunayb5b1aa12022-07-05 16:55:55 +020085 {.compatible = "st,stm32mp1-rcc-secure", .data = (ulong)&stm32_rcc_clk_mp1 },
Patrick Delaunay6b4490c2022-05-19 17:56:46 +020086 {.compatible = "st,stm32mp13-rcc", .data = (ulong)&stm32_rcc_clk_mp13 },
Christophe Kerello275f7062017-09-13 18:00:08 +020087 { }
88};
89
90U_BOOT_DRIVER(stm32_rcc) = {
91 .name = "stm32-rcc",
Patrick Delaunayd79f8ee2019-08-02 13:08:08 +020092 .id = UCLASS_NOP,
Christophe Kerello275f7062017-09-13 18:00:08 +020093 .of_match = stm32_rcc_ids,
94 .bind = stm32_rcc_bind,
Christophe Kerello275f7062017-09-13 18:00:08 +020095};