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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chander Kashyap0d2f2772013-08-21 10:38:56 +05302/*
3 * Copyright (C) 2013 Samsung Electronics
Chander Kashyap0d2f2772013-08-21 10:38:56 +05304 */
5
6#include <common.h>
Simon Glass370382c2019-11-14 12:57:35 -07007#include <cpu_func.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07008#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Inderpal Singh3260bc82014-01-08 09:19:57 +053010#include <usb.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
Simon Glass37f11622014-10-20 19:48:37 -060012#include <asm/gpio.h>
Chander Kashyap0d2f2772013-08-21 10:38:56 +053013#include <asm/arch/pinmux.h>
Inderpal Singh04bb7372013-08-21 10:38:57 +053014#include <asm/arch/dwmmc.h>
Chander Kashyap0d2f2772013-08-21 10:38:56 +053015#include <asm/arch/power.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
Inderpal Singh3260bc82014-01-08 09:19:57 +053019#ifdef CONFIG_USB_EHCI_EXYNOS
20int board_usb_init(int index, enum usb_init_type init)
21{
Inderpal Singh3260bc82014-01-08 09:19:57 +053022 /* Configure gpios for usb 3503 hub:
23 * disconnect, toggle reset and connect
24 */
Simon Glass4f83d3d2014-10-20 19:48:39 -060025 gpio_request(EXYNOS5_GPIO_D17, "usb_connect");
26 gpio_request(EXYNOS5_GPIO_X35, "usb_reset");
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053027 gpio_direction_output(EXYNOS5_GPIO_D17, 0);
28 gpio_direction_output(EXYNOS5_GPIO_X35, 0);
Inderpal Singh3260bc82014-01-08 09:19:57 +053029
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053030 gpio_direction_output(EXYNOS5_GPIO_X35, 1);
31 gpio_direction_output(EXYNOS5_GPIO_D17, 1);
Inderpal Singh3260bc82014-01-08 09:19:57 +053032
33 return 0;
34}
35#endif
36
Chander Kashyap0d2f2772013-08-21 10:38:56 +053037int board_init(void)
38{
39 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
40 return 0;
41}
42
43int dram_init(void)
44{
45 int i;
46 u32 addr;
47
48 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
Tom Rinibb4dd962022-11-16 13:10:37 -050049 addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
Chander Kashyap0d2f2772013-08-21 10:38:56 +053050 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
51 }
52 return 0;
53}
54
55int power_init_board(void)
56{
57 set_ps_hold_ctrl();
58 return 0;
59}
60
Simon Glass2f949c32017-03-31 08:40:32 -060061int dram_init_banksize(void)
Chander Kashyap0d2f2772013-08-21 10:38:56 +053062{
63 int i;
64 u32 addr, size;
65
66 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
Tom Rinibb4dd962022-11-16 13:10:37 -050067 addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
Chander Kashyap0d2f2772013-08-21 10:38:56 +053068 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
69
70 gd->bd->bi_dram[i].start = addr;
71 gd->bd->bi_dram[i].size = size;
72 }
Simon Glass2f949c32017-03-31 08:40:32 -060073
74 return 0;
Chander Kashyap0d2f2772013-08-21 10:38:56 +053075}
76
Chander Kashyap0d2f2772013-08-21 10:38:56 +053077static int board_uart_init(void)
78{
79 int err = 0, uart_id;
80
81 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
82 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
83 if (err) {
84 debug("UART%d not configured\n",
85 (uart_id - PERIPH_ID_UART0));
86 return err;
87 }
88 }
89 return err;
90}
91
92#ifdef CONFIG_BOARD_EARLY_INIT_F
93int board_early_init_f(void)
94{
95 int err;
96
97 err = board_uart_init();
98 if (err) {
99 debug("UART init failed\n");
100 return err;
101 }
102 return err;
103}
104#endif
105
106#ifdef CONFIG_DISPLAY_BOARDINFO
107int checkboard(void)
108{
109 printf("\nBoard: Arndale\n");
110
111 return 0;
112}
113#endif
Andre Przywara64d4c222014-08-01 13:35:44 +0200114
Tom Rinib942f0a2022-12-04 10:13:54 -0500115#ifdef CFG_SMP_PEN_ADDR
Andre Przywara64d4c222014-08-01 13:35:44 +0200116void smp_set_core_boot_addr(unsigned long addr, int corenr)
117{
Tom Rinib942f0a2022-12-04 10:13:54 -0500118 writel(addr, CFG_SMP_PEN_ADDR);
Andre Przywara64d4c222014-08-01 13:35:44 +0200119
120 /* make sure this write is really executed */
121 __asm__ volatile ("dsb\n");
122}
123#endif