Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 |
| 4 | * David Feng <fenghua@phytium.com.cn> |
| 5 | * Sharma Bhupesh <bhupesh.sharma@freescale.com> |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 6 | */ |
| 7 | #include <common.h> |
Simon Glass | 11c89f3 | 2017-05-17 17:18:03 -0600 | [diff] [blame] | 8 | #include <dm.h> |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 9 | #include <malloc.h> |
| 10 | #include <errno.h> |
| 11 | #include <netdev.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <linux/compiler.h> |
David Feng | ab33c2c | 2015-01-31 11:55:29 +0800 | [diff] [blame] | 14 | #include <dm/platform_data/serial_pl01x.h> |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 15 | #include "pcie.h" |
Alexander Graf | 5889e39 | 2016-03-04 01:09:51 +0100 | [diff] [blame] | 16 | #include <asm/armv8/mmu.h> |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
David Feng | ab33c2c | 2015-01-31 11:55:29 +0800 | [diff] [blame] | 20 | static const struct pl01x_serial_platdata serial_platdata = { |
| 21 | .base = V2M_UART0, |
| 22 | .type = TYPE_PL011, |
Linus Walleij | 31e476e | 2015-04-14 10:01:35 +0200 | [diff] [blame] | 23 | .clock = CONFIG_PL011_CLOCK, |
David Feng | ab33c2c | 2015-01-31 11:55:29 +0800 | [diff] [blame] | 24 | }; |
| 25 | |
| 26 | U_BOOT_DEVICE(vexpress_serials) = { |
| 27 | .name = "serial_pl01x", |
| 28 | .platdata = &serial_platdata, |
| 29 | }; |
| 30 | |
Alexander Graf | 5889e39 | 2016-03-04 01:09:51 +0100 | [diff] [blame] | 31 | static struct mm_region vexpress64_mem_map[] = { |
| 32 | { |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 33 | .virt = 0x0UL, |
| 34 | .phys = 0x0UL, |
Alexander Graf | 5889e39 | 2016-03-04 01:09:51 +0100 | [diff] [blame] | 35 | .size = 0x80000000UL, |
| 36 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 37 | PTE_BLOCK_NON_SHARE | |
| 38 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 39 | }, { |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 40 | .virt = 0x80000000UL, |
| 41 | .phys = 0x80000000UL, |
Alexander Graf | 5889e39 | 2016-03-04 01:09:51 +0100 | [diff] [blame] | 42 | .size = 0xff80000000UL, |
| 43 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 44 | PTE_BLOCK_INNER_SHARE |
| 45 | }, { |
| 46 | /* List terminator */ |
| 47 | 0, |
| 48 | } |
| 49 | }; |
| 50 | |
| 51 | struct mm_region *mem_map = vexpress64_mem_map; |
| 52 | |
Ryan Harkin | 8961d50 | 2015-11-18 10:39:06 +0000 | [diff] [blame] | 53 | /* This function gets replaced by platforms supporting PCIe. |
| 54 | * The replacement function, eg. on Juno, initialises the PCIe bus. |
| 55 | */ |
| 56 | __weak void vexpress64_pcie_init(void) |
| 57 | { |
| 58 | } |
| 59 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 60 | int board_init(void) |
| 61 | { |
Liviu Dudau | 8d1fdc3 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 62 | vexpress64_pcie_init(); |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | int dram_init(void) |
| 67 | { |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 68 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
| 69 | return 0; |
| 70 | } |
| 71 | |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 72 | int dram_init_banksize(void) |
Liviu Dudau | 086c977 | 2015-10-19 11:08:31 +0100 | [diff] [blame] | 73 | { |
| 74 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 75 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 76 | #ifdef PHYS_SDRAM_2 |
Liviu Dudau | 086c977 | 2015-10-19 11:08:31 +0100 | [diff] [blame] | 77 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
| 78 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 79 | #endif |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 80 | |
| 81 | return 0; |
Liviu Dudau | 086c977 | 2015-10-19 11:08:31 +0100 | [diff] [blame] | 82 | } |
| 83 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 84 | /* |
| 85 | * Board specific reset that is system reset. |
| 86 | */ |
| 87 | void reset_cpu(ulong addr) |
| 88 | { |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 89 | } |
| 90 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 91 | /* |
| 92 | * Board specific ethernet initialization routine. |
| 93 | */ |
| 94 | int board_eth_init(bd_t *bis) |
| 95 | { |
| 96 | int rc = 0; |
| 97 | #ifdef CONFIG_SMC91111 |
| 98 | rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); |
| 99 | #endif |
Linus Walleij | 48b4755 | 2015-02-17 11:35:25 +0100 | [diff] [blame] | 100 | #ifdef CONFIG_SMC911X |
| 101 | rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
| 102 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 103 | return rc; |
| 104 | } |