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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
David Feng3b5458c2013-12-14 11:47:37 +08002/*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
5 * Sharma Bhupesh <bhupesh.sharma@freescale.com>
David Feng3b5458c2013-12-14 11:47:37 +08006 */
7#include <common.h>
Simon Glass11c89f32017-05-17 17:18:03 -06008#include <dm.h>
David Feng3b5458c2013-12-14 11:47:37 +08009#include <malloc.h>
10#include <errno.h>
11#include <netdev.h>
12#include <asm/io.h>
13#include <linux/compiler.h>
David Fengab33c2c2015-01-31 11:55:29 +080014#include <dm/platform_data/serial_pl01x.h>
Liviu Dudau8d1fdc32015-10-19 11:08:32 +010015#include "pcie.h"
Alexander Graf5889e392016-03-04 01:09:51 +010016#include <asm/armv8/mmu.h>
David Feng3b5458c2013-12-14 11:47:37 +080017
18DECLARE_GLOBAL_DATA_PTR;
19
David Fengab33c2c2015-01-31 11:55:29 +080020static const struct pl01x_serial_platdata serial_platdata = {
21 .base = V2M_UART0,
22 .type = TYPE_PL011,
Linus Walleij31e476e2015-04-14 10:01:35 +020023 .clock = CONFIG_PL011_CLOCK,
David Fengab33c2c2015-01-31 11:55:29 +080024};
25
26U_BOOT_DEVICE(vexpress_serials) = {
27 .name = "serial_pl01x",
28 .platdata = &serial_platdata,
29};
30
Alexander Graf5889e392016-03-04 01:09:51 +010031static struct mm_region vexpress64_mem_map[] = {
32 {
York Sunc7104e52016-06-24 16:46:22 -070033 .virt = 0x0UL,
34 .phys = 0x0UL,
Alexander Graf5889e392016-03-04 01:09:51 +010035 .size = 0x80000000UL,
36 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
37 PTE_BLOCK_NON_SHARE |
38 PTE_BLOCK_PXN | PTE_BLOCK_UXN
39 }, {
York Sunc7104e52016-06-24 16:46:22 -070040 .virt = 0x80000000UL,
41 .phys = 0x80000000UL,
Alexander Graf5889e392016-03-04 01:09:51 +010042 .size = 0xff80000000UL,
43 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
44 PTE_BLOCK_INNER_SHARE
45 }, {
46 /* List terminator */
47 0,
48 }
49};
50
51struct mm_region *mem_map = vexpress64_mem_map;
52
Ryan Harkin8961d502015-11-18 10:39:06 +000053/* This function gets replaced by platforms supporting PCIe.
54 * The replacement function, eg. on Juno, initialises the PCIe bus.
55 */
56__weak void vexpress64_pcie_init(void)
57{
58}
59
David Feng3b5458c2013-12-14 11:47:37 +080060int board_init(void)
61{
Liviu Dudau8d1fdc32015-10-19 11:08:32 +010062 vexpress64_pcie_init();
David Feng3b5458c2013-12-14 11:47:37 +080063 return 0;
64}
65
66int dram_init(void)
67{
David Feng3b5458c2013-12-14 11:47:37 +080068 gd->ram_size = PHYS_SDRAM_1_SIZE;
69 return 0;
70}
71
Simon Glass2f949c32017-03-31 08:40:32 -060072int dram_init_banksize(void)
Liviu Dudau086c9772015-10-19 11:08:31 +010073{
74 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
75 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
Ryan Harkin98d2fff2015-11-18 10:39:07 +000076#ifdef PHYS_SDRAM_2
Liviu Dudau086c9772015-10-19 11:08:31 +010077 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
78 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
Ryan Harkin98d2fff2015-11-18 10:39:07 +000079#endif
Simon Glass2f949c32017-03-31 08:40:32 -060080
81 return 0;
Liviu Dudau086c9772015-10-19 11:08:31 +010082}
83
David Feng3b5458c2013-12-14 11:47:37 +080084/*
85 * Board specific reset that is system reset.
86 */
87void reset_cpu(ulong addr)
88{
Darwin Rambod32d4112014-06-09 11:12:59 -070089}
90
David Feng3b5458c2013-12-14 11:47:37 +080091/*
92 * Board specific ethernet initialization routine.
93 */
94int board_eth_init(bd_t *bis)
95{
96 int rc = 0;
97#ifdef CONFIG_SMC91111
98 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
99#endif
Linus Walleij48b47552015-02-17 11:35:25 +0100100#ifdef CONFIG_SMC911X
101 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
102#endif
David Feng3b5458c2013-12-14 11:47:37 +0800103 return rc;
104}