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git01.mediatek.com / filogic / uboot / 0cb3112526860f97990b0e0901f83e352f1112db / . / drivers / pinctrl / renesas / pfc-r8a7796.c
blob: 24fbbf19aa967d81a04ca75253cacf31ee35f8c4 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
3 * R8A7796 processor support - PFC hardware block.
4 *
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]12 */
13
14#include <common.h>
15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/kernel.h>
19
20#include "sh_pfc.h"
21
22#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
23 SH_PFC_PIN_CFG_PULL_UP | \
24 SH_PFC_PIN_CFG_PULL_DOWN)
25
26#define CPU_ALL_PORT(fn, sfx) \
27 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
36 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
39/*
40 * F_() : just information
41 * FM() : macro for FN_xxx / xxx_MARK
42 */
43
44/* GPSR0 */
45#define GPSR0_15 F_(D15, IP7_11_8)
46#define GPSR0_14 F_(D14, IP7_7_4)
47#define GPSR0_13 F_(D13, IP7_3_0)
48#define GPSR0_12 F_(D12, IP6_31_28)
49#define GPSR0_11 F_(D11, IP6_27_24)
50#define GPSR0_10 F_(D10, IP6_23_20)
51#define GPSR0_9 F_(D9, IP6_19_16)
52#define GPSR0_8 F_(D8, IP6_15_12)
53#define GPSR0_7 F_(D7, IP6_11_8)
54#define GPSR0_6 F_(D6, IP6_7_4)
55#define GPSR0_5 F_(D5, IP6_3_0)
56#define GPSR0_4 F_(D4, IP5_31_28)
57#define GPSR0_3 F_(D3, IP5_27_24)
58#define GPSR0_2 F_(D2, IP5_23_20)
59#define GPSR0_1 F_(D1, IP5_19_16)
60#define GPSR0_0 F_(D0, IP5_15_12)
61
62/* GPSR1 */
63#define GPSR1_28 FM(CLKOUT)
64#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
65#define GPSR1_26 F_(WE1_N, IP5_7_4)
66#define GPSR1_25 F_(WE0_N, IP5_3_0)
67#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
68#define GPSR1_23 F_(RD_N, IP4_27_24)
69#define GPSR1_22 F_(BS_N, IP4_23_20)
70#define GPSR1_21 F_(CS1_N, IP4_19_16)
71#define GPSR1_20 F_(CS0_N, IP4_15_12)
72#define GPSR1_19 F_(A19, IP4_11_8)
73#define GPSR1_18 F_(A18, IP4_7_4)
74#define GPSR1_17 F_(A17, IP4_3_0)
75#define GPSR1_16 F_(A16, IP3_31_28)
76#define GPSR1_15 F_(A15, IP3_27_24)
77#define GPSR1_14 F_(A14, IP3_23_20)
78#define GPSR1_13 F_(A13, IP3_19_16)
79#define GPSR1_12 F_(A12, IP3_15_12)
80#define GPSR1_11 F_(A11, IP3_11_8)
81#define GPSR1_10 F_(A10, IP3_7_4)
82#define GPSR1_9 F_(A9, IP3_3_0)
83#define GPSR1_8 F_(A8, IP2_31_28)
84#define GPSR1_7 F_(A7, IP2_27_24)
85#define GPSR1_6 F_(A6, IP2_23_20)
86#define GPSR1_5 F_(A5, IP2_19_16)
87#define GPSR1_4 F_(A4, IP2_15_12)
88#define GPSR1_3 F_(A3, IP2_11_8)
89#define GPSR1_2 F_(A2, IP2_7_4)
90#define GPSR1_1 F_(A1, IP2_3_0)
91#define GPSR1_0 F_(A0, IP1_31_28)
92
93/* GPSR2 */
94#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
95#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
96#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
97#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
98#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
99#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
100#define GPSR2_8 F_(PWM2_A, IP1_27_24)
101#define GPSR2_7 F_(PWM1_A, IP1_23_20)
102#define GPSR2_6 F_(PWM0, IP1_19_16)
103#define GPSR2_5 F_(IRQ5, IP1_15_12)
104#define GPSR2_4 F_(IRQ4, IP1_11_8)
105#define GPSR2_3 F_(IRQ3, IP1_7_4)
106#define GPSR2_2 F_(IRQ2, IP1_3_0)
107#define GPSR2_1 F_(IRQ1, IP0_31_28)
108#define GPSR2_0 F_(IRQ0, IP0_27_24)
109
110/* GPSR3 */
111#define GPSR3_15 F_(SD1_WP, IP11_23_20)
112#define GPSR3_14 F_(SD1_CD, IP11_19_16)
113#define GPSR3_13 F_(SD0_WP, IP11_15_12)
114#define GPSR3_12 F_(SD0_CD, IP11_11_8)
115#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
116#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
117#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
118#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
119#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
120#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
121#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
122#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
123#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
124#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
125#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
126#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
127
128/* GPSR4 */
129#define GPSR4_17 F_(SD3_DS, IP11_7_4)
130#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
131#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
132#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
133#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
134#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
135#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
136#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
137#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
138#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
139#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
140#define GPSR4_6 F_(SD2_DS, IP9_27_24)
141#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
142#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
143#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
144#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
145#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
146#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
147
148/* GPSR5 */
149#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
150#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
151#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
152#define GPSR5_22 FM(MSIOF0_RXD)
153#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
154#define GPSR5_20 FM(MSIOF0_TXD)
155#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
156#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
157#define GPSR5_17 FM(MSIOF0_SCK)
158#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
159#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
160#define GPSR5_14 F_(HTX0, IP13_19_16)
161#define GPSR5_13 F_(HRX0, IP13_15_12)
162#define GPSR5_12 F_(HSCK0, IP13_11_8)
163#define GPSR5_11 F_(RX2_A, IP13_7_4)
164#define GPSR5_10 F_(TX2_A, IP13_3_0)
165#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]166#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]167#define GPSR5_7 F_(CTS1_N, IP12_23_20)
168#define GPSR5_6 F_(TX1_A, IP12_19_16)
169#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]170#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]171#define GPSR5_3 F_(CTS0_N, IP12_7_4)
172#define GPSR5_2 F_(TX0, IP12_3_0)
173#define GPSR5_1 F_(RX0, IP11_31_28)
174#define GPSR5_0 F_(SCK0, IP11_27_24)
175
176/* GPSR6 */
177#define GPSR6_31 F_(GP6_31, IP18_7_4)
178#define GPSR6_30 F_(GP6_30, IP18_3_0)
179#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
180#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
181#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
182#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
183#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
184#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
185#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
186#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
187#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
188#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
189#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
190#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
191#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
192#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
193#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
194#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
195#define GPSR6_13 FM(SSI_SDATA5)
196#define GPSR6_12 FM(SSI_WS5)
197#define GPSR6_11 FM(SSI_SCK5)
198#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
199#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
200#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
201#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
202#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
203#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
204#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
205#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
206#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
207#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
208#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
209
210/* GPSR7 */
211#define GPSR7_3 FM(GP7_03)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]212#define GPSR7_2 FM(HDMI0_CEC)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]213#define GPSR7_1 FM(AVS2)
214#define GPSR7_0 FM(AVS1)
215
216
217/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
218#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]227#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]233#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]243#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]244#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245
246/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
247#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]261#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]262#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]274#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]275#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276
277/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
278#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312
313/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
314#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]321#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]322#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]325#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]326#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
335#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342
343/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
344#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]361#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]362#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
364#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
365#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
366#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
367#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
368#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
370#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
371
372#define PINMUX_GPSR \
373\
374 GPSR6_31 \
375 GPSR6_30 \
376 GPSR6_29 \
377 GPSR1_28 GPSR6_28 \
378 GPSR1_27 GPSR6_27 \
379 GPSR1_26 GPSR6_26 \
380 GPSR1_25 GPSR5_25 GPSR6_25 \
381 GPSR1_24 GPSR5_24 GPSR6_24 \
382 GPSR1_23 GPSR5_23 GPSR6_23 \
383 GPSR1_22 GPSR5_22 GPSR6_22 \
384 GPSR1_21 GPSR5_21 GPSR6_21 \
385 GPSR1_20 GPSR5_20 GPSR6_20 \
386 GPSR1_19 GPSR5_19 GPSR6_19 \
387 GPSR1_18 GPSR5_18 GPSR6_18 \
388 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
389 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
390GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
391GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
392GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
393GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
394GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
395GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
396GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
397GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
398GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
399GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
400GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
401GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
402GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
403GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
404GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
405GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
406
407#define PINMUX_IPSR \
408\
409FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
410FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
411FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
412FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
413FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
414FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
415FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
416FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
417\
418FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
419FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
420FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
421FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
422FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
423FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
424FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
425FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
426\
427FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
428FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
429FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
430FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
431FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
432FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
433FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
434FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
435\
436FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
437FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
438FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
439FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
440FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
441FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
442FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
443FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
444\
445FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
446FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
447FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
448FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
449FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
450FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
451FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
452FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
453
454/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
455#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
456#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
457#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
458#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
459#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
460#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
461#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
462#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
463#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
464#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
465#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
466#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
467#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
468#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
469#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
470#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
471#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]472#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]473
474/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
475#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
476#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
477#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
478#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
479#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]480#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]481#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
482#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
483#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
484#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
485#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
486#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
487#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
488#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
489#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
490#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
491#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
492#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
493#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
494#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
495#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
496#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
497
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]498/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]499#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
500#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
501#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
502#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
503#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
504#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]505#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]506#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
507#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
508#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]509#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
510#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]511#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
512
513#define PINMUX_MOD_SELS \
514\
515MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
516 MOD_SEL2_30 \
517 MOD_SEL1_29_28_27 MOD_SEL2_29 \
518MOD_SEL0_28_27 MOD_SEL2_28_27 \
519MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
520 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
521MOD_SEL0_23 MOD_SEL1_23_22_21 \
522MOD_SEL0_22 MOD_SEL2_22 \
523MOD_SEL0_21 MOD_SEL2_21 \
524MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
525MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
526MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
527 MOD_SEL2_17 \
528MOD_SEL0_16 MOD_SEL1_16 \
529 MOD_SEL1_15_14 \
530MOD_SEL0_14_13 \
531 MOD_SEL1_13 \
532MOD_SEL0_12 MOD_SEL1_12 \
533MOD_SEL0_11 MOD_SEL1_11 \
534MOD_SEL0_10 MOD_SEL1_10 \
535MOD_SEL0_9_8 MOD_SEL1_9 \
536MOD_SEL0_7_6 \
537 MOD_SEL1_6 \
538MOD_SEL0_5 MOD_SEL1_5 \
539MOD_SEL0_4_3 MOD_SEL1_4 \
540 MOD_SEL1_3 \
541 MOD_SEL1_2 \
542 MOD_SEL1_1 \
543 MOD_SEL1_0 MOD_SEL2_0
544
545/*
546 * These pins are not able to be muxed but have other properties
547 * that can be set, such as drive-strength or pull-up/pull-down enable.
548 */
549#define PINMUX_STATIC \
550 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
551 FM(QSPI0_IO2) FM(QSPI0_IO3) \
552 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
553 FM(QSPI1_IO2) FM(QSPI1_IO3) \
554 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
555 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
556 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
557 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
558 FM(PRESETOUT) \
559 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
560 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
561
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]562#define PINMUX_PHYS \
563 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
564
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]565enum {
566 PINMUX_RESERVED = 0,
567
568 PINMUX_DATA_BEGIN,
569 GP_ALL(DATA),
570 PINMUX_DATA_END,
571
572#define F_(x, y)
573#define FM(x) FN_##x,
574 PINMUX_FUNCTION_BEGIN,
575 GP_ALL(FN),
576 PINMUX_GPSR
577 PINMUX_IPSR
578 PINMUX_MOD_SELS
579 PINMUX_FUNCTION_END,
580#undef F_
581#undef FM
582
583#define F_(x, y)
584#define FM(x) x##_MARK,
585 PINMUX_MARK_BEGIN,
586 PINMUX_GPSR
587 PINMUX_IPSR
588 PINMUX_MOD_SELS
589 PINMUX_STATIC
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]590 PINMUX_PHYS
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]591 PINMUX_MARK_END,
592#undef F_
593#undef FM
594};
595
596static const u16 pinmux_data[] = {
597 PINMUX_DATA_GP_ALL(),
598
599 PINMUX_SINGLE(AVS1),
600 PINMUX_SINGLE(AVS2),
601 PINMUX_SINGLE(CLKOUT),
602 PINMUX_SINGLE(GP7_03),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]603 PINMUX_SINGLE(HDMI0_CEC),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]604 PINMUX_SINGLE(MSIOF0_RXD),
605 PINMUX_SINGLE(MSIOF0_SCK),
606 PINMUX_SINGLE(MSIOF0_TXD),
607 PINMUX_SINGLE(SSI_SCK5),
608 PINMUX_SINGLE(SSI_SDATA5),
609 PINMUX_SINGLE(SSI_WS5),
610
611 /* IPSR0 */
612 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
613 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
614
615 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
616 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
617 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
618
619 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
620 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
621 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
622
623 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
624 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
626
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]627 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
628 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
629 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
630 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]631
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]632 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
633 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
634 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
635 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]636
637 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
638 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
639 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
640 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
643 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
644
645 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
646 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
647 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
648 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
649 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
650 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
651 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
652
653 /* IPSR1 */
654 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
655 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
656 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
657 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
659 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
660
661 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
662 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]663 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
664 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
665 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
666 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
667
668 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
669 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]670 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
671 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
673 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
674
675 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
676 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]677 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
678 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
680 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
681
682 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
683 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]684 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
685 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
686
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]687 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
688 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
689 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
690 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
691 PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]692
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]693 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
694 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
695 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
696 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]697
698 PINMUX_IPSR_GPSR(IP1_31_28, A0),
699 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
700 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
701 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
702 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
703 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
704
705 /* IPSR2 */
706 PINMUX_IPSR_GPSR(IP2_3_0, A1),
707 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
708 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
709 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
710 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
711 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
712
713 PINMUX_IPSR_GPSR(IP2_7_4, A2),
714 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
715 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
716 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
717 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
718 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
719
720 PINMUX_IPSR_GPSR(IP2_11_8, A3),
721 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
722 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
723 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
724 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
725 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
726
727 PINMUX_IPSR_GPSR(IP2_15_12, A4),
728 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
729 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
730 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
731 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
732 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
733
734 PINMUX_IPSR_GPSR(IP2_19_16, A5),
735 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
736 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
737 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
738 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
739 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
740 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
741
742 PINMUX_IPSR_GPSR(IP2_23_20, A6),
743 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
744 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
745 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
746 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
747 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
748 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
749
750 PINMUX_IPSR_GPSR(IP2_27_24, A7),
751 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
752 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
753 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
754 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
755 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
756 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
757
758 PINMUX_IPSR_GPSR(IP2_31_28, A8),
759 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
760 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
761 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
762 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
763 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
764 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
765
766 /* IPSR3 */
767 PINMUX_IPSR_GPSR(IP3_3_0, A9),
768 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
769 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
770 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
771
772 PINMUX_IPSR_GPSR(IP3_7_4, A10),
773 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]774 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]775 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
776
777 PINMUX_IPSR_GPSR(IP3_11_8, A11),
778 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
779 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
780 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
781 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
782 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
783 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
784 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
785 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
786
787 PINMUX_IPSR_GPSR(IP3_15_12, A12),
788 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
789 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
790 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
791 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
792 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
793
794 PINMUX_IPSR_GPSR(IP3_19_16, A13),
795 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
796 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
797 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
798 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
799 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
800
801 PINMUX_IPSR_GPSR(IP3_23_20, A14),
802 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
803 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
804 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
805 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
806 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
807
808 PINMUX_IPSR_GPSR(IP3_27_24, A15),
809 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
810 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
811 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
812 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
813 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
814
815 PINMUX_IPSR_GPSR(IP3_31_28, A16),
816 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
817 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
818 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
819
820 /* IPSR4 */
821 PINMUX_IPSR_GPSR(IP4_3_0, A17),
822 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
823 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
824 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
825
826 PINMUX_IPSR_GPSR(IP4_7_4, A18),
827 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
828 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
829 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
830
831 PINMUX_IPSR_GPSR(IP4_11_8, A19),
832 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
833 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
834 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
835
836 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
837 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
838
839 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
840 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
841 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
842
843 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
844 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
845 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
846 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
847 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
848 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
849 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
850 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
851
852 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
853 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
854 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
855 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
856 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
857 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
858
859 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
860 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
861 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
862 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
863 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
864 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
865
866 /* IPSR5 */
867 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
868 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
869 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
870 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
871 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
872 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
873 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
874
875 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
876 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]877 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]878 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
879 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
880 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
881 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
882 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
883
884 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
885 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
886 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
887 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
888
889 PINMUX_IPSR_GPSR(IP5_15_12, D0),
890 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
891 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
892 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
893 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
894
895 PINMUX_IPSR_GPSR(IP5_19_16, D1),
896 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
897 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
898 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
899 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
900
901 PINMUX_IPSR_GPSR(IP5_23_20, D2),
902 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
903 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
904 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
905
906 PINMUX_IPSR_GPSR(IP5_27_24, D3),
907 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
908 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
909 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
910
911 PINMUX_IPSR_GPSR(IP5_31_28, D4),
912 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
913 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
914 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
915
916 /* IPSR6 */
917 PINMUX_IPSR_GPSR(IP6_3_0, D5),
918 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
920 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
921
922 PINMUX_IPSR_GPSR(IP6_7_4, D6),
923 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
924 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
925 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
926
927 PINMUX_IPSR_GPSR(IP6_11_8, D7),
928 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
929 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
930 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
931
932 PINMUX_IPSR_GPSR(IP6_15_12, D8),
933 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
934 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
935 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
936 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
937 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
938
939 PINMUX_IPSR_GPSR(IP6_19_16, D9),
940 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
941 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
942 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
943 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
944
945 PINMUX_IPSR_GPSR(IP6_23_20, D10),
946 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
947 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
948 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
949 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
950 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
951 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
952
953 PINMUX_IPSR_GPSR(IP6_27_24, D11),
954 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
955 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
956 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
957 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]958 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]959 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
960
961 PINMUX_IPSR_GPSR(IP6_31_28, D12),
962 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
963 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
964 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
965 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
966 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
967
968 /* IPSR7 */
969 PINMUX_IPSR_GPSR(IP7_3_0, D13),
970 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
971 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
972 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
973 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
974 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
975
976 PINMUX_IPSR_GPSR(IP7_7_4, D14),
977 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
978 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
979 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
980 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
982 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
983
984 PINMUX_IPSR_GPSR(IP7_11_8, D15),
985 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
986 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
987 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
988 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
989 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
990 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
991
992 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
993 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
994 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
995
996 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
997 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
998 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
999
1000 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1001 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1004
1005 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1006 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1007 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1008 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1009
1010 /* IPSR8 */
1011 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1012 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1013 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1014 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1015
1016 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1017 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1018 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1019 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1020
1021 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1022 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1023 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1024
1025 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1026 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1027 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1028 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1029 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1030
1031 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1032 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1033 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1034 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1035 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1036 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1037
1038 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1039 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1040 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1041 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1042 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1043 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1044
1045 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1046 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1047 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1048 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1049 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1050 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1051
1052 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1053 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1054 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1055 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1056 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1057 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1058
1059 /* IPSR9 */
1060 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1061 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1062
1063 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1064 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1065
1066 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1067 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1068
1069 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1070 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1071
1072 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1073 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1074
1075 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1076 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1077
1078 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1079 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1080
1081 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1082 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1083
1084 /* IPSR10 */
1085 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1086 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1087
1088 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1089 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1090
1091 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1092 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1093
1094 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1095 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1096
1097 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1098 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1099
1100 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1101 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1103
1104 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1105 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1106 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1107
1108 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1109 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1110 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1111
1112 /* IPSR11 */
1113 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1114 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1115 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1116
1117 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1118 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1119
1120 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1121 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1122 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1123 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1124
1125 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1126 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1127 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1128
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1129 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1130 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0),
1131 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1132 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1133
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1134 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1135 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0),
1136 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1137 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1138
1139 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1140 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1141 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1142 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1143 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1144 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1145 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1146 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1147 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1148 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1149
1150 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1151 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1152 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1153 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1154 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1155
1156 /* IPSR12 */
1157 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1158 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1159 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1160 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1161 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1162
1163 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1164 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1165 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1166 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1167 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1169 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1170 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1171
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1172 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1173 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1174 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1175 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1176 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1177 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1178 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1179 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1180
1181 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1182 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1183 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1184 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1185 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1186
1187 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1188 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1189 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1190 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1191 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1192
1193 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1194 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1195 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1196 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1197 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1198 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1199 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1200
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1201 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1202 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1203 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1204 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1205 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1206 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1207 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1208
1209 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1210 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1211 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1212 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1213 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1214 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1215 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1216
1217 /* IPSR13 */
1218 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1219 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1220 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1221 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1222 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1223 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1224
1225 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1226 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1227 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1228 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1229 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1230 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1231
1232 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1233 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1234 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1235 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1236 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1237 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1238 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1239 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1240
1241 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1242 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1243 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1244 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1245 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1246 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1247
1248 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1249 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1250 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1251 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1252 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1253 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1254
1255 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1256 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1257 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1258 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1259 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1260 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1261 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1262 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1263
1264 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1265 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1266 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1267 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1268 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1269 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1270 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1271
1272 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1273 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1274 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1275 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1276
1277 /* IPSR14 */
1278 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1279 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1280 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
1281 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1282 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1283 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1284 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1285 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1286
1287 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1288 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1289 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1290 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1291 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1292 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1293 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1294 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1295
1296 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1297 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1298 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1299
1300 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1301 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1302 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1303 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1304
1305 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1306 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1307 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1308
1309 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1310 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1311
1312 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1313 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1314
1315 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1316 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1317
1318 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1319 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1320
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1321 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1322 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1323
1324 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1325 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1326 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1327
1328 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1329 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1330 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1331 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1332
1333 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1334 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1336 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1338 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1340
1341 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1342 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1343 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1344 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1346 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1348
1349 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1350 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1351 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1352 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1354 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1356
1357 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1358 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1359 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1360 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1361 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1362 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1363 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1364
1365 /* IPSR16 */
1366 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1367 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1368
1369 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1370 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1371
1372 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1373 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1374
1375 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1376 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1377 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1378 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1380 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1381 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1382
1383 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1384 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1385 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1386 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1388 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1389 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1390
1391 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1392 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1393 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1394 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1395 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1396 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1397 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1398 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1399
1400 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1401 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1402 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1403 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1404 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1405 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1406 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1407
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1408 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1409 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1410 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1411 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1412 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1413 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1414 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1415 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1416
1417 /* IPSR17 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1418 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1419 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1420
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1421 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1422 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1423 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1425 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1426
1427 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1428 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1429 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1430 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1431 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1432 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1433 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1434
1435 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1436 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1437 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1438 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1439 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1440 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1441
1442 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1443 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1444 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1445 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1446 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1447 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1448 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1449 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1450 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1451
1452 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1453 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1454 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1455 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1456 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1457 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1458 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1459 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1460 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1461
1462 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1463 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1464 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1465 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1466 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1467 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1468 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1469 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1470 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1471 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1472 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1473
1474 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1475 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1476 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1477 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1478 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1479 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1480 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1481 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1482 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1483
1484 /* IPSR18 */
1485 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1486 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1487 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1488 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1489 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1490 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1491 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1492 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1493 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1494
1495 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1496 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1497 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1498 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1499 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1500 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1501 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1502 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1503 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1504
1505 /* I2C */
1506 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1507 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1508 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1509
1510/*
1511 * Static pins can not be muxed between different functions but
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1512 * still need mark entries in the pinmux list. Add each static
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1513 * pin to the list without an associated function. The sh-pfc
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1514 * core will do the right thing and skip trying to mux the pin
1515 * while still applying configuration to it.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1516 */
1517#define FM(x) PINMUX_DATA(x##_MARK, 0),
1518 PINMUX_STATIC
1519#undef FM
1520};
1521
1522/*
1523 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1524 * Physical layout rows: A - AW, cols: 1 - 39.
1525 */
1526#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1527#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1528#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1529#define PIN_NONE U16_MAX
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1530
1531static const struct sh_pfc_pin pinmux_pins[] = {
1532 PINMUX_GPIO_GP_ALL(),
1533
1534 /*
1535 * Pins not associated with a GPIO port.
1536 *
1537 * The pin positions are different between different r8a7796
1538 * packages, all that is needed for the pfc driver is a unique
1539 * number for each pin. To this end use the pin layout from
1540 * R-Car M3SiP to calculate a unique number for each pin.
1541 */
1542 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1577 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1578 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1579 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1580 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1581 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1582 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1583 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1584};
1585
1586/* - AUDIO CLOCK ------------------------------------------------------------ */
1587static const unsigned int audio_clk_a_a_pins[] = {
1588 /* CLK A */
1589 RCAR_GP_PIN(6, 22),
1590};
1591static const unsigned int audio_clk_a_a_mux[] = {
1592 AUDIO_CLKA_A_MARK,
1593};
1594static const unsigned int audio_clk_a_b_pins[] = {
1595 /* CLK A */
1596 RCAR_GP_PIN(5, 4),
1597};
1598static const unsigned int audio_clk_a_b_mux[] = {
1599 AUDIO_CLKA_B_MARK,
1600};
1601static const unsigned int audio_clk_a_c_pins[] = {
1602 /* CLK A */
1603 RCAR_GP_PIN(5, 19),
1604};
1605static const unsigned int audio_clk_a_c_mux[] = {
1606 AUDIO_CLKA_C_MARK,
1607};
1608static const unsigned int audio_clk_b_a_pins[] = {
1609 /* CLK B */
1610 RCAR_GP_PIN(5, 12),
1611};
1612static const unsigned int audio_clk_b_a_mux[] = {
1613 AUDIO_CLKB_A_MARK,
1614};
1615static const unsigned int audio_clk_b_b_pins[] = {
1616 /* CLK B */
1617 RCAR_GP_PIN(6, 23),
1618};
1619static const unsigned int audio_clk_b_b_mux[] = {
1620 AUDIO_CLKB_B_MARK,
1621};
1622static const unsigned int audio_clk_c_a_pins[] = {
1623 /* CLK C */
1624 RCAR_GP_PIN(5, 21),
1625};
1626static const unsigned int audio_clk_c_a_mux[] = {
1627 AUDIO_CLKC_A_MARK,
1628};
1629static const unsigned int audio_clk_c_b_pins[] = {
1630 /* CLK C */
1631 RCAR_GP_PIN(5, 0),
1632};
1633static const unsigned int audio_clk_c_b_mux[] = {
1634 AUDIO_CLKC_B_MARK,
1635};
1636static const unsigned int audio_clkout_a_pins[] = {
1637 /* CLKOUT */
1638 RCAR_GP_PIN(5, 18),
1639};
1640static const unsigned int audio_clkout_a_mux[] = {
1641 AUDIO_CLKOUT_A_MARK,
1642};
1643static const unsigned int audio_clkout_b_pins[] = {
1644 /* CLKOUT */
1645 RCAR_GP_PIN(6, 28),
1646};
1647static const unsigned int audio_clkout_b_mux[] = {
1648 AUDIO_CLKOUT_B_MARK,
1649};
1650static const unsigned int audio_clkout_c_pins[] = {
1651 /* CLKOUT */
1652 RCAR_GP_PIN(5, 3),
1653};
1654static const unsigned int audio_clkout_c_mux[] = {
1655 AUDIO_CLKOUT_C_MARK,
1656};
1657static const unsigned int audio_clkout_d_pins[] = {
1658 /* CLKOUT */
1659 RCAR_GP_PIN(5, 21),
1660};
1661static const unsigned int audio_clkout_d_mux[] = {
1662 AUDIO_CLKOUT_D_MARK,
1663};
1664static const unsigned int audio_clkout1_a_pins[] = {
1665 /* CLKOUT1 */
1666 RCAR_GP_PIN(5, 15),
1667};
1668static const unsigned int audio_clkout1_a_mux[] = {
1669 AUDIO_CLKOUT1_A_MARK,
1670};
1671static const unsigned int audio_clkout1_b_pins[] = {
1672 /* CLKOUT1 */
1673 RCAR_GP_PIN(6, 29),
1674};
1675static const unsigned int audio_clkout1_b_mux[] = {
1676 AUDIO_CLKOUT1_B_MARK,
1677};
1678static const unsigned int audio_clkout2_a_pins[] = {
1679 /* CLKOUT2 */
1680 RCAR_GP_PIN(5, 16),
1681};
1682static const unsigned int audio_clkout2_a_mux[] = {
1683 AUDIO_CLKOUT2_A_MARK,
1684};
1685static const unsigned int audio_clkout2_b_pins[] = {
1686 /* CLKOUT2 */
1687 RCAR_GP_PIN(6, 30),
1688};
1689static const unsigned int audio_clkout2_b_mux[] = {
1690 AUDIO_CLKOUT2_B_MARK,
1691};
1692
1693static const unsigned int audio_clkout3_a_pins[] = {
1694 /* CLKOUT3 */
1695 RCAR_GP_PIN(5, 19),
1696};
1697static const unsigned int audio_clkout3_a_mux[] = {
1698 AUDIO_CLKOUT3_A_MARK,
1699};
1700static const unsigned int audio_clkout3_b_pins[] = {
1701 /* CLKOUT3 */
1702 RCAR_GP_PIN(6, 31),
1703};
1704static const unsigned int audio_clkout3_b_mux[] = {
1705 AUDIO_CLKOUT3_B_MARK,
1706};
1707
1708/* - EtherAVB --------------------------------------------------------------- */
1709static const unsigned int avb_link_pins[] = {
1710 /* AVB_LINK */
1711 RCAR_GP_PIN(2, 12),
1712};
1713static const unsigned int avb_link_mux[] = {
1714 AVB_LINK_MARK,
1715};
1716static const unsigned int avb_magic_pins[] = {
1717 /* AVB_MAGIC_ */
1718 RCAR_GP_PIN(2, 10),
1719};
1720static const unsigned int avb_magic_mux[] = {
1721 AVB_MAGIC_MARK,
1722};
1723static const unsigned int avb_phy_int_pins[] = {
1724 /* AVB_PHY_INT */
1725 RCAR_GP_PIN(2, 11),
1726};
1727static const unsigned int avb_phy_int_mux[] = {
1728 AVB_PHY_INT_MARK,
1729};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1730static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1731 /* AVB_MDC, AVB_MDIO */
1732 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1733};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1734static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1735 AVB_MDC_MARK, AVB_MDIO_MARK,
1736};
1737static const unsigned int avb_mii_pins[] = {
1738 /*
1739 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1740 * AVB_TD1, AVB_TD2, AVB_TD3,
1741 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1742 * AVB_RD1, AVB_RD2, AVB_RD3,
1743 * AVB_TXCREFCLK
1744 */
1745 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1746 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1747 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1748 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1749 PIN_NUMBER('A', 12),
1750
1751};
1752static const unsigned int avb_mii_mux[] = {
1753 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1754 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1755 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1756 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1757 AVB_TXCREFCLK_MARK,
1758};
1759static const unsigned int avb_avtp_pps_pins[] = {
1760 /* AVB_AVTP_PPS */
1761 RCAR_GP_PIN(2, 6),
1762};
1763static const unsigned int avb_avtp_pps_mux[] = {
1764 AVB_AVTP_PPS_MARK,
1765};
1766static const unsigned int avb_avtp_match_a_pins[] = {
1767 /* AVB_AVTP_MATCH_A */
1768 RCAR_GP_PIN(2, 13),
1769};
1770static const unsigned int avb_avtp_match_a_mux[] = {
1771 AVB_AVTP_MATCH_A_MARK,
1772};
1773static const unsigned int avb_avtp_capture_a_pins[] = {
1774 /* AVB_AVTP_CAPTURE_A */
1775 RCAR_GP_PIN(2, 14),
1776};
1777static const unsigned int avb_avtp_capture_a_mux[] = {
1778 AVB_AVTP_CAPTURE_A_MARK,
1779};
1780static const unsigned int avb_avtp_match_b_pins[] = {
1781 /* AVB_AVTP_MATCH_B */
1782 RCAR_GP_PIN(1, 8),
1783};
1784static const unsigned int avb_avtp_match_b_mux[] = {
1785 AVB_AVTP_MATCH_B_MARK,
1786};
1787static const unsigned int avb_avtp_capture_b_pins[] = {
1788 /* AVB_AVTP_CAPTURE_B */
1789 RCAR_GP_PIN(1, 11),
1790};
1791static const unsigned int avb_avtp_capture_b_mux[] = {
1792 AVB_AVTP_CAPTURE_B_MARK,
1793};
1794
1795/* - CAN ------------------------------------------------------------------ */
1796static const unsigned int can0_data_a_pins[] = {
1797 /* TX, RX */
1798 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1799};
1800static const unsigned int can0_data_a_mux[] = {
1801 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1802};
1803static const unsigned int can0_data_b_pins[] = {
1804 /* TX, RX */
1805 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1806};
1807static const unsigned int can0_data_b_mux[] = {
1808 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1809};
1810static const unsigned int can1_data_pins[] = {
1811 /* TX, RX */
1812 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1813};
1814static const unsigned int can1_data_mux[] = {
1815 CAN1_TX_MARK, CAN1_RX_MARK,
1816};
1817
1818/* - CAN Clock -------------------------------------------------------------- */
1819static const unsigned int can_clk_pins[] = {
1820 /* CLK */
1821 RCAR_GP_PIN(1, 25),
1822};
1823static const unsigned int can_clk_mux[] = {
1824 CAN_CLK_MARK,
1825};
1826
1827/* - CAN FD --------------------------------------------------------------- */
1828static const unsigned int canfd0_data_a_pins[] = {
1829 /* TX, RX */
1830 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1831};
1832static const unsigned int canfd0_data_a_mux[] = {
1833 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1834};
1835static const unsigned int canfd0_data_b_pins[] = {
1836 /* TX, RX */
1837 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1838};
1839static const unsigned int canfd0_data_b_mux[] = {
1840 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1841};
1842static const unsigned int canfd1_data_pins[] = {
1843 /* TX, RX */
1844 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1845};
1846static const unsigned int canfd1_data_mux[] = {
1847 CANFD1_TX_MARK, CANFD1_RX_MARK,
1848};
1849
1850/* - DRIF0 --------------------------------------------------------------- */
1851static const unsigned int drif0_ctrl_a_pins[] = {
1852 /* CLK, SYNC */
1853 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1854};
1855static const unsigned int drif0_ctrl_a_mux[] = {
1856 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1857};
1858static const unsigned int drif0_data0_a_pins[] = {
1859 /* D0 */
1860 RCAR_GP_PIN(6, 10),
1861};
1862static const unsigned int drif0_data0_a_mux[] = {
1863 RIF0_D0_A_MARK,
1864};
1865static const unsigned int drif0_data1_a_pins[] = {
1866 /* D1 */
1867 RCAR_GP_PIN(6, 7),
1868};
1869static const unsigned int drif0_data1_a_mux[] = {
1870 RIF0_D1_A_MARK,
1871};
1872static const unsigned int drif0_ctrl_b_pins[] = {
1873 /* CLK, SYNC */
1874 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1875};
1876static const unsigned int drif0_ctrl_b_mux[] = {
1877 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1878};
1879static const unsigned int drif0_data0_b_pins[] = {
1880 /* D0 */
1881 RCAR_GP_PIN(5, 1),
1882};
1883static const unsigned int drif0_data0_b_mux[] = {
1884 RIF0_D0_B_MARK,
1885};
1886static const unsigned int drif0_data1_b_pins[] = {
1887 /* D1 */
1888 RCAR_GP_PIN(5, 2),
1889};
1890static const unsigned int drif0_data1_b_mux[] = {
1891 RIF0_D1_B_MARK,
1892};
1893static const unsigned int drif0_ctrl_c_pins[] = {
1894 /* CLK, SYNC */
1895 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1896};
1897static const unsigned int drif0_ctrl_c_mux[] = {
1898 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1899};
1900static const unsigned int drif0_data0_c_pins[] = {
1901 /* D0 */
1902 RCAR_GP_PIN(5, 13),
1903};
1904static const unsigned int drif0_data0_c_mux[] = {
1905 RIF0_D0_C_MARK,
1906};
1907static const unsigned int drif0_data1_c_pins[] = {
1908 /* D1 */
1909 RCAR_GP_PIN(5, 14),
1910};
1911static const unsigned int drif0_data1_c_mux[] = {
1912 RIF0_D1_C_MARK,
1913};
1914/* - DRIF1 --------------------------------------------------------------- */
1915static const unsigned int drif1_ctrl_a_pins[] = {
1916 /* CLK, SYNC */
1917 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1918};
1919static const unsigned int drif1_ctrl_a_mux[] = {
1920 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1921};
1922static const unsigned int drif1_data0_a_pins[] = {
1923 /* D0 */
1924 RCAR_GP_PIN(6, 19),
1925};
1926static const unsigned int drif1_data0_a_mux[] = {
1927 RIF1_D0_A_MARK,
1928};
1929static const unsigned int drif1_data1_a_pins[] = {
1930 /* D1 */
1931 RCAR_GP_PIN(6, 20),
1932};
1933static const unsigned int drif1_data1_a_mux[] = {
1934 RIF1_D1_A_MARK,
1935};
1936static const unsigned int drif1_ctrl_b_pins[] = {
1937 /* CLK, SYNC */
1938 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1939};
1940static const unsigned int drif1_ctrl_b_mux[] = {
1941 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1942};
1943static const unsigned int drif1_data0_b_pins[] = {
1944 /* D0 */
1945 RCAR_GP_PIN(5, 7),
1946};
1947static const unsigned int drif1_data0_b_mux[] = {
1948 RIF1_D0_B_MARK,
1949};
1950static const unsigned int drif1_data1_b_pins[] = {
1951 /* D1 */
1952 RCAR_GP_PIN(5, 8),
1953};
1954static const unsigned int drif1_data1_b_mux[] = {
1955 RIF1_D1_B_MARK,
1956};
1957static const unsigned int drif1_ctrl_c_pins[] = {
1958 /* CLK, SYNC */
1959 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1960};
1961static const unsigned int drif1_ctrl_c_mux[] = {
1962 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1963};
1964static const unsigned int drif1_data0_c_pins[] = {
1965 /* D0 */
1966 RCAR_GP_PIN(5, 6),
1967};
1968static const unsigned int drif1_data0_c_mux[] = {
1969 RIF1_D0_C_MARK,
1970};
1971static const unsigned int drif1_data1_c_pins[] = {
1972 /* D1 */
1973 RCAR_GP_PIN(5, 10),
1974};
1975static const unsigned int drif1_data1_c_mux[] = {
1976 RIF1_D1_C_MARK,
1977};
1978/* - DRIF2 --------------------------------------------------------------- */
1979static const unsigned int drif2_ctrl_a_pins[] = {
1980 /* CLK, SYNC */
1981 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1982};
1983static const unsigned int drif2_ctrl_a_mux[] = {
1984 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1985};
1986static const unsigned int drif2_data0_a_pins[] = {
1987 /* D0 */
1988 RCAR_GP_PIN(6, 7),
1989};
1990static const unsigned int drif2_data0_a_mux[] = {
1991 RIF2_D0_A_MARK,
1992};
1993static const unsigned int drif2_data1_a_pins[] = {
1994 /* D1 */
1995 RCAR_GP_PIN(6, 10),
1996};
1997static const unsigned int drif2_data1_a_mux[] = {
1998 RIF2_D1_A_MARK,
1999};
2000static const unsigned int drif2_ctrl_b_pins[] = {
2001 /* CLK, SYNC */
2002 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2003};
2004static const unsigned int drif2_ctrl_b_mux[] = {
2005 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2006};
2007static const unsigned int drif2_data0_b_pins[] = {
2008 /* D0 */
2009 RCAR_GP_PIN(6, 30),
2010};
2011static const unsigned int drif2_data0_b_mux[] = {
2012 RIF2_D0_B_MARK,
2013};
2014static const unsigned int drif2_data1_b_pins[] = {
2015 /* D1 */
2016 RCAR_GP_PIN(6, 31),
2017};
2018static const unsigned int drif2_data1_b_mux[] = {
2019 RIF2_D1_B_MARK,
2020};
2021/* - DRIF3 --------------------------------------------------------------- */
2022static const unsigned int drif3_ctrl_a_pins[] = {
2023 /* CLK, SYNC */
2024 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2025};
2026static const unsigned int drif3_ctrl_a_mux[] = {
2027 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2028};
2029static const unsigned int drif3_data0_a_pins[] = {
2030 /* D0 */
2031 RCAR_GP_PIN(6, 19),
2032};
2033static const unsigned int drif3_data0_a_mux[] = {
2034 RIF3_D0_A_MARK,
2035};
2036static const unsigned int drif3_data1_a_pins[] = {
2037 /* D1 */
2038 RCAR_GP_PIN(6, 20),
2039};
2040static const unsigned int drif3_data1_a_mux[] = {
2041 RIF3_D1_A_MARK,
2042};
2043static const unsigned int drif3_ctrl_b_pins[] = {
2044 /* CLK, SYNC */
2045 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2046};
2047static const unsigned int drif3_ctrl_b_mux[] = {
2048 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2049};
2050static const unsigned int drif3_data0_b_pins[] = {
2051 /* D0 */
2052 RCAR_GP_PIN(6, 28),
2053};
2054static const unsigned int drif3_data0_b_mux[] = {
2055 RIF3_D0_B_MARK,
2056};
2057static const unsigned int drif3_data1_b_pins[] = {
2058 /* D1 */
2059 RCAR_GP_PIN(6, 29),
2060};
2061static const unsigned int drif3_data1_b_mux[] = {
2062 RIF3_D1_B_MARK,
2063};
2064
2065/* - DU --------------------------------------------------------------------- */
2066static const unsigned int du_rgb666_pins[] = {
2067 /* R[7:2], G[7:2], B[7:2] */
2068 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2069 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2070 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2071 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2072 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2073 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2074};
2075static const unsigned int du_rgb666_mux[] = {
2076 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2077 DU_DR3_MARK, DU_DR2_MARK,
2078 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2079 DU_DG3_MARK, DU_DG2_MARK,
2080 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2081 DU_DB3_MARK, DU_DB2_MARK,
2082};
2083static const unsigned int du_rgb888_pins[] = {
2084 /* R[7:0], G[7:0], B[7:0] */
2085 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2086 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2087 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2088 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2089 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2090 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2091 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2092 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2093 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2094};
2095static const unsigned int du_rgb888_mux[] = {
2096 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2097 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2098 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2099 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2100 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2101 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2102};
2103static const unsigned int du_clk_out_0_pins[] = {
2104 /* CLKOUT */
2105 RCAR_GP_PIN(1, 27),
2106};
2107static const unsigned int du_clk_out_0_mux[] = {
2108 DU_DOTCLKOUT0_MARK
2109};
2110static const unsigned int du_clk_out_1_pins[] = {
2111 /* CLKOUT */
2112 RCAR_GP_PIN(2, 3),
2113};
2114static const unsigned int du_clk_out_1_mux[] = {
2115 DU_DOTCLKOUT1_MARK
2116};
2117static const unsigned int du_sync_pins[] = {
2118 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2119 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2120};
2121static const unsigned int du_sync_mux[] = {
2122 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2123};
2124static const unsigned int du_oddf_pins[] = {
2125 /* EXDISP/EXODDF/EXCDE */
2126 RCAR_GP_PIN(2, 2),
2127};
2128static const unsigned int du_oddf_mux[] = {
2129 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2130};
2131static const unsigned int du_cde_pins[] = {
2132 /* CDE */
2133 RCAR_GP_PIN(2, 0),
2134};
2135static const unsigned int du_cde_mux[] = {
2136 DU_CDE_MARK,
2137};
2138static const unsigned int du_disp_pins[] = {
2139 /* DISP */
2140 RCAR_GP_PIN(2, 1),
2141};
2142static const unsigned int du_disp_mux[] = {
2143 DU_DISP_MARK,
2144};
2145
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2146/* - HDMI ------------------------------------------------------------------- */
2147static const unsigned int hdmi0_cec_pins[] = {
2148 /* HDMI0_CEC */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2149 RCAR_GP_PIN(7, 2),
2150};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2151static const unsigned int hdmi0_cec_mux[] = {
2152 HDMI0_CEC_MARK,
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]2153};
2154
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2155/* - HSCIF0 ----------------------------------------------------------------- */
2156static const unsigned int hscif0_data_pins[] = {
2157 /* RX, TX */
2158 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2159};
2160static const unsigned int hscif0_data_mux[] = {
2161 HRX0_MARK, HTX0_MARK,
2162};
2163static const unsigned int hscif0_clk_pins[] = {
2164 /* SCK */
2165 RCAR_GP_PIN(5, 12),
2166};
2167static const unsigned int hscif0_clk_mux[] = {
2168 HSCK0_MARK,
2169};
2170static const unsigned int hscif0_ctrl_pins[] = {
2171 /* RTS, CTS */
2172 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2173};
2174static const unsigned int hscif0_ctrl_mux[] = {
2175 HRTS0_N_MARK, HCTS0_N_MARK,
2176};
2177/* - HSCIF1 ----------------------------------------------------------------- */
2178static const unsigned int hscif1_data_a_pins[] = {
2179 /* RX, TX */
2180 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2181};
2182static const unsigned int hscif1_data_a_mux[] = {
2183 HRX1_A_MARK, HTX1_A_MARK,
2184};
2185static const unsigned int hscif1_clk_a_pins[] = {
2186 /* SCK */
2187 RCAR_GP_PIN(6, 21),
2188};
2189static const unsigned int hscif1_clk_a_mux[] = {
2190 HSCK1_A_MARK,
2191};
2192static const unsigned int hscif1_ctrl_a_pins[] = {
2193 /* RTS, CTS */
2194 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2195};
2196static const unsigned int hscif1_ctrl_a_mux[] = {
2197 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2198};
2199
2200static const unsigned int hscif1_data_b_pins[] = {
2201 /* RX, TX */
2202 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2203};
2204static const unsigned int hscif1_data_b_mux[] = {
2205 HRX1_B_MARK, HTX1_B_MARK,
2206};
2207static const unsigned int hscif1_clk_b_pins[] = {
2208 /* SCK */
2209 RCAR_GP_PIN(5, 0),
2210};
2211static const unsigned int hscif1_clk_b_mux[] = {
2212 HSCK1_B_MARK,
2213};
2214static const unsigned int hscif1_ctrl_b_pins[] = {
2215 /* RTS, CTS */
2216 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2217};
2218static const unsigned int hscif1_ctrl_b_mux[] = {
2219 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2220};
2221/* - HSCIF2 ----------------------------------------------------------------- */
2222static const unsigned int hscif2_data_a_pins[] = {
2223 /* RX, TX */
2224 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2225};
2226static const unsigned int hscif2_data_a_mux[] = {
2227 HRX2_A_MARK, HTX2_A_MARK,
2228};
2229static const unsigned int hscif2_clk_a_pins[] = {
2230 /* SCK */
2231 RCAR_GP_PIN(6, 10),
2232};
2233static const unsigned int hscif2_clk_a_mux[] = {
2234 HSCK2_A_MARK,
2235};
2236static const unsigned int hscif2_ctrl_a_pins[] = {
2237 /* RTS, CTS */
2238 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2239};
2240static const unsigned int hscif2_ctrl_a_mux[] = {
2241 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2242};
2243
2244static const unsigned int hscif2_data_b_pins[] = {
2245 /* RX, TX */
2246 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2247};
2248static const unsigned int hscif2_data_b_mux[] = {
2249 HRX2_B_MARK, HTX2_B_MARK,
2250};
2251static const unsigned int hscif2_clk_b_pins[] = {
2252 /* SCK */
2253 RCAR_GP_PIN(6, 21),
2254};
2255static const unsigned int hscif2_clk_b_mux[] = {
2256 HSCK2_B_MARK,
2257};
2258static const unsigned int hscif2_ctrl_b_pins[] = {
2259 /* RTS, CTS */
2260 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2261};
2262static const unsigned int hscif2_ctrl_b_mux[] = {
2263 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2264};
2265
2266static const unsigned int hscif2_data_c_pins[] = {
2267 /* RX, TX */
2268 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2269};
2270static const unsigned int hscif2_data_c_mux[] = {
2271 HRX2_C_MARK, HTX2_C_MARK,
2272};
2273static const unsigned int hscif2_clk_c_pins[] = {
2274 /* SCK */
2275 RCAR_GP_PIN(6, 24),
2276};
2277static const unsigned int hscif2_clk_c_mux[] = {
2278 HSCK2_C_MARK,
2279};
2280static const unsigned int hscif2_ctrl_c_pins[] = {
2281 /* RTS, CTS */
2282 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2283};
2284static const unsigned int hscif2_ctrl_c_mux[] = {
2285 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2286};
2287/* - HSCIF3 ----------------------------------------------------------------- */
2288static const unsigned int hscif3_data_a_pins[] = {
2289 /* RX, TX */
2290 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2291};
2292static const unsigned int hscif3_data_a_mux[] = {
2293 HRX3_A_MARK, HTX3_A_MARK,
2294};
2295static const unsigned int hscif3_clk_pins[] = {
2296 /* SCK */
2297 RCAR_GP_PIN(1, 22),
2298};
2299static const unsigned int hscif3_clk_mux[] = {
2300 HSCK3_MARK,
2301};
2302static const unsigned int hscif3_ctrl_pins[] = {
2303 /* RTS, CTS */
2304 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2305};
2306static const unsigned int hscif3_ctrl_mux[] = {
2307 HRTS3_N_MARK, HCTS3_N_MARK,
2308};
2309
2310static const unsigned int hscif3_data_b_pins[] = {
2311 /* RX, TX */
2312 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2313};
2314static const unsigned int hscif3_data_b_mux[] = {
2315 HRX3_B_MARK, HTX3_B_MARK,
2316};
2317static const unsigned int hscif3_data_c_pins[] = {
2318 /* RX, TX */
2319 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2320};
2321static const unsigned int hscif3_data_c_mux[] = {
2322 HRX3_C_MARK, HTX3_C_MARK,
2323};
2324static const unsigned int hscif3_data_d_pins[] = {
2325 /* RX, TX */
2326 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2327};
2328static const unsigned int hscif3_data_d_mux[] = {
2329 HRX3_D_MARK, HTX3_D_MARK,
2330};
2331/* - HSCIF4 ----------------------------------------------------------------- */
2332static const unsigned int hscif4_data_a_pins[] = {
2333 /* RX, TX */
2334 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2335};
2336static const unsigned int hscif4_data_a_mux[] = {
2337 HRX4_A_MARK, HTX4_A_MARK,
2338};
2339static const unsigned int hscif4_clk_pins[] = {
2340 /* SCK */
2341 RCAR_GP_PIN(1, 11),
2342};
2343static const unsigned int hscif4_clk_mux[] = {
2344 HSCK4_MARK,
2345};
2346static const unsigned int hscif4_ctrl_pins[] = {
2347 /* RTS, CTS */
2348 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2349};
2350static const unsigned int hscif4_ctrl_mux[] = {
2351 HRTS4_N_MARK, HCTS4_N_MARK,
2352};
2353
2354static const unsigned int hscif4_data_b_pins[] = {
2355 /* RX, TX */
2356 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2357};
2358static const unsigned int hscif4_data_b_mux[] = {
2359 HRX4_B_MARK, HTX4_B_MARK,
2360};
2361
2362/* - I2C -------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2363static const unsigned int i2c0_pins[] = {
2364 /* SCL, SDA */
2365 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2366};
2367
2368static const unsigned int i2c0_mux[] = {
2369 SCL0_MARK, SDA0_MARK,
2370};
2371
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2372static const unsigned int i2c1_a_pins[] = {
2373 /* SDA, SCL */
2374 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2375};
2376static const unsigned int i2c1_a_mux[] = {
2377 SDA1_A_MARK, SCL1_A_MARK,
2378};
2379static const unsigned int i2c1_b_pins[] = {
2380 /* SDA, SCL */
2381 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2382};
2383static const unsigned int i2c1_b_mux[] = {
2384 SDA1_B_MARK, SCL1_B_MARK,
2385};
2386static const unsigned int i2c2_a_pins[] = {
2387 /* SDA, SCL */
2388 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2389};
2390static const unsigned int i2c2_a_mux[] = {
2391 SDA2_A_MARK, SCL2_A_MARK,
2392};
2393static const unsigned int i2c2_b_pins[] = {
2394 /* SDA, SCL */
2395 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2396};
2397static const unsigned int i2c2_b_mux[] = {
2398 SDA2_B_MARK, SCL2_B_MARK,
2399};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2400
2401static const unsigned int i2c3_pins[] = {
2402 /* SCL, SDA */
2403 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2404};
2405
2406static const unsigned int i2c3_mux[] = {
2407 SCL3_MARK, SDA3_MARK,
2408};
2409
2410static const unsigned int i2c5_pins[] = {
2411 /* SCL, SDA */
2412 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2413};
2414
2415static const unsigned int i2c5_mux[] = {
2416 SCL5_MARK, SDA5_MARK,
2417};
2418
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2419static const unsigned int i2c6_a_pins[] = {
2420 /* SDA, SCL */
2421 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2422};
2423static const unsigned int i2c6_a_mux[] = {
2424 SDA6_A_MARK, SCL6_A_MARK,
2425};
2426static const unsigned int i2c6_b_pins[] = {
2427 /* SDA, SCL */
2428 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2429};
2430static const unsigned int i2c6_b_mux[] = {
2431 SDA6_B_MARK, SCL6_B_MARK,
2432};
2433static const unsigned int i2c6_c_pins[] = {
2434 /* SDA, SCL */
2435 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2436};
2437static const unsigned int i2c6_c_mux[] = {
2438 SDA6_C_MARK, SCL6_C_MARK,
2439};
2440
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2441/* - INTC-EX ---------------------------------------------------------------- */
2442static const unsigned int intc_ex_irq0_pins[] = {
2443 /* IRQ0 */
2444 RCAR_GP_PIN(2, 0),
2445};
2446static const unsigned int intc_ex_irq0_mux[] = {
2447 IRQ0_MARK,
2448};
2449static const unsigned int intc_ex_irq1_pins[] = {
2450 /* IRQ1 */
2451 RCAR_GP_PIN(2, 1),
2452};
2453static const unsigned int intc_ex_irq1_mux[] = {
2454 IRQ1_MARK,
2455};
2456static const unsigned int intc_ex_irq2_pins[] = {
2457 /* IRQ2 */
2458 RCAR_GP_PIN(2, 2),
2459};
2460static const unsigned int intc_ex_irq2_mux[] = {
2461 IRQ2_MARK,
2462};
2463static const unsigned int intc_ex_irq3_pins[] = {
2464 /* IRQ3 */
2465 RCAR_GP_PIN(2, 3),
2466};
2467static const unsigned int intc_ex_irq3_mux[] = {
2468 IRQ3_MARK,
2469};
2470static const unsigned int intc_ex_irq4_pins[] = {
2471 /* IRQ4 */
2472 RCAR_GP_PIN(2, 4),
2473};
2474static const unsigned int intc_ex_irq4_mux[] = {
2475 IRQ4_MARK,
2476};
2477static const unsigned int intc_ex_irq5_pins[] = {
2478 /* IRQ5 */
2479 RCAR_GP_PIN(2, 5),
2480};
2481static const unsigned int intc_ex_irq5_mux[] = {
2482 IRQ5_MARK,
2483};
2484
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2485/* - MSIOF0 ----------------------------------------------------------------- */
2486static const unsigned int msiof0_clk_pins[] = {
2487 /* SCK */
2488 RCAR_GP_PIN(5, 17),
2489};
2490static const unsigned int msiof0_clk_mux[] = {
2491 MSIOF0_SCK_MARK,
2492};
2493static const unsigned int msiof0_sync_pins[] = {
2494 /* SYNC */
2495 RCAR_GP_PIN(5, 18),
2496};
2497static const unsigned int msiof0_sync_mux[] = {
2498 MSIOF0_SYNC_MARK,
2499};
2500static const unsigned int msiof0_ss1_pins[] = {
2501 /* SS1 */
2502 RCAR_GP_PIN(5, 19),
2503};
2504static const unsigned int msiof0_ss1_mux[] = {
2505 MSIOF0_SS1_MARK,
2506};
2507static const unsigned int msiof0_ss2_pins[] = {
2508 /* SS2 */
2509 RCAR_GP_PIN(5, 21),
2510};
2511static const unsigned int msiof0_ss2_mux[] = {
2512 MSIOF0_SS2_MARK,
2513};
2514static const unsigned int msiof0_txd_pins[] = {
2515 /* TXD */
2516 RCAR_GP_PIN(5, 20),
2517};
2518static const unsigned int msiof0_txd_mux[] = {
2519 MSIOF0_TXD_MARK,
2520};
2521static const unsigned int msiof0_rxd_pins[] = {
2522 /* RXD */
2523 RCAR_GP_PIN(5, 22),
2524};
2525static const unsigned int msiof0_rxd_mux[] = {
2526 MSIOF0_RXD_MARK,
2527};
2528/* - MSIOF1 ----------------------------------------------------------------- */
2529static const unsigned int msiof1_clk_a_pins[] = {
2530 /* SCK */
2531 RCAR_GP_PIN(6, 8),
2532};
2533static const unsigned int msiof1_clk_a_mux[] = {
2534 MSIOF1_SCK_A_MARK,
2535};
2536static const unsigned int msiof1_sync_a_pins[] = {
2537 /* SYNC */
2538 RCAR_GP_PIN(6, 9),
2539};
2540static const unsigned int msiof1_sync_a_mux[] = {
2541 MSIOF1_SYNC_A_MARK,
2542};
2543static const unsigned int msiof1_ss1_a_pins[] = {
2544 /* SS1 */
2545 RCAR_GP_PIN(6, 5),
2546};
2547static const unsigned int msiof1_ss1_a_mux[] = {
2548 MSIOF1_SS1_A_MARK,
2549};
2550static const unsigned int msiof1_ss2_a_pins[] = {
2551 /* SS2 */
2552 RCAR_GP_PIN(6, 6),
2553};
2554static const unsigned int msiof1_ss2_a_mux[] = {
2555 MSIOF1_SS2_A_MARK,
2556};
2557static const unsigned int msiof1_txd_a_pins[] = {
2558 /* TXD */
2559 RCAR_GP_PIN(6, 7),
2560};
2561static const unsigned int msiof1_txd_a_mux[] = {
2562 MSIOF1_TXD_A_MARK,
2563};
2564static const unsigned int msiof1_rxd_a_pins[] = {
2565 /* RXD */
2566 RCAR_GP_PIN(6, 10),
2567};
2568static const unsigned int msiof1_rxd_a_mux[] = {
2569 MSIOF1_RXD_A_MARK,
2570};
2571static const unsigned int msiof1_clk_b_pins[] = {
2572 /* SCK */
2573 RCAR_GP_PIN(5, 9),
2574};
2575static const unsigned int msiof1_clk_b_mux[] = {
2576 MSIOF1_SCK_B_MARK,
2577};
2578static const unsigned int msiof1_sync_b_pins[] = {
2579 /* SYNC */
2580 RCAR_GP_PIN(5, 3),
2581};
2582static const unsigned int msiof1_sync_b_mux[] = {
2583 MSIOF1_SYNC_B_MARK,
2584};
2585static const unsigned int msiof1_ss1_b_pins[] = {
2586 /* SS1 */
2587 RCAR_GP_PIN(5, 4),
2588};
2589static const unsigned int msiof1_ss1_b_mux[] = {
2590 MSIOF1_SS1_B_MARK,
2591};
2592static const unsigned int msiof1_ss2_b_pins[] = {
2593 /* SS2 */
2594 RCAR_GP_PIN(5, 0),
2595};
2596static const unsigned int msiof1_ss2_b_mux[] = {
2597 MSIOF1_SS2_B_MARK,
2598};
2599static const unsigned int msiof1_txd_b_pins[] = {
2600 /* TXD */
2601 RCAR_GP_PIN(5, 8),
2602};
2603static const unsigned int msiof1_txd_b_mux[] = {
2604 MSIOF1_TXD_B_MARK,
2605};
2606static const unsigned int msiof1_rxd_b_pins[] = {
2607 /* RXD */
2608 RCAR_GP_PIN(5, 7),
2609};
2610static const unsigned int msiof1_rxd_b_mux[] = {
2611 MSIOF1_RXD_B_MARK,
2612};
2613static const unsigned int msiof1_clk_c_pins[] = {
2614 /* SCK */
2615 RCAR_GP_PIN(6, 17),
2616};
2617static const unsigned int msiof1_clk_c_mux[] = {
2618 MSIOF1_SCK_C_MARK,
2619};
2620static const unsigned int msiof1_sync_c_pins[] = {
2621 /* SYNC */
2622 RCAR_GP_PIN(6, 18),
2623};
2624static const unsigned int msiof1_sync_c_mux[] = {
2625 MSIOF1_SYNC_C_MARK,
2626};
2627static const unsigned int msiof1_ss1_c_pins[] = {
2628 /* SS1 */
2629 RCAR_GP_PIN(6, 21),
2630};
2631static const unsigned int msiof1_ss1_c_mux[] = {
2632 MSIOF1_SS1_C_MARK,
2633};
2634static const unsigned int msiof1_ss2_c_pins[] = {
2635 /* SS2 */
2636 RCAR_GP_PIN(6, 27),
2637};
2638static const unsigned int msiof1_ss2_c_mux[] = {
2639 MSIOF1_SS2_C_MARK,
2640};
2641static const unsigned int msiof1_txd_c_pins[] = {
2642 /* TXD */
2643 RCAR_GP_PIN(6, 20),
2644};
2645static const unsigned int msiof1_txd_c_mux[] = {
2646 MSIOF1_TXD_C_MARK,
2647};
2648static const unsigned int msiof1_rxd_c_pins[] = {
2649 /* RXD */
2650 RCAR_GP_PIN(6, 19),
2651};
2652static const unsigned int msiof1_rxd_c_mux[] = {
2653 MSIOF1_RXD_C_MARK,
2654};
2655static const unsigned int msiof1_clk_d_pins[] = {
2656 /* SCK */
2657 RCAR_GP_PIN(5, 12),
2658};
2659static const unsigned int msiof1_clk_d_mux[] = {
2660 MSIOF1_SCK_D_MARK,
2661};
2662static const unsigned int msiof1_sync_d_pins[] = {
2663 /* SYNC */
2664 RCAR_GP_PIN(5, 15),
2665};
2666static const unsigned int msiof1_sync_d_mux[] = {
2667 MSIOF1_SYNC_D_MARK,
2668};
2669static const unsigned int msiof1_ss1_d_pins[] = {
2670 /* SS1 */
2671 RCAR_GP_PIN(5, 16),
2672};
2673static const unsigned int msiof1_ss1_d_mux[] = {
2674 MSIOF1_SS1_D_MARK,
2675};
2676static const unsigned int msiof1_ss2_d_pins[] = {
2677 /* SS2 */
2678 RCAR_GP_PIN(5, 21),
2679};
2680static const unsigned int msiof1_ss2_d_mux[] = {
2681 MSIOF1_SS2_D_MARK,
2682};
2683static const unsigned int msiof1_txd_d_pins[] = {
2684 /* TXD */
2685 RCAR_GP_PIN(5, 14),
2686};
2687static const unsigned int msiof1_txd_d_mux[] = {
2688 MSIOF1_TXD_D_MARK,
2689};
2690static const unsigned int msiof1_rxd_d_pins[] = {
2691 /* RXD */
2692 RCAR_GP_PIN(5, 13),
2693};
2694static const unsigned int msiof1_rxd_d_mux[] = {
2695 MSIOF1_RXD_D_MARK,
2696};
2697static const unsigned int msiof1_clk_e_pins[] = {
2698 /* SCK */
2699 RCAR_GP_PIN(3, 0),
2700};
2701static const unsigned int msiof1_clk_e_mux[] = {
2702 MSIOF1_SCK_E_MARK,
2703};
2704static const unsigned int msiof1_sync_e_pins[] = {
2705 /* SYNC */
2706 RCAR_GP_PIN(3, 1),
2707};
2708static const unsigned int msiof1_sync_e_mux[] = {
2709 MSIOF1_SYNC_E_MARK,
2710};
2711static const unsigned int msiof1_ss1_e_pins[] = {
2712 /* SS1 */
2713 RCAR_GP_PIN(3, 4),
2714};
2715static const unsigned int msiof1_ss1_e_mux[] = {
2716 MSIOF1_SS1_E_MARK,
2717};
2718static const unsigned int msiof1_ss2_e_pins[] = {
2719 /* SS2 */
2720 RCAR_GP_PIN(3, 5),
2721};
2722static const unsigned int msiof1_ss2_e_mux[] = {
2723 MSIOF1_SS2_E_MARK,
2724};
2725static const unsigned int msiof1_txd_e_pins[] = {
2726 /* TXD */
2727 RCAR_GP_PIN(3, 3),
2728};
2729static const unsigned int msiof1_txd_e_mux[] = {
2730 MSIOF1_TXD_E_MARK,
2731};
2732static const unsigned int msiof1_rxd_e_pins[] = {
2733 /* RXD */
2734 RCAR_GP_PIN(3, 2),
2735};
2736static const unsigned int msiof1_rxd_e_mux[] = {
2737 MSIOF1_RXD_E_MARK,
2738};
2739static const unsigned int msiof1_clk_f_pins[] = {
2740 /* SCK */
2741 RCAR_GP_PIN(5, 23),
2742};
2743static const unsigned int msiof1_clk_f_mux[] = {
2744 MSIOF1_SCK_F_MARK,
2745};
2746static const unsigned int msiof1_sync_f_pins[] = {
2747 /* SYNC */
2748 RCAR_GP_PIN(5, 24),
2749};
2750static const unsigned int msiof1_sync_f_mux[] = {
2751 MSIOF1_SYNC_F_MARK,
2752};
2753static const unsigned int msiof1_ss1_f_pins[] = {
2754 /* SS1 */
2755 RCAR_GP_PIN(6, 1),
2756};
2757static const unsigned int msiof1_ss1_f_mux[] = {
2758 MSIOF1_SS1_F_MARK,
2759};
2760static const unsigned int msiof1_ss2_f_pins[] = {
2761 /* SS2 */
2762 RCAR_GP_PIN(6, 2),
2763};
2764static const unsigned int msiof1_ss2_f_mux[] = {
2765 MSIOF1_SS2_F_MARK,
2766};
2767static const unsigned int msiof1_txd_f_pins[] = {
2768 /* TXD */
2769 RCAR_GP_PIN(6, 0),
2770};
2771static const unsigned int msiof1_txd_f_mux[] = {
2772 MSIOF1_TXD_F_MARK,
2773};
2774static const unsigned int msiof1_rxd_f_pins[] = {
2775 /* RXD */
2776 RCAR_GP_PIN(5, 25),
2777};
2778static const unsigned int msiof1_rxd_f_mux[] = {
2779 MSIOF1_RXD_F_MARK,
2780};
2781static const unsigned int msiof1_clk_g_pins[] = {
2782 /* SCK */
2783 RCAR_GP_PIN(3, 6),
2784};
2785static const unsigned int msiof1_clk_g_mux[] = {
2786 MSIOF1_SCK_G_MARK,
2787};
2788static const unsigned int msiof1_sync_g_pins[] = {
2789 /* SYNC */
2790 RCAR_GP_PIN(3, 7),
2791};
2792static const unsigned int msiof1_sync_g_mux[] = {
2793 MSIOF1_SYNC_G_MARK,
2794};
2795static const unsigned int msiof1_ss1_g_pins[] = {
2796 /* SS1 */
2797 RCAR_GP_PIN(3, 10),
2798};
2799static const unsigned int msiof1_ss1_g_mux[] = {
2800 MSIOF1_SS1_G_MARK,
2801};
2802static const unsigned int msiof1_ss2_g_pins[] = {
2803 /* SS2 */
2804 RCAR_GP_PIN(3, 11),
2805};
2806static const unsigned int msiof1_ss2_g_mux[] = {
2807 MSIOF1_SS2_G_MARK,
2808};
2809static const unsigned int msiof1_txd_g_pins[] = {
2810 /* TXD */
2811 RCAR_GP_PIN(3, 9),
2812};
2813static const unsigned int msiof1_txd_g_mux[] = {
2814 MSIOF1_TXD_G_MARK,
2815};
2816static const unsigned int msiof1_rxd_g_pins[] = {
2817 /* RXD */
2818 RCAR_GP_PIN(3, 8),
2819};
2820static const unsigned int msiof1_rxd_g_mux[] = {
2821 MSIOF1_RXD_G_MARK,
2822};
2823/* - MSIOF2 ----------------------------------------------------------------- */
2824static const unsigned int msiof2_clk_a_pins[] = {
2825 /* SCK */
2826 RCAR_GP_PIN(1, 9),
2827};
2828static const unsigned int msiof2_clk_a_mux[] = {
2829 MSIOF2_SCK_A_MARK,
2830};
2831static const unsigned int msiof2_sync_a_pins[] = {
2832 /* SYNC */
2833 RCAR_GP_PIN(1, 8),
2834};
2835static const unsigned int msiof2_sync_a_mux[] = {
2836 MSIOF2_SYNC_A_MARK,
2837};
2838static const unsigned int msiof2_ss1_a_pins[] = {
2839 /* SS1 */
2840 RCAR_GP_PIN(1, 6),
2841};
2842static const unsigned int msiof2_ss1_a_mux[] = {
2843 MSIOF2_SS1_A_MARK,
2844};
2845static const unsigned int msiof2_ss2_a_pins[] = {
2846 /* SS2 */
2847 RCAR_GP_PIN(1, 7),
2848};
2849static const unsigned int msiof2_ss2_a_mux[] = {
2850 MSIOF2_SS2_A_MARK,
2851};
2852static const unsigned int msiof2_txd_a_pins[] = {
2853 /* TXD */
2854 RCAR_GP_PIN(1, 11),
2855};
2856static const unsigned int msiof2_txd_a_mux[] = {
2857 MSIOF2_TXD_A_MARK,
2858};
2859static const unsigned int msiof2_rxd_a_pins[] = {
2860 /* RXD */
2861 RCAR_GP_PIN(1, 10),
2862};
2863static const unsigned int msiof2_rxd_a_mux[] = {
2864 MSIOF2_RXD_A_MARK,
2865};
2866static const unsigned int msiof2_clk_b_pins[] = {
2867 /* SCK */
2868 RCAR_GP_PIN(0, 4),
2869};
2870static const unsigned int msiof2_clk_b_mux[] = {
2871 MSIOF2_SCK_B_MARK,
2872};
2873static const unsigned int msiof2_sync_b_pins[] = {
2874 /* SYNC */
2875 RCAR_GP_PIN(0, 5),
2876};
2877static const unsigned int msiof2_sync_b_mux[] = {
2878 MSIOF2_SYNC_B_MARK,
2879};
2880static const unsigned int msiof2_ss1_b_pins[] = {
2881 /* SS1 */
2882 RCAR_GP_PIN(0, 0),
2883};
2884static const unsigned int msiof2_ss1_b_mux[] = {
2885 MSIOF2_SS1_B_MARK,
2886};
2887static const unsigned int msiof2_ss2_b_pins[] = {
2888 /* SS2 */
2889 RCAR_GP_PIN(0, 1),
2890};
2891static const unsigned int msiof2_ss2_b_mux[] = {
2892 MSIOF2_SS2_B_MARK,
2893};
2894static const unsigned int msiof2_txd_b_pins[] = {
2895 /* TXD */
2896 RCAR_GP_PIN(0, 7),
2897};
2898static const unsigned int msiof2_txd_b_mux[] = {
2899 MSIOF2_TXD_B_MARK,
2900};
2901static const unsigned int msiof2_rxd_b_pins[] = {
2902 /* RXD */
2903 RCAR_GP_PIN(0, 6),
2904};
2905static const unsigned int msiof2_rxd_b_mux[] = {
2906 MSIOF2_RXD_B_MARK,
2907};
2908static const unsigned int msiof2_clk_c_pins[] = {
2909 /* SCK */
2910 RCAR_GP_PIN(2, 12),
2911};
2912static const unsigned int msiof2_clk_c_mux[] = {
2913 MSIOF2_SCK_C_MARK,
2914};
2915static const unsigned int msiof2_sync_c_pins[] = {
2916 /* SYNC */
2917 RCAR_GP_PIN(2, 11),
2918};
2919static const unsigned int msiof2_sync_c_mux[] = {
2920 MSIOF2_SYNC_C_MARK,
2921};
2922static const unsigned int msiof2_ss1_c_pins[] = {
2923 /* SS1 */
2924 RCAR_GP_PIN(2, 10),
2925};
2926static const unsigned int msiof2_ss1_c_mux[] = {
2927 MSIOF2_SS1_C_MARK,
2928};
2929static const unsigned int msiof2_ss2_c_pins[] = {
2930 /* SS2 */
2931 RCAR_GP_PIN(2, 9),
2932};
2933static const unsigned int msiof2_ss2_c_mux[] = {
2934 MSIOF2_SS2_C_MARK,
2935};
2936static const unsigned int msiof2_txd_c_pins[] = {
2937 /* TXD */
2938 RCAR_GP_PIN(2, 14),
2939};
2940static const unsigned int msiof2_txd_c_mux[] = {
2941 MSIOF2_TXD_C_MARK,
2942};
2943static const unsigned int msiof2_rxd_c_pins[] = {
2944 /* RXD */
2945 RCAR_GP_PIN(2, 13),
2946};
2947static const unsigned int msiof2_rxd_c_mux[] = {
2948 MSIOF2_RXD_C_MARK,
2949};
2950static const unsigned int msiof2_clk_d_pins[] = {
2951 /* SCK */
2952 RCAR_GP_PIN(0, 8),
2953};
2954static const unsigned int msiof2_clk_d_mux[] = {
2955 MSIOF2_SCK_D_MARK,
2956};
2957static const unsigned int msiof2_sync_d_pins[] = {
2958 /* SYNC */
2959 RCAR_GP_PIN(0, 9),
2960};
2961static const unsigned int msiof2_sync_d_mux[] = {
2962 MSIOF2_SYNC_D_MARK,
2963};
2964static const unsigned int msiof2_ss1_d_pins[] = {
2965 /* SS1 */
2966 RCAR_GP_PIN(0, 12),
2967};
2968static const unsigned int msiof2_ss1_d_mux[] = {
2969 MSIOF2_SS1_D_MARK,
2970};
2971static const unsigned int msiof2_ss2_d_pins[] = {
2972 /* SS2 */
2973 RCAR_GP_PIN(0, 13),
2974};
2975static const unsigned int msiof2_ss2_d_mux[] = {
2976 MSIOF2_SS2_D_MARK,
2977};
2978static const unsigned int msiof2_txd_d_pins[] = {
2979 /* TXD */
2980 RCAR_GP_PIN(0, 11),
2981};
2982static const unsigned int msiof2_txd_d_mux[] = {
2983 MSIOF2_TXD_D_MARK,
2984};
2985static const unsigned int msiof2_rxd_d_pins[] = {
2986 /* RXD */
2987 RCAR_GP_PIN(0, 10),
2988};
2989static const unsigned int msiof2_rxd_d_mux[] = {
2990 MSIOF2_RXD_D_MARK,
2991};
2992/* - MSIOF3 ----------------------------------------------------------------- */
2993static const unsigned int msiof3_clk_a_pins[] = {
2994 /* SCK */
2995 RCAR_GP_PIN(0, 0),
2996};
2997static const unsigned int msiof3_clk_a_mux[] = {
2998 MSIOF3_SCK_A_MARK,
2999};
3000static const unsigned int msiof3_sync_a_pins[] = {
3001 /* SYNC */
3002 RCAR_GP_PIN(0, 1),
3003};
3004static const unsigned int msiof3_sync_a_mux[] = {
3005 MSIOF3_SYNC_A_MARK,
3006};
3007static const unsigned int msiof3_ss1_a_pins[] = {
3008 /* SS1 */
3009 RCAR_GP_PIN(0, 14),
3010};
3011static const unsigned int msiof3_ss1_a_mux[] = {
3012 MSIOF3_SS1_A_MARK,
3013};
3014static const unsigned int msiof3_ss2_a_pins[] = {
3015 /* SS2 */
3016 RCAR_GP_PIN(0, 15),
3017};
3018static const unsigned int msiof3_ss2_a_mux[] = {
3019 MSIOF3_SS2_A_MARK,
3020};
3021static const unsigned int msiof3_txd_a_pins[] = {
3022 /* TXD */
3023 RCAR_GP_PIN(0, 3),
3024};
3025static const unsigned int msiof3_txd_a_mux[] = {
3026 MSIOF3_TXD_A_MARK,
3027};
3028static const unsigned int msiof3_rxd_a_pins[] = {
3029 /* RXD */
3030 RCAR_GP_PIN(0, 2),
3031};
3032static const unsigned int msiof3_rxd_a_mux[] = {
3033 MSIOF3_RXD_A_MARK,
3034};
3035static const unsigned int msiof3_clk_b_pins[] = {
3036 /* SCK */
3037 RCAR_GP_PIN(1, 2),
3038};
3039static const unsigned int msiof3_clk_b_mux[] = {
3040 MSIOF3_SCK_B_MARK,
3041};
3042static const unsigned int msiof3_sync_b_pins[] = {
3043 /* SYNC */
3044 RCAR_GP_PIN(1, 0),
3045};
3046static const unsigned int msiof3_sync_b_mux[] = {
3047 MSIOF3_SYNC_B_MARK,
3048};
3049static const unsigned int msiof3_ss1_b_pins[] = {
3050 /* SS1 */
3051 RCAR_GP_PIN(1, 4),
3052};
3053static const unsigned int msiof3_ss1_b_mux[] = {
3054 MSIOF3_SS1_B_MARK,
3055};
3056static const unsigned int msiof3_ss2_b_pins[] = {
3057 /* SS2 */
3058 RCAR_GP_PIN(1, 5),
3059};
3060static const unsigned int msiof3_ss2_b_mux[] = {
3061 MSIOF3_SS2_B_MARK,
3062};
3063static const unsigned int msiof3_txd_b_pins[] = {
3064 /* TXD */
3065 RCAR_GP_PIN(1, 1),
3066};
3067static const unsigned int msiof3_txd_b_mux[] = {
3068 MSIOF3_TXD_B_MARK,
3069};
3070static const unsigned int msiof3_rxd_b_pins[] = {
3071 /* RXD */
3072 RCAR_GP_PIN(1, 3),
3073};
3074static const unsigned int msiof3_rxd_b_mux[] = {
3075 MSIOF3_RXD_B_MARK,
3076};
3077static const unsigned int msiof3_clk_c_pins[] = {
3078 /* SCK */
3079 RCAR_GP_PIN(1, 12),
3080};
3081static const unsigned int msiof3_clk_c_mux[] = {
3082 MSIOF3_SCK_C_MARK,
3083};
3084static const unsigned int msiof3_sync_c_pins[] = {
3085 /* SYNC */
3086 RCAR_GP_PIN(1, 13),
3087};
3088static const unsigned int msiof3_sync_c_mux[] = {
3089 MSIOF3_SYNC_C_MARK,
3090};
3091static const unsigned int msiof3_txd_c_pins[] = {
3092 /* TXD */
3093 RCAR_GP_PIN(1, 15),
3094};
3095static const unsigned int msiof3_txd_c_mux[] = {
3096 MSIOF3_TXD_C_MARK,
3097};
3098static const unsigned int msiof3_rxd_c_pins[] = {
3099 /* RXD */
3100 RCAR_GP_PIN(1, 14),
3101};
3102static const unsigned int msiof3_rxd_c_mux[] = {
3103 MSIOF3_RXD_C_MARK,
3104};
3105static const unsigned int msiof3_clk_d_pins[] = {
3106 /* SCK */
3107 RCAR_GP_PIN(1, 22),
3108};
3109static const unsigned int msiof3_clk_d_mux[] = {
3110 MSIOF3_SCK_D_MARK,
3111};
3112static const unsigned int msiof3_sync_d_pins[] = {
3113 /* SYNC */
3114 RCAR_GP_PIN(1, 23),
3115};
3116static const unsigned int msiof3_sync_d_mux[] = {
3117 MSIOF3_SYNC_D_MARK,
3118};
3119static const unsigned int msiof3_ss1_d_pins[] = {
3120 /* SS1 */
3121 RCAR_GP_PIN(1, 26),
3122};
3123static const unsigned int msiof3_ss1_d_mux[] = {
3124 MSIOF3_SS1_D_MARK,
3125};
3126static const unsigned int msiof3_txd_d_pins[] = {
3127 /* TXD */
3128 RCAR_GP_PIN(1, 25),
3129};
3130static const unsigned int msiof3_txd_d_mux[] = {
3131 MSIOF3_TXD_D_MARK,
3132};
3133static const unsigned int msiof3_rxd_d_pins[] = {
3134 /* RXD */
3135 RCAR_GP_PIN(1, 24),
3136};
3137static const unsigned int msiof3_rxd_d_mux[] = {
3138 MSIOF3_RXD_D_MARK,
3139};
3140
3141static const unsigned int msiof3_clk_e_pins[] = {
3142 /* SCK */
3143 RCAR_GP_PIN(2, 3),
3144};
3145static const unsigned int msiof3_clk_e_mux[] = {
3146 MSIOF3_SCK_E_MARK,
3147};
3148static const unsigned int msiof3_sync_e_pins[] = {
3149 /* SYNC */
3150 RCAR_GP_PIN(2, 2),
3151};
3152static const unsigned int msiof3_sync_e_mux[] = {
3153 MSIOF3_SYNC_E_MARK,
3154};
3155static const unsigned int msiof3_ss1_e_pins[] = {
3156 /* SS1 */
3157 RCAR_GP_PIN(2, 1),
3158};
3159static const unsigned int msiof3_ss1_e_mux[] = {
3160 MSIOF3_SS1_E_MARK,
3161};
3162static const unsigned int msiof3_ss2_e_pins[] = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]3163 /* SS2 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3164 RCAR_GP_PIN(2, 0),
3165};
3166static const unsigned int msiof3_ss2_e_mux[] = {
3167 MSIOF3_SS2_E_MARK,
3168};
3169static const unsigned int msiof3_txd_e_pins[] = {
3170 /* TXD */
3171 RCAR_GP_PIN(2, 5),
3172};
3173static const unsigned int msiof3_txd_e_mux[] = {
3174 MSIOF3_TXD_E_MARK,
3175};
3176static const unsigned int msiof3_rxd_e_pins[] = {
3177 /* RXD */
3178 RCAR_GP_PIN(2, 4),
3179};
3180static const unsigned int msiof3_rxd_e_mux[] = {
3181 MSIOF3_RXD_E_MARK,
3182};
3183
3184/* - PWM0 --------------------------------------------------------------------*/
3185static const unsigned int pwm0_pins[] = {
3186 /* PWM */
3187 RCAR_GP_PIN(2, 6),
3188};
3189static const unsigned int pwm0_mux[] = {
3190 PWM0_MARK,
3191};
3192/* - PWM1 --------------------------------------------------------------------*/
3193static const unsigned int pwm1_a_pins[] = {
3194 /* PWM */
3195 RCAR_GP_PIN(2, 7),
3196};
3197static const unsigned int pwm1_a_mux[] = {
3198 PWM1_A_MARK,
3199};
3200static const unsigned int pwm1_b_pins[] = {
3201 /* PWM */
3202 RCAR_GP_PIN(1, 8),
3203};
3204static const unsigned int pwm1_b_mux[] = {
3205 PWM1_B_MARK,
3206};
3207/* - PWM2 --------------------------------------------------------------------*/
3208static const unsigned int pwm2_a_pins[] = {
3209 /* PWM */
3210 RCAR_GP_PIN(2, 8),
3211};
3212static const unsigned int pwm2_a_mux[] = {
3213 PWM2_A_MARK,
3214};
3215static const unsigned int pwm2_b_pins[] = {
3216 /* PWM */
3217 RCAR_GP_PIN(1, 11),
3218};
3219static const unsigned int pwm2_b_mux[] = {
3220 PWM2_B_MARK,
3221};
3222/* - PWM3 --------------------------------------------------------------------*/
3223static const unsigned int pwm3_a_pins[] = {
3224 /* PWM */
3225 RCAR_GP_PIN(1, 0),
3226};
3227static const unsigned int pwm3_a_mux[] = {
3228 PWM3_A_MARK,
3229};
3230static const unsigned int pwm3_b_pins[] = {
3231 /* PWM */
3232 RCAR_GP_PIN(2, 2),
3233};
3234static const unsigned int pwm3_b_mux[] = {
3235 PWM3_B_MARK,
3236};
3237/* - PWM4 --------------------------------------------------------------------*/
3238static const unsigned int pwm4_a_pins[] = {
3239 /* PWM */
3240 RCAR_GP_PIN(1, 1),
3241};
3242static const unsigned int pwm4_a_mux[] = {
3243 PWM4_A_MARK,
3244};
3245static const unsigned int pwm4_b_pins[] = {
3246 /* PWM */
3247 RCAR_GP_PIN(2, 3),
3248};
3249static const unsigned int pwm4_b_mux[] = {
3250 PWM4_B_MARK,
3251};
3252/* - PWM5 --------------------------------------------------------------------*/
3253static const unsigned int pwm5_a_pins[] = {
3254 /* PWM */
3255 RCAR_GP_PIN(1, 2),
3256};
3257static const unsigned int pwm5_a_mux[] = {
3258 PWM5_A_MARK,
3259};
3260static const unsigned int pwm5_b_pins[] = {
3261 /* PWM */
3262 RCAR_GP_PIN(2, 4),
3263};
3264static const unsigned int pwm5_b_mux[] = {
3265 PWM5_B_MARK,
3266};
3267/* - PWM6 --------------------------------------------------------------------*/
3268static const unsigned int pwm6_a_pins[] = {
3269 /* PWM */
3270 RCAR_GP_PIN(1, 3),
3271};
3272static const unsigned int pwm6_a_mux[] = {
3273 PWM6_A_MARK,
3274};
3275static const unsigned int pwm6_b_pins[] = {
3276 /* PWM */
3277 RCAR_GP_PIN(2, 5),
3278};
3279static const unsigned int pwm6_b_mux[] = {
3280 PWM6_B_MARK,
3281};
3282
3283/* - SCIF0 ------------------------------------------------------------------ */
3284static const unsigned int scif0_data_pins[] = {
3285 /* RX, TX */
3286 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3287};
3288static const unsigned int scif0_data_mux[] = {
3289 RX0_MARK, TX0_MARK,
3290};
3291static const unsigned int scif0_clk_pins[] = {
3292 /* SCK */
3293 RCAR_GP_PIN(5, 0),
3294};
3295static const unsigned int scif0_clk_mux[] = {
3296 SCK0_MARK,
3297};
3298static const unsigned int scif0_ctrl_pins[] = {
3299 /* RTS, CTS */
3300 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3301};
3302static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3303 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3304};
3305/* - SCIF1 ------------------------------------------------------------------ */
3306static const unsigned int scif1_data_a_pins[] = {
3307 /* RX, TX */
3308 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3309};
3310static const unsigned int scif1_data_a_mux[] = {
3311 RX1_A_MARK, TX1_A_MARK,
3312};
3313static const unsigned int scif1_clk_pins[] = {
3314 /* SCK */
3315 RCAR_GP_PIN(6, 21),
3316};
3317static const unsigned int scif1_clk_mux[] = {
3318 SCK1_MARK,
3319};
3320static const unsigned int scif1_ctrl_pins[] = {
3321 /* RTS, CTS */
3322 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3323};
3324static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3325 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3326};
3327
3328static const unsigned int scif1_data_b_pins[] = {
3329 /* RX, TX */
3330 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3331};
3332static const unsigned int scif1_data_b_mux[] = {
3333 RX1_B_MARK, TX1_B_MARK,
3334};
3335/* - SCIF2 ------------------------------------------------------------------ */
3336static const unsigned int scif2_data_a_pins[] = {
3337 /* RX, TX */
3338 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3339};
3340static const unsigned int scif2_data_a_mux[] = {
3341 RX2_A_MARK, TX2_A_MARK,
3342};
3343static const unsigned int scif2_clk_pins[] = {
3344 /* SCK */
3345 RCAR_GP_PIN(5, 9),
3346};
3347static const unsigned int scif2_clk_mux[] = {
3348 SCK2_MARK,
3349};
3350static const unsigned int scif2_data_b_pins[] = {
3351 /* RX, TX */
3352 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3353};
3354static const unsigned int scif2_data_b_mux[] = {
3355 RX2_B_MARK, TX2_B_MARK,
3356};
3357/* - SCIF3 ------------------------------------------------------------------ */
3358static const unsigned int scif3_data_a_pins[] = {
3359 /* RX, TX */
3360 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3361};
3362static const unsigned int scif3_data_a_mux[] = {
3363 RX3_A_MARK, TX3_A_MARK,
3364};
3365static const unsigned int scif3_clk_pins[] = {
3366 /* SCK */
3367 RCAR_GP_PIN(1, 22),
3368};
3369static const unsigned int scif3_clk_mux[] = {
3370 SCK3_MARK,
3371};
3372static const unsigned int scif3_ctrl_pins[] = {
3373 /* RTS, CTS */
3374 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3375};
3376static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3377 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3378};
3379static const unsigned int scif3_data_b_pins[] = {
3380 /* RX, TX */
3381 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3382};
3383static const unsigned int scif3_data_b_mux[] = {
3384 RX3_B_MARK, TX3_B_MARK,
3385};
3386/* - SCIF4 ------------------------------------------------------------------ */
3387static const unsigned int scif4_data_a_pins[] = {
3388 /* RX, TX */
3389 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3390};
3391static const unsigned int scif4_data_a_mux[] = {
3392 RX4_A_MARK, TX4_A_MARK,
3393};
3394static const unsigned int scif4_clk_a_pins[] = {
3395 /* SCK */
3396 RCAR_GP_PIN(2, 10),
3397};
3398static const unsigned int scif4_clk_a_mux[] = {
3399 SCK4_A_MARK,
3400};
3401static const unsigned int scif4_ctrl_a_pins[] = {
3402 /* RTS, CTS */
3403 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3404};
3405static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3406 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3407};
3408static const unsigned int scif4_data_b_pins[] = {
3409 /* RX, TX */
3410 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3411};
3412static const unsigned int scif4_data_b_mux[] = {
3413 RX4_B_MARK, TX4_B_MARK,
3414};
3415static const unsigned int scif4_clk_b_pins[] = {
3416 /* SCK */
3417 RCAR_GP_PIN(1, 5),
3418};
3419static const unsigned int scif4_clk_b_mux[] = {
3420 SCK4_B_MARK,
3421};
3422static const unsigned int scif4_ctrl_b_pins[] = {
3423 /* RTS, CTS */
3424 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3425};
3426static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3427 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3428};
3429static const unsigned int scif4_data_c_pins[] = {
3430 /* RX, TX */
3431 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3432};
3433static const unsigned int scif4_data_c_mux[] = {
3434 RX4_C_MARK, TX4_C_MARK,
3435};
3436static const unsigned int scif4_clk_c_pins[] = {
3437 /* SCK */
3438 RCAR_GP_PIN(0, 8),
3439};
3440static const unsigned int scif4_clk_c_mux[] = {
3441 SCK4_C_MARK,
3442};
3443static const unsigned int scif4_ctrl_c_pins[] = {
3444 /* RTS, CTS */
3445 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3446};
3447static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3448 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3449};
3450/* - SCIF5 ------------------------------------------------------------------ */
3451static const unsigned int scif5_data_a_pins[] = {
3452 /* RX, TX */
3453 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3454};
3455static const unsigned int scif5_data_a_mux[] = {
3456 RX5_A_MARK, TX5_A_MARK,
3457};
3458static const unsigned int scif5_clk_a_pins[] = {
3459 /* SCK */
3460 RCAR_GP_PIN(6, 21),
3461};
3462static const unsigned int scif5_clk_a_mux[] = {
3463 SCK5_A_MARK,
3464};
3465
3466static const unsigned int scif5_data_b_pins[] = {
3467 /* RX, TX */
3468 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3469};
3470static const unsigned int scif5_data_b_mux[] = {
3471 RX5_B_MARK, TX5_B_MARK,
3472};
3473static const unsigned int scif5_clk_b_pins[] = {
3474 /* SCK */
3475 RCAR_GP_PIN(5, 0),
3476};
3477static const unsigned int scif5_clk_b_mux[] = {
3478 SCK5_B_MARK,
3479};
3480
3481/* - SCIF Clock ------------------------------------------------------------- */
3482static const unsigned int scif_clk_a_pins[] = {
3483 /* SCIF_CLK */
3484 RCAR_GP_PIN(6, 23),
3485};
3486static const unsigned int scif_clk_a_mux[] = {
3487 SCIF_CLK_A_MARK,
3488};
3489static const unsigned int scif_clk_b_pins[] = {
3490 /* SCIF_CLK */
3491 RCAR_GP_PIN(5, 9),
3492};
3493static const unsigned int scif_clk_b_mux[] = {
3494 SCIF_CLK_B_MARK,
3495};
3496
3497/* - SDHI0 ------------------------------------------------------------------ */
3498static const unsigned int sdhi0_data1_pins[] = {
3499 /* D0 */
3500 RCAR_GP_PIN(3, 2),
3501};
3502static const unsigned int sdhi0_data1_mux[] = {
3503 SD0_DAT0_MARK,
3504};
3505static const unsigned int sdhi0_data4_pins[] = {
3506 /* D[0:3] */
3507 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3508 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3509};
3510static const unsigned int sdhi0_data4_mux[] = {
3511 SD0_DAT0_MARK, SD0_DAT1_MARK,
3512 SD0_DAT2_MARK, SD0_DAT3_MARK,
3513};
3514static const unsigned int sdhi0_ctrl_pins[] = {
3515 /* CLK, CMD */
3516 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3517};
3518static const unsigned int sdhi0_ctrl_mux[] = {
3519 SD0_CLK_MARK, SD0_CMD_MARK,
3520};
3521static const unsigned int sdhi0_cd_pins[] = {
3522 /* CD */
3523 RCAR_GP_PIN(3, 12),
3524};
3525static const unsigned int sdhi0_cd_mux[] = {
3526 SD0_CD_MARK,
3527};
3528static const unsigned int sdhi0_wp_pins[] = {
3529 /* WP */
3530 RCAR_GP_PIN(3, 13),
3531};
3532static const unsigned int sdhi0_wp_mux[] = {
3533 SD0_WP_MARK,
3534};
3535/* - SDHI1 ------------------------------------------------------------------ */
3536static const unsigned int sdhi1_data1_pins[] = {
3537 /* D0 */
3538 RCAR_GP_PIN(3, 8),
3539};
3540static const unsigned int sdhi1_data1_mux[] = {
3541 SD1_DAT0_MARK,
3542};
3543static const unsigned int sdhi1_data4_pins[] = {
3544 /* D[0:3] */
3545 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3546 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3547};
3548static const unsigned int sdhi1_data4_mux[] = {
3549 SD1_DAT0_MARK, SD1_DAT1_MARK,
3550 SD1_DAT2_MARK, SD1_DAT3_MARK,
3551};
3552static const unsigned int sdhi1_ctrl_pins[] = {
3553 /* CLK, CMD */
3554 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3555};
3556static const unsigned int sdhi1_ctrl_mux[] = {
3557 SD1_CLK_MARK, SD1_CMD_MARK,
3558};
3559static const unsigned int sdhi1_cd_pins[] = {
3560 /* CD */
3561 RCAR_GP_PIN(3, 14),
3562};
3563static const unsigned int sdhi1_cd_mux[] = {
3564 SD1_CD_MARK,
3565};
3566static const unsigned int sdhi1_wp_pins[] = {
3567 /* WP */
3568 RCAR_GP_PIN(3, 15),
3569};
3570static const unsigned int sdhi1_wp_mux[] = {
3571 SD1_WP_MARK,
3572};
3573/* - SDHI2 ------------------------------------------------------------------ */
3574static const unsigned int sdhi2_data1_pins[] = {
3575 /* D0 */
3576 RCAR_GP_PIN(4, 2),
3577};
3578static const unsigned int sdhi2_data1_mux[] = {
3579 SD2_DAT0_MARK,
3580};
3581static const unsigned int sdhi2_data4_pins[] = {
3582 /* D[0:3] */
3583 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3584 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3585};
3586static const unsigned int sdhi2_data4_mux[] = {
3587 SD2_DAT0_MARK, SD2_DAT1_MARK,
3588 SD2_DAT2_MARK, SD2_DAT3_MARK,
3589};
3590static const unsigned int sdhi2_data8_pins[] = {
3591 /* D[0:7] */
3592 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3593 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3594 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3595 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3596};
3597static const unsigned int sdhi2_data8_mux[] = {
3598 SD2_DAT0_MARK, SD2_DAT1_MARK,
3599 SD2_DAT2_MARK, SD2_DAT3_MARK,
3600 SD2_DAT4_MARK, SD2_DAT5_MARK,
3601 SD2_DAT6_MARK, SD2_DAT7_MARK,
3602};
3603static const unsigned int sdhi2_ctrl_pins[] = {
3604 /* CLK, CMD */
3605 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3606};
3607static const unsigned int sdhi2_ctrl_mux[] = {
3608 SD2_CLK_MARK, SD2_CMD_MARK,
3609};
3610static const unsigned int sdhi2_cd_a_pins[] = {
3611 /* CD */
3612 RCAR_GP_PIN(4, 13),
3613};
3614static const unsigned int sdhi2_cd_a_mux[] = {
3615 SD2_CD_A_MARK,
3616};
3617static const unsigned int sdhi2_cd_b_pins[] = {
3618 /* CD */
3619 RCAR_GP_PIN(5, 10),
3620};
3621static const unsigned int sdhi2_cd_b_mux[] = {
3622 SD2_CD_B_MARK,
3623};
3624static const unsigned int sdhi2_wp_a_pins[] = {
3625 /* WP */
3626 RCAR_GP_PIN(4, 14),
3627};
3628static const unsigned int sdhi2_wp_a_mux[] = {
3629 SD2_WP_A_MARK,
3630};
3631static const unsigned int sdhi2_wp_b_pins[] = {
3632 /* WP */
3633 RCAR_GP_PIN(5, 11),
3634};
3635static const unsigned int sdhi2_wp_b_mux[] = {
3636 SD2_WP_B_MARK,
3637};
3638static const unsigned int sdhi2_ds_pins[] = {
3639 /* DS */
3640 RCAR_GP_PIN(4, 6),
3641};
3642static const unsigned int sdhi2_ds_mux[] = {
3643 SD2_DS_MARK,
3644};
3645/* - SDHI3 ------------------------------------------------------------------ */
3646static const unsigned int sdhi3_data1_pins[] = {
3647 /* D0 */
3648 RCAR_GP_PIN(4, 9),
3649};
3650static const unsigned int sdhi3_data1_mux[] = {
3651 SD3_DAT0_MARK,
3652};
3653static const unsigned int sdhi3_data4_pins[] = {
3654 /* D[0:3] */
3655 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3656 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3657};
3658static const unsigned int sdhi3_data4_mux[] = {
3659 SD3_DAT0_MARK, SD3_DAT1_MARK,
3660 SD3_DAT2_MARK, SD3_DAT3_MARK,
3661};
3662static const unsigned int sdhi3_data8_pins[] = {
3663 /* D[0:7] */
3664 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3665 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3666 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3667 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3668};
3669static const unsigned int sdhi3_data8_mux[] = {
3670 SD3_DAT0_MARK, SD3_DAT1_MARK,
3671 SD3_DAT2_MARK, SD3_DAT3_MARK,
3672 SD3_DAT4_MARK, SD3_DAT5_MARK,
3673 SD3_DAT6_MARK, SD3_DAT7_MARK,
3674};
3675static const unsigned int sdhi3_ctrl_pins[] = {
3676 /* CLK, CMD */
3677 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3678};
3679static const unsigned int sdhi3_ctrl_mux[] = {
3680 SD3_CLK_MARK, SD3_CMD_MARK,
3681};
3682static const unsigned int sdhi3_cd_pins[] = {
3683 /* CD */
3684 RCAR_GP_PIN(4, 15),
3685};
3686static const unsigned int sdhi3_cd_mux[] = {
3687 SD3_CD_MARK,
3688};
3689static const unsigned int sdhi3_wp_pins[] = {
3690 /* WP */
3691 RCAR_GP_PIN(4, 16),
3692};
3693static const unsigned int sdhi3_wp_mux[] = {
3694 SD3_WP_MARK,
3695};
3696static const unsigned int sdhi3_ds_pins[] = {
3697 /* DS */
3698 RCAR_GP_PIN(4, 17),
3699};
3700static const unsigned int sdhi3_ds_mux[] = {
3701 SD3_DS_MARK,
3702};
3703
3704/* - SSI -------------------------------------------------------------------- */
3705static const unsigned int ssi0_data_pins[] = {
3706 /* SDATA */
3707 RCAR_GP_PIN(6, 2),
3708};
3709static const unsigned int ssi0_data_mux[] = {
3710 SSI_SDATA0_MARK,
3711};
3712static const unsigned int ssi01239_ctrl_pins[] = {
3713 /* SCK, WS */
3714 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3715};
3716static const unsigned int ssi01239_ctrl_mux[] = {
3717 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3718};
3719static const unsigned int ssi1_data_a_pins[] = {
3720 /* SDATA */
3721 RCAR_GP_PIN(6, 3),
3722};
3723static const unsigned int ssi1_data_a_mux[] = {
3724 SSI_SDATA1_A_MARK,
3725};
3726static const unsigned int ssi1_data_b_pins[] = {
3727 /* SDATA */
3728 RCAR_GP_PIN(5, 12),
3729};
3730static const unsigned int ssi1_data_b_mux[] = {
3731 SSI_SDATA1_B_MARK,
3732};
3733static const unsigned int ssi1_ctrl_a_pins[] = {
3734 /* SCK, WS */
3735 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3736};
3737static const unsigned int ssi1_ctrl_a_mux[] = {
3738 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3739};
3740static const unsigned int ssi1_ctrl_b_pins[] = {
3741 /* SCK, WS */
3742 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3743};
3744static const unsigned int ssi1_ctrl_b_mux[] = {
3745 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3746};
3747static const unsigned int ssi2_data_a_pins[] = {
3748 /* SDATA */
3749 RCAR_GP_PIN(6, 4),
3750};
3751static const unsigned int ssi2_data_a_mux[] = {
3752 SSI_SDATA2_A_MARK,
3753};
3754static const unsigned int ssi2_data_b_pins[] = {
3755 /* SDATA */
3756 RCAR_GP_PIN(5, 13),
3757};
3758static const unsigned int ssi2_data_b_mux[] = {
3759 SSI_SDATA2_B_MARK,
3760};
3761static const unsigned int ssi2_ctrl_a_pins[] = {
3762 /* SCK, WS */
3763 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3764};
3765static const unsigned int ssi2_ctrl_a_mux[] = {
3766 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3767};
3768static const unsigned int ssi2_ctrl_b_pins[] = {
3769 /* SCK, WS */
3770 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3771};
3772static const unsigned int ssi2_ctrl_b_mux[] = {
3773 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3774};
3775static const unsigned int ssi3_data_pins[] = {
3776 /* SDATA */
3777 RCAR_GP_PIN(6, 7),
3778};
3779static const unsigned int ssi3_data_mux[] = {
3780 SSI_SDATA3_MARK,
3781};
3782static const unsigned int ssi349_ctrl_pins[] = {
3783 /* SCK, WS */
3784 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3785};
3786static const unsigned int ssi349_ctrl_mux[] = {
3787 SSI_SCK349_MARK, SSI_WS349_MARK,
3788};
3789static const unsigned int ssi4_data_pins[] = {
3790 /* SDATA */
3791 RCAR_GP_PIN(6, 10),
3792};
3793static const unsigned int ssi4_data_mux[] = {
3794 SSI_SDATA4_MARK,
3795};
3796static const unsigned int ssi4_ctrl_pins[] = {
3797 /* SCK, WS */
3798 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3799};
3800static const unsigned int ssi4_ctrl_mux[] = {
3801 SSI_SCK4_MARK, SSI_WS4_MARK,
3802};
3803static const unsigned int ssi5_data_pins[] = {
3804 /* SDATA */
3805 RCAR_GP_PIN(6, 13),
3806};
3807static const unsigned int ssi5_data_mux[] = {
3808 SSI_SDATA5_MARK,
3809};
3810static const unsigned int ssi5_ctrl_pins[] = {
3811 /* SCK, WS */
3812 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3813};
3814static const unsigned int ssi5_ctrl_mux[] = {
3815 SSI_SCK5_MARK, SSI_WS5_MARK,
3816};
3817static const unsigned int ssi6_data_pins[] = {
3818 /* SDATA */
3819 RCAR_GP_PIN(6, 16),
3820};
3821static const unsigned int ssi6_data_mux[] = {
3822 SSI_SDATA6_MARK,
3823};
3824static const unsigned int ssi6_ctrl_pins[] = {
3825 /* SCK, WS */
3826 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3827};
3828static const unsigned int ssi6_ctrl_mux[] = {
3829 SSI_SCK6_MARK, SSI_WS6_MARK,
3830};
3831static const unsigned int ssi7_data_pins[] = {
3832 /* SDATA */
3833 RCAR_GP_PIN(6, 19),
3834};
3835static const unsigned int ssi7_data_mux[] = {
3836 SSI_SDATA7_MARK,
3837};
3838static const unsigned int ssi78_ctrl_pins[] = {
3839 /* SCK, WS */
3840 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3841};
3842static const unsigned int ssi78_ctrl_mux[] = {
3843 SSI_SCK78_MARK, SSI_WS78_MARK,
3844};
3845static const unsigned int ssi8_data_pins[] = {
3846 /* SDATA */
3847 RCAR_GP_PIN(6, 20),
3848};
3849static const unsigned int ssi8_data_mux[] = {
3850 SSI_SDATA8_MARK,
3851};
3852static const unsigned int ssi9_data_a_pins[] = {
3853 /* SDATA */
3854 RCAR_GP_PIN(6, 21),
3855};
3856static const unsigned int ssi9_data_a_mux[] = {
3857 SSI_SDATA9_A_MARK,
3858};
3859static const unsigned int ssi9_data_b_pins[] = {
3860 /* SDATA */
3861 RCAR_GP_PIN(5, 14),
3862};
3863static const unsigned int ssi9_data_b_mux[] = {
3864 SSI_SDATA9_B_MARK,
3865};
3866static const unsigned int ssi9_ctrl_a_pins[] = {
3867 /* SCK, WS */
3868 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3869};
3870static const unsigned int ssi9_ctrl_a_mux[] = {
3871 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3872};
3873static const unsigned int ssi9_ctrl_b_pins[] = {
3874 /* SCK, WS */
3875 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3876};
3877static const unsigned int ssi9_ctrl_b_mux[] = {
3878 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3879};
3880
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3881/* - TMU -------------------------------------------------------------------- */
3882static const unsigned int tmu_tclk1_a_pins[] = {
3883 /* TCLK */
3884 RCAR_GP_PIN(6, 23),
3885};
3886static const unsigned int tmu_tclk1_a_mux[] = {
3887 TCLK1_A_MARK,
3888};
3889static const unsigned int tmu_tclk1_b_pins[] = {
3890 /* TCLK */
3891 RCAR_GP_PIN(5, 19),
3892};
3893static const unsigned int tmu_tclk1_b_mux[] = {
3894 TCLK1_B_MARK,
3895};
3896static const unsigned int tmu_tclk2_a_pins[] = {
3897 /* TCLK */
3898 RCAR_GP_PIN(6, 19),
3899};
3900static const unsigned int tmu_tclk2_a_mux[] = {
3901 TCLK2_A_MARK,
3902};
3903static const unsigned int tmu_tclk2_b_pins[] = {
3904 /* TCLK */
3905 RCAR_GP_PIN(6, 28),
3906};
3907static const unsigned int tmu_tclk2_b_mux[] = {
3908 TCLK2_B_MARK,
3909};
3910
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3911/* - USB0 ------------------------------------------------------------------- */
3912static const unsigned int usb0_pins[] = {
3913 /* PWEN, OVC */
3914 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3915};
3916static const unsigned int usb0_mux[] = {
3917 USB0_PWEN_MARK, USB0_OVC_MARK,
3918};
3919/* - USB1 ------------------------------------------------------------------- */
3920static const unsigned int usb1_pins[] = {
3921 /* PWEN, OVC */
3922 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3923};
3924static const unsigned int usb1_mux[] = {
3925 USB1_PWEN_MARK, USB1_OVC_MARK,
3926};
3927
3928/* - USB30 ------------------------------------------------------------------ */
3929static const unsigned int usb30_pins[] = {
3930 /* PWEN, OVC */
3931 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3932};
3933static const unsigned int usb30_mux[] = {
3934 USB30_PWEN_MARK, USB30_OVC_MARK,
3935};
3936
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3937/* - VIN4 ------------------------------------------------------------------- */
3938static const unsigned int vin4_data18_a_pins[] = {
3939 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3940 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3941 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3942 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3943 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3944 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3945 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3946 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3947 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3948};
3949static const unsigned int vin4_data18_a_mux[] = {
3950 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3951 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3952 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3953 VI4_DATA10_MARK, VI4_DATA11_MARK,
3954 VI4_DATA12_MARK, VI4_DATA13_MARK,
3955 VI4_DATA14_MARK, VI4_DATA15_MARK,
3956 VI4_DATA18_MARK, VI4_DATA19_MARK,
3957 VI4_DATA20_MARK, VI4_DATA21_MARK,
3958 VI4_DATA22_MARK, VI4_DATA23_MARK,
3959};
3960static const unsigned int vin4_data18_b_pins[] = {
3961 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3962 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3963 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3964 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3965 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3966 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3967 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3968 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3969 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3970};
3971static const unsigned int vin4_data18_b_mux[] = {
3972 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3973 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3974 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3975 VI4_DATA10_MARK, VI4_DATA11_MARK,
3976 VI4_DATA12_MARK, VI4_DATA13_MARK,
3977 VI4_DATA14_MARK, VI4_DATA15_MARK,
3978 VI4_DATA18_MARK, VI4_DATA19_MARK,
3979 VI4_DATA20_MARK, VI4_DATA21_MARK,
3980 VI4_DATA22_MARK, VI4_DATA23_MARK,
3981};
3982static const union vin_data vin4_data_a_pins = {
3983 .data24 = {
3984 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3985 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3986 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3987 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3988 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3989 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3990 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3991 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3992 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3993 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3994 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3995 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3996 },
3997};
3998static const union vin_data vin4_data_a_mux = {
3999 .data24 = {
4000 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4001 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4002 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4003 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4004 VI4_DATA8_MARK, VI4_DATA9_MARK,
4005 VI4_DATA10_MARK, VI4_DATA11_MARK,
4006 VI4_DATA12_MARK, VI4_DATA13_MARK,
4007 VI4_DATA14_MARK, VI4_DATA15_MARK,
4008 VI4_DATA16_MARK, VI4_DATA17_MARK,
4009 VI4_DATA18_MARK, VI4_DATA19_MARK,
4010 VI4_DATA20_MARK, VI4_DATA21_MARK,
4011 VI4_DATA22_MARK, VI4_DATA23_MARK,
4012 },
4013};
4014static const union vin_data vin4_data_b_pins = {
4015 .data24 = {
4016 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4017 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4018 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4019 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4020 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4021 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4022 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4023 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4024 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4025 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4026 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4027 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4028 },
4029};
4030static const union vin_data vin4_data_b_mux = {
4031 .data24 = {
4032 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4033 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4034 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4035 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4036 VI4_DATA8_MARK, VI4_DATA9_MARK,
4037 VI4_DATA10_MARK, VI4_DATA11_MARK,
4038 VI4_DATA12_MARK, VI4_DATA13_MARK,
4039 VI4_DATA14_MARK, VI4_DATA15_MARK,
4040 VI4_DATA16_MARK, VI4_DATA17_MARK,
4041 VI4_DATA18_MARK, VI4_DATA19_MARK,
4042 VI4_DATA20_MARK, VI4_DATA21_MARK,
4043 VI4_DATA22_MARK, VI4_DATA23_MARK,
4044 },
4045};
4046static const unsigned int vin4_sync_pins[] = {
4047 /* HSYNC#, VSYNC# */
4048 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4049};
4050static const unsigned int vin4_sync_mux[] = {
4051 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4052};
4053static const unsigned int vin4_field_pins[] = {
4054 /* FIELD */
4055 RCAR_GP_PIN(1, 16),
4056};
4057static const unsigned int vin4_field_mux[] = {
4058 VI4_FIELD_MARK,
4059};
4060static const unsigned int vin4_clkenb_pins[] = {
4061 /* CLKENB */
4062 RCAR_GP_PIN(1, 19),
4063};
4064static const unsigned int vin4_clkenb_mux[] = {
4065 VI4_CLKENB_MARK,
4066};
4067static const unsigned int vin4_clk_pins[] = {
4068 /* CLK */
4069 RCAR_GP_PIN(1, 27),
4070};
4071static const unsigned int vin4_clk_mux[] = {
4072 VI4_CLK_MARK,
4073};
4074
4075/* - VIN5 ------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4076static const union vin_data16 vin5_data_pins = {
4077 .data16 = {
4078 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4079 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4080 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4081 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4082 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4083 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4084 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4085 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4086 },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4087};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4088static const union vin_data16 vin5_data_mux = {
4089 .data16 = {
4090 VI5_DATA0_MARK, VI5_DATA1_MARK,
4091 VI5_DATA2_MARK, VI5_DATA3_MARK,
4092 VI5_DATA4_MARK, VI5_DATA5_MARK,
4093 VI5_DATA6_MARK, VI5_DATA7_MARK,
4094 VI5_DATA8_MARK, VI5_DATA9_MARK,
4095 VI5_DATA10_MARK, VI5_DATA11_MARK,
4096 VI5_DATA12_MARK, VI5_DATA13_MARK,
4097 VI5_DATA14_MARK, VI5_DATA15_MARK,
4098 },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4099};
4100static const unsigned int vin5_sync_pins[] = {
4101 /* HSYNC#, VSYNC# */
4102 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4103};
4104static const unsigned int vin5_sync_mux[] = {
4105 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4106};
4107static const unsigned int vin5_field_pins[] = {
4108 RCAR_GP_PIN(1, 11),
4109};
4110static const unsigned int vin5_field_mux[] = {
4111 /* FIELD */
4112 VI5_FIELD_MARK,
4113};
4114static const unsigned int vin5_clkenb_pins[] = {
4115 RCAR_GP_PIN(1, 20),
4116};
4117static const unsigned int vin5_clkenb_mux[] = {
4118 /* CLKENB */
4119 VI5_CLKENB_MARK,
4120};
4121static const unsigned int vin5_clk_pins[] = {
4122 RCAR_GP_PIN(1, 21),
4123};
4124static const unsigned int vin5_clk_mux[] = {
4125 /* CLK */
4126 VI5_CLK_MARK,
4127};
4128
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4129static const struct {
4130 struct sh_pfc_pin_group common[310];
4131 struct sh_pfc_pin_group automotive[33];
4132} pinmux_groups = {
4133 .common = {
4134 SH_PFC_PIN_GROUP(audio_clk_a_a),
4135 SH_PFC_PIN_GROUP(audio_clk_a_b),
4136 SH_PFC_PIN_GROUP(audio_clk_a_c),
4137 SH_PFC_PIN_GROUP(audio_clk_b_a),
4138 SH_PFC_PIN_GROUP(audio_clk_b_b),
4139 SH_PFC_PIN_GROUP(audio_clk_c_a),
4140 SH_PFC_PIN_GROUP(audio_clk_c_b),
4141 SH_PFC_PIN_GROUP(audio_clkout_a),
4142 SH_PFC_PIN_GROUP(audio_clkout_b),
4143 SH_PFC_PIN_GROUP(audio_clkout_c),
4144 SH_PFC_PIN_GROUP(audio_clkout_d),
4145 SH_PFC_PIN_GROUP(audio_clkout1_a),
4146 SH_PFC_PIN_GROUP(audio_clkout1_b),
4147 SH_PFC_PIN_GROUP(audio_clkout2_a),
4148 SH_PFC_PIN_GROUP(audio_clkout2_b),
4149 SH_PFC_PIN_GROUP(audio_clkout3_a),
4150 SH_PFC_PIN_GROUP(audio_clkout3_b),
4151 SH_PFC_PIN_GROUP(avb_link),
4152 SH_PFC_PIN_GROUP(avb_magic),
4153 SH_PFC_PIN_GROUP(avb_phy_int),
4154 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4155 SH_PFC_PIN_GROUP(avb_mdio),
4156 SH_PFC_PIN_GROUP(avb_mii),
4157 SH_PFC_PIN_GROUP(avb_avtp_pps),
4158 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4159 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4160 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4161 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4162 SH_PFC_PIN_GROUP(can0_data_a),
4163 SH_PFC_PIN_GROUP(can0_data_b),
4164 SH_PFC_PIN_GROUP(can1_data),
4165 SH_PFC_PIN_GROUP(can_clk),
4166 SH_PFC_PIN_GROUP(du_rgb666),
4167 SH_PFC_PIN_GROUP(du_rgb888),
4168 SH_PFC_PIN_GROUP(du_clk_out_0),
4169 SH_PFC_PIN_GROUP(du_clk_out_1),
4170 SH_PFC_PIN_GROUP(du_sync),
4171 SH_PFC_PIN_GROUP(du_oddf),
4172 SH_PFC_PIN_GROUP(du_cde),
4173 SH_PFC_PIN_GROUP(du_disp),
4174 SH_PFC_PIN_GROUP(hdmi0_cec),
4175 SH_PFC_PIN_GROUP(hscif0_data),
4176 SH_PFC_PIN_GROUP(hscif0_clk),
4177 SH_PFC_PIN_GROUP(hscif0_ctrl),
4178 SH_PFC_PIN_GROUP(hscif1_data_a),
4179 SH_PFC_PIN_GROUP(hscif1_clk_a),
4180 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4181 SH_PFC_PIN_GROUP(hscif1_data_b),
4182 SH_PFC_PIN_GROUP(hscif1_clk_b),
4183 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4184 SH_PFC_PIN_GROUP(hscif2_data_a),
4185 SH_PFC_PIN_GROUP(hscif2_clk_a),
4186 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4187 SH_PFC_PIN_GROUP(hscif2_data_b),
4188 SH_PFC_PIN_GROUP(hscif2_clk_b),
4189 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4190 SH_PFC_PIN_GROUP(hscif2_data_c),
4191 SH_PFC_PIN_GROUP(hscif2_clk_c),
4192 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4193 SH_PFC_PIN_GROUP(hscif3_data_a),
4194 SH_PFC_PIN_GROUP(hscif3_clk),
4195 SH_PFC_PIN_GROUP(hscif3_ctrl),
4196 SH_PFC_PIN_GROUP(hscif3_data_b),
4197 SH_PFC_PIN_GROUP(hscif3_data_c),
4198 SH_PFC_PIN_GROUP(hscif3_data_d),
4199 SH_PFC_PIN_GROUP(hscif4_data_a),
4200 SH_PFC_PIN_GROUP(hscif4_clk),
4201 SH_PFC_PIN_GROUP(hscif4_ctrl),
4202 SH_PFC_PIN_GROUP(hscif4_data_b),
4203 SH_PFC_PIN_GROUP(i2c0),
4204 SH_PFC_PIN_GROUP(i2c1_a),
4205 SH_PFC_PIN_GROUP(i2c1_b),
4206 SH_PFC_PIN_GROUP(i2c2_a),
4207 SH_PFC_PIN_GROUP(i2c2_b),
4208 SH_PFC_PIN_GROUP(i2c3),
4209 SH_PFC_PIN_GROUP(i2c5),
4210 SH_PFC_PIN_GROUP(i2c6_a),
4211 SH_PFC_PIN_GROUP(i2c6_b),
4212 SH_PFC_PIN_GROUP(i2c6_c),
4213 SH_PFC_PIN_GROUP(intc_ex_irq0),
4214 SH_PFC_PIN_GROUP(intc_ex_irq1),
4215 SH_PFC_PIN_GROUP(intc_ex_irq2),
4216 SH_PFC_PIN_GROUP(intc_ex_irq3),
4217 SH_PFC_PIN_GROUP(intc_ex_irq4),
4218 SH_PFC_PIN_GROUP(intc_ex_irq5),
4219 SH_PFC_PIN_GROUP(msiof0_clk),
4220 SH_PFC_PIN_GROUP(msiof0_sync),
4221 SH_PFC_PIN_GROUP(msiof0_ss1),
4222 SH_PFC_PIN_GROUP(msiof0_ss2),
4223 SH_PFC_PIN_GROUP(msiof0_txd),
4224 SH_PFC_PIN_GROUP(msiof0_rxd),
4225 SH_PFC_PIN_GROUP(msiof1_clk_a),
4226 SH_PFC_PIN_GROUP(msiof1_sync_a),
4227 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4228 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4229 SH_PFC_PIN_GROUP(msiof1_txd_a),
4230 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4231 SH_PFC_PIN_GROUP(msiof1_clk_b),
4232 SH_PFC_PIN_GROUP(msiof1_sync_b),
4233 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4234 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4235 SH_PFC_PIN_GROUP(msiof1_txd_b),
4236 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4237 SH_PFC_PIN_GROUP(msiof1_clk_c),
4238 SH_PFC_PIN_GROUP(msiof1_sync_c),
4239 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4240 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4241 SH_PFC_PIN_GROUP(msiof1_txd_c),
4242 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4243 SH_PFC_PIN_GROUP(msiof1_clk_d),
4244 SH_PFC_PIN_GROUP(msiof1_sync_d),
4245 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4246 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4247 SH_PFC_PIN_GROUP(msiof1_txd_d),
4248 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4249 SH_PFC_PIN_GROUP(msiof1_clk_e),
4250 SH_PFC_PIN_GROUP(msiof1_sync_e),
4251 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4252 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4253 SH_PFC_PIN_GROUP(msiof1_txd_e),
4254 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4255 SH_PFC_PIN_GROUP(msiof1_clk_f),
4256 SH_PFC_PIN_GROUP(msiof1_sync_f),
4257 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4258 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4259 SH_PFC_PIN_GROUP(msiof1_txd_f),
4260 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4261 SH_PFC_PIN_GROUP(msiof1_clk_g),
4262 SH_PFC_PIN_GROUP(msiof1_sync_g),
4263 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4264 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4265 SH_PFC_PIN_GROUP(msiof1_txd_g),
4266 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4267 SH_PFC_PIN_GROUP(msiof2_clk_a),
4268 SH_PFC_PIN_GROUP(msiof2_sync_a),
4269 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4270 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4271 SH_PFC_PIN_GROUP(msiof2_txd_a),
4272 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4273 SH_PFC_PIN_GROUP(msiof2_clk_b),
4274 SH_PFC_PIN_GROUP(msiof2_sync_b),
4275 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4276 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4277 SH_PFC_PIN_GROUP(msiof2_txd_b),
4278 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4279 SH_PFC_PIN_GROUP(msiof2_clk_c),
4280 SH_PFC_PIN_GROUP(msiof2_sync_c),
4281 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4282 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4283 SH_PFC_PIN_GROUP(msiof2_txd_c),
4284 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4285 SH_PFC_PIN_GROUP(msiof2_clk_d),
4286 SH_PFC_PIN_GROUP(msiof2_sync_d),
4287 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4288 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4289 SH_PFC_PIN_GROUP(msiof2_txd_d),
4290 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4291 SH_PFC_PIN_GROUP(msiof3_clk_a),
4292 SH_PFC_PIN_GROUP(msiof3_sync_a),
4293 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4294 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4295 SH_PFC_PIN_GROUP(msiof3_txd_a),
4296 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4297 SH_PFC_PIN_GROUP(msiof3_clk_b),
4298 SH_PFC_PIN_GROUP(msiof3_sync_b),
4299 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4300 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4301 SH_PFC_PIN_GROUP(msiof3_txd_b),
4302 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4303 SH_PFC_PIN_GROUP(msiof3_clk_c),
4304 SH_PFC_PIN_GROUP(msiof3_sync_c),
4305 SH_PFC_PIN_GROUP(msiof3_txd_c),
4306 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4307 SH_PFC_PIN_GROUP(msiof3_clk_d),
4308 SH_PFC_PIN_GROUP(msiof3_sync_d),
4309 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4310 SH_PFC_PIN_GROUP(msiof3_txd_d),
4311 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4312 SH_PFC_PIN_GROUP(msiof3_clk_e),
4313 SH_PFC_PIN_GROUP(msiof3_sync_e),
4314 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4315 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4316 SH_PFC_PIN_GROUP(msiof3_txd_e),
4317 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4318 SH_PFC_PIN_GROUP(pwm0),
4319 SH_PFC_PIN_GROUP(pwm1_a),
4320 SH_PFC_PIN_GROUP(pwm1_b),
4321 SH_PFC_PIN_GROUP(pwm2_a),
4322 SH_PFC_PIN_GROUP(pwm2_b),
4323 SH_PFC_PIN_GROUP(pwm3_a),
4324 SH_PFC_PIN_GROUP(pwm3_b),
4325 SH_PFC_PIN_GROUP(pwm4_a),
4326 SH_PFC_PIN_GROUP(pwm4_b),
4327 SH_PFC_PIN_GROUP(pwm5_a),
4328 SH_PFC_PIN_GROUP(pwm5_b),
4329 SH_PFC_PIN_GROUP(pwm6_a),
4330 SH_PFC_PIN_GROUP(pwm6_b),
4331 SH_PFC_PIN_GROUP(scif0_data),
4332 SH_PFC_PIN_GROUP(scif0_clk),
4333 SH_PFC_PIN_GROUP(scif0_ctrl),
4334 SH_PFC_PIN_GROUP(scif1_data_a),
4335 SH_PFC_PIN_GROUP(scif1_clk),
4336 SH_PFC_PIN_GROUP(scif1_ctrl),
4337 SH_PFC_PIN_GROUP(scif1_data_b),
4338 SH_PFC_PIN_GROUP(scif2_data_a),
4339 SH_PFC_PIN_GROUP(scif2_clk),
4340 SH_PFC_PIN_GROUP(scif2_data_b),
4341 SH_PFC_PIN_GROUP(scif3_data_a),
4342 SH_PFC_PIN_GROUP(scif3_clk),
4343 SH_PFC_PIN_GROUP(scif3_ctrl),
4344 SH_PFC_PIN_GROUP(scif3_data_b),
4345 SH_PFC_PIN_GROUP(scif4_data_a),
4346 SH_PFC_PIN_GROUP(scif4_clk_a),
4347 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4348 SH_PFC_PIN_GROUP(scif4_data_b),
4349 SH_PFC_PIN_GROUP(scif4_clk_b),
4350 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4351 SH_PFC_PIN_GROUP(scif4_data_c),
4352 SH_PFC_PIN_GROUP(scif4_clk_c),
4353 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4354 SH_PFC_PIN_GROUP(scif5_data_a),
4355 SH_PFC_PIN_GROUP(scif5_clk_a),
4356 SH_PFC_PIN_GROUP(scif5_data_b),
4357 SH_PFC_PIN_GROUP(scif5_clk_b),
4358 SH_PFC_PIN_GROUP(scif_clk_a),
4359 SH_PFC_PIN_GROUP(scif_clk_b),
4360 SH_PFC_PIN_GROUP(sdhi0_data1),
4361 SH_PFC_PIN_GROUP(sdhi0_data4),
4362 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4363 SH_PFC_PIN_GROUP(sdhi0_cd),
4364 SH_PFC_PIN_GROUP(sdhi0_wp),
4365 SH_PFC_PIN_GROUP(sdhi1_data1),
4366 SH_PFC_PIN_GROUP(sdhi1_data4),
4367 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4368 SH_PFC_PIN_GROUP(sdhi1_cd),
4369 SH_PFC_PIN_GROUP(sdhi1_wp),
4370 SH_PFC_PIN_GROUP(sdhi2_data1),
4371 SH_PFC_PIN_GROUP(sdhi2_data4),
4372 SH_PFC_PIN_GROUP(sdhi2_data8),
4373 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4374 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4375 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4376 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4377 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4378 SH_PFC_PIN_GROUP(sdhi2_ds),
4379 SH_PFC_PIN_GROUP(sdhi3_data1),
4380 SH_PFC_PIN_GROUP(sdhi3_data4),
4381 SH_PFC_PIN_GROUP(sdhi3_data8),
4382 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4383 SH_PFC_PIN_GROUP(sdhi3_cd),
4384 SH_PFC_PIN_GROUP(sdhi3_wp),
4385 SH_PFC_PIN_GROUP(sdhi3_ds),
4386 SH_PFC_PIN_GROUP(ssi0_data),
4387 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4388 SH_PFC_PIN_GROUP(ssi1_data_a),
4389 SH_PFC_PIN_GROUP(ssi1_data_b),
4390 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4391 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4392 SH_PFC_PIN_GROUP(ssi2_data_a),
4393 SH_PFC_PIN_GROUP(ssi2_data_b),
4394 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4395 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4396 SH_PFC_PIN_GROUP(ssi3_data),
4397 SH_PFC_PIN_GROUP(ssi349_ctrl),
4398 SH_PFC_PIN_GROUP(ssi4_data),
4399 SH_PFC_PIN_GROUP(ssi4_ctrl),
4400 SH_PFC_PIN_GROUP(ssi5_data),
4401 SH_PFC_PIN_GROUP(ssi5_ctrl),
4402 SH_PFC_PIN_GROUP(ssi6_data),
4403 SH_PFC_PIN_GROUP(ssi6_ctrl),
4404 SH_PFC_PIN_GROUP(ssi7_data),
4405 SH_PFC_PIN_GROUP(ssi78_ctrl),
4406 SH_PFC_PIN_GROUP(ssi8_data),
4407 SH_PFC_PIN_GROUP(ssi9_data_a),
4408 SH_PFC_PIN_GROUP(ssi9_data_b),
4409 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4410 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4411 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4412 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4413 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4414 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4415 SH_PFC_PIN_GROUP(usb0),
4416 SH_PFC_PIN_GROUP(usb1),
4417 SH_PFC_PIN_GROUP(usb30),
4418 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4419 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4420 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4421 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4422 SH_PFC_PIN_GROUP(vin4_data18_a),
4423 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4424 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4425 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4426 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4427 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4428 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4429 SH_PFC_PIN_GROUP(vin4_data18_b),
4430 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4431 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4432 SH_PFC_PIN_GROUP(vin4_sync),
4433 SH_PFC_PIN_GROUP(vin4_field),
4434 SH_PFC_PIN_GROUP(vin4_clkenb),
4435 SH_PFC_PIN_GROUP(vin4_clk),
4436 VIN_DATA_PIN_GROUP(vin5_data, 8),
4437 VIN_DATA_PIN_GROUP(vin5_data, 10),
4438 VIN_DATA_PIN_GROUP(vin5_data, 12),
4439 VIN_DATA_PIN_GROUP(vin5_data, 16),
4440 SH_PFC_PIN_GROUP(vin5_sync),
4441 SH_PFC_PIN_GROUP(vin5_field),
4442 SH_PFC_PIN_GROUP(vin5_clkenb),
4443 SH_PFC_PIN_GROUP(vin5_clk),
4444 },
4445 .automotive = {
4446 SH_PFC_PIN_GROUP(canfd0_data_a),
4447 SH_PFC_PIN_GROUP(canfd0_data_b),
4448 SH_PFC_PIN_GROUP(canfd1_data),
4449 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4450 SH_PFC_PIN_GROUP(drif0_data0_a),
4451 SH_PFC_PIN_GROUP(drif0_data1_a),
4452 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4453 SH_PFC_PIN_GROUP(drif0_data0_b),
4454 SH_PFC_PIN_GROUP(drif0_data1_b),
4455 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4456 SH_PFC_PIN_GROUP(drif0_data0_c),
4457 SH_PFC_PIN_GROUP(drif0_data1_c),
4458 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4459 SH_PFC_PIN_GROUP(drif1_data0_a),
4460 SH_PFC_PIN_GROUP(drif1_data1_a),
4461 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4462 SH_PFC_PIN_GROUP(drif1_data0_b),
4463 SH_PFC_PIN_GROUP(drif1_data1_b),
4464 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4465 SH_PFC_PIN_GROUP(drif1_data0_c),
4466 SH_PFC_PIN_GROUP(drif1_data1_c),
4467 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4468 SH_PFC_PIN_GROUP(drif2_data0_a),
4469 SH_PFC_PIN_GROUP(drif2_data1_a),
4470 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4471 SH_PFC_PIN_GROUP(drif2_data0_b),
4472 SH_PFC_PIN_GROUP(drif2_data1_b),
4473 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4474 SH_PFC_PIN_GROUP(drif3_data0_a),
4475 SH_PFC_PIN_GROUP(drif3_data1_a),
4476 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4477 SH_PFC_PIN_GROUP(drif3_data0_b),
4478 SH_PFC_PIN_GROUP(drif3_data1_b),
4479 }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4480};
4481
4482static const char * const audio_clk_groups[] = {
4483 "audio_clk_a_a",
4484 "audio_clk_a_b",
4485 "audio_clk_a_c",
4486 "audio_clk_b_a",
4487 "audio_clk_b_b",
4488 "audio_clk_c_a",
4489 "audio_clk_c_b",
4490 "audio_clkout_a",
4491 "audio_clkout_b",
4492 "audio_clkout_c",
4493 "audio_clkout_d",
4494 "audio_clkout1_a",
4495 "audio_clkout1_b",
4496 "audio_clkout2_a",
4497 "audio_clkout2_b",
4498 "audio_clkout3_a",
4499 "audio_clkout3_b",
4500};
4501
4502static const char * const avb_groups[] = {
4503 "avb_link",
4504 "avb_magic",
4505 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4506 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4507 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4508 "avb_mii",
4509 "avb_avtp_pps",
4510 "avb_avtp_match_a",
4511 "avb_avtp_capture_a",
4512 "avb_avtp_match_b",
4513 "avb_avtp_capture_b",
4514};
4515
4516static const char * const can0_groups[] = {
4517 "can0_data_a",
4518 "can0_data_b",
4519};
4520
4521static const char * const can1_groups[] = {
4522 "can1_data",
4523};
4524
4525static const char * const can_clk_groups[] = {
4526 "can_clk",
4527};
4528
4529static const char * const canfd0_groups[] = {
4530 "canfd0_data_a",
4531 "canfd0_data_b",
4532};
4533
4534static const char * const canfd1_groups[] = {
4535 "canfd1_data",
4536};
4537
4538static const char * const drif0_groups[] = {
4539 "drif0_ctrl_a",
4540 "drif0_data0_a",
4541 "drif0_data1_a",
4542 "drif0_ctrl_b",
4543 "drif0_data0_b",
4544 "drif0_data1_b",
4545 "drif0_ctrl_c",
4546 "drif0_data0_c",
4547 "drif0_data1_c",
4548};
4549
4550static const char * const drif1_groups[] = {
4551 "drif1_ctrl_a",
4552 "drif1_data0_a",
4553 "drif1_data1_a",
4554 "drif1_ctrl_b",
4555 "drif1_data0_b",
4556 "drif1_data1_b",
4557 "drif1_ctrl_c",
4558 "drif1_data0_c",
4559 "drif1_data1_c",
4560};
4561
4562static const char * const drif2_groups[] = {
4563 "drif2_ctrl_a",
4564 "drif2_data0_a",
4565 "drif2_data1_a",
4566 "drif2_ctrl_b",
4567 "drif2_data0_b",
4568 "drif2_data1_b",
4569};
4570
4571static const char * const drif3_groups[] = {
4572 "drif3_ctrl_a",
4573 "drif3_data0_a",
4574 "drif3_data1_a",
4575 "drif3_ctrl_b",
4576 "drif3_data0_b",
4577 "drif3_data1_b",
4578};
4579
4580static const char * const du_groups[] = {
4581 "du_rgb666",
4582 "du_rgb888",
4583 "du_clk_out_0",
4584 "du_clk_out_1",
4585 "du_sync",
4586 "du_oddf",
4587 "du_cde",
4588 "du_disp",
4589};
4590
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4591static const char * const hdmi0_groups[] = {
4592 "hdmi0_cec",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4593};
4594
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4595static const char * const hscif0_groups[] = {
4596 "hscif0_data",
4597 "hscif0_clk",
4598 "hscif0_ctrl",
4599};
4600
4601static const char * const hscif1_groups[] = {
4602 "hscif1_data_a",
4603 "hscif1_clk_a",
4604 "hscif1_ctrl_a",
4605 "hscif1_data_b",
4606 "hscif1_clk_b",
4607 "hscif1_ctrl_b",
4608};
4609
4610static const char * const hscif2_groups[] = {
4611 "hscif2_data_a",
4612 "hscif2_clk_a",
4613 "hscif2_ctrl_a",
4614 "hscif2_data_b",
4615 "hscif2_clk_b",
4616 "hscif2_ctrl_b",
4617 "hscif2_data_c",
4618 "hscif2_clk_c",
4619 "hscif2_ctrl_c",
4620};
4621
4622static const char * const hscif3_groups[] = {
4623 "hscif3_data_a",
4624 "hscif3_clk",
4625 "hscif3_ctrl",
4626 "hscif3_data_b",
4627 "hscif3_data_c",
4628 "hscif3_data_d",
4629};
4630
4631static const char * const hscif4_groups[] = {
4632 "hscif4_data_a",
4633 "hscif4_clk",
4634 "hscif4_ctrl",
4635 "hscif4_data_b",
4636};
4637
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4638static const char * const i2c0_groups[] = {
4639 "i2c0",
4640};
4641
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4642static const char * const i2c1_groups[] = {
4643 "i2c1_a",
4644 "i2c1_b",
4645};
4646
4647static const char * const i2c2_groups[] = {
4648 "i2c2_a",
4649 "i2c2_b",
4650};
4651
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4652static const char * const i2c3_groups[] = {
4653 "i2c3",
4654};
4655
4656static const char * const i2c5_groups[] = {
4657 "i2c5",
4658};
4659
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4660static const char * const i2c6_groups[] = {
4661 "i2c6_a",
4662 "i2c6_b",
4663 "i2c6_c",
4664};
4665
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4666static const char * const intc_ex_groups[] = {
4667 "intc_ex_irq0",
4668 "intc_ex_irq1",
4669 "intc_ex_irq2",
4670 "intc_ex_irq3",
4671 "intc_ex_irq4",
4672 "intc_ex_irq5",
4673};
4674
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4675static const char * const msiof0_groups[] = {
4676 "msiof0_clk",
4677 "msiof0_sync",
4678 "msiof0_ss1",
4679 "msiof0_ss2",
4680 "msiof0_txd",
4681 "msiof0_rxd",
4682};
4683
4684static const char * const msiof1_groups[] = {
4685 "msiof1_clk_a",
4686 "msiof1_sync_a",
4687 "msiof1_ss1_a",
4688 "msiof1_ss2_a",
4689 "msiof1_txd_a",
4690 "msiof1_rxd_a",
4691 "msiof1_clk_b",
4692 "msiof1_sync_b",
4693 "msiof1_ss1_b",
4694 "msiof1_ss2_b",
4695 "msiof1_txd_b",
4696 "msiof1_rxd_b",
4697 "msiof1_clk_c",
4698 "msiof1_sync_c",
4699 "msiof1_ss1_c",
4700 "msiof1_ss2_c",
4701 "msiof1_txd_c",
4702 "msiof1_rxd_c",
4703 "msiof1_clk_d",
4704 "msiof1_sync_d",
4705 "msiof1_ss1_d",
4706 "msiof1_ss2_d",
4707 "msiof1_txd_d",
4708 "msiof1_rxd_d",
4709 "msiof1_clk_e",
4710 "msiof1_sync_e",
4711 "msiof1_ss1_e",
4712 "msiof1_ss2_e",
4713 "msiof1_txd_e",
4714 "msiof1_rxd_e",
4715 "msiof1_clk_f",
4716 "msiof1_sync_f",
4717 "msiof1_ss1_f",
4718 "msiof1_ss2_f",
4719 "msiof1_txd_f",
4720 "msiof1_rxd_f",
4721 "msiof1_clk_g",
4722 "msiof1_sync_g",
4723 "msiof1_ss1_g",
4724 "msiof1_ss2_g",
4725 "msiof1_txd_g",
4726 "msiof1_rxd_g",
4727};
4728
4729static const char * const msiof2_groups[] = {
4730 "msiof2_clk_a",
4731 "msiof2_sync_a",
4732 "msiof2_ss1_a",
4733 "msiof2_ss2_a",
4734 "msiof2_txd_a",
4735 "msiof2_rxd_a",
4736 "msiof2_clk_b",
4737 "msiof2_sync_b",
4738 "msiof2_ss1_b",
4739 "msiof2_ss2_b",
4740 "msiof2_txd_b",
4741 "msiof2_rxd_b",
4742 "msiof2_clk_c",
4743 "msiof2_sync_c",
4744 "msiof2_ss1_c",
4745 "msiof2_ss2_c",
4746 "msiof2_txd_c",
4747 "msiof2_rxd_c",
4748 "msiof2_clk_d",
4749 "msiof2_sync_d",
4750 "msiof2_ss1_d",
4751 "msiof2_ss2_d",
4752 "msiof2_txd_d",
4753 "msiof2_rxd_d",
4754};
4755
4756static const char * const msiof3_groups[] = {
4757 "msiof3_clk_a",
4758 "msiof3_sync_a",
4759 "msiof3_ss1_a",
4760 "msiof3_ss2_a",
4761 "msiof3_txd_a",
4762 "msiof3_rxd_a",
4763 "msiof3_clk_b",
4764 "msiof3_sync_b",
4765 "msiof3_ss1_b",
4766 "msiof3_ss2_b",
4767 "msiof3_txd_b",
4768 "msiof3_rxd_b",
4769 "msiof3_clk_c",
4770 "msiof3_sync_c",
4771 "msiof3_txd_c",
4772 "msiof3_rxd_c",
4773 "msiof3_clk_d",
4774 "msiof3_sync_d",
4775 "msiof3_ss1_d",
4776 "msiof3_txd_d",
4777 "msiof3_rxd_d",
4778 "msiof3_clk_e",
4779 "msiof3_sync_e",
4780 "msiof3_ss1_e",
4781 "msiof3_ss2_e",
4782 "msiof3_txd_e",
4783 "msiof3_rxd_e",
4784};
4785
4786static const char * const pwm0_groups[] = {
4787 "pwm0",
4788};
4789
4790static const char * const pwm1_groups[] = {
4791 "pwm1_a",
4792 "pwm1_b",
4793};
4794
4795static const char * const pwm2_groups[] = {
4796 "pwm2_a",
4797 "pwm2_b",
4798};
4799
4800static const char * const pwm3_groups[] = {
4801 "pwm3_a",
4802 "pwm3_b",
4803};
4804
4805static const char * const pwm4_groups[] = {
4806 "pwm4_a",
4807 "pwm4_b",
4808};
4809
4810static const char * const pwm5_groups[] = {
4811 "pwm5_a",
4812 "pwm5_b",
4813};
4814
4815static const char * const pwm6_groups[] = {
4816 "pwm6_a",
4817 "pwm6_b",
4818};
4819
4820static const char * const scif0_groups[] = {
4821 "scif0_data",
4822 "scif0_clk",
4823 "scif0_ctrl",
4824};
4825
4826static const char * const scif1_groups[] = {
4827 "scif1_data_a",
4828 "scif1_clk",
4829 "scif1_ctrl",
4830 "scif1_data_b",
4831};
4832
4833static const char * const scif2_groups[] = {
4834 "scif2_data_a",
4835 "scif2_clk",
4836 "scif2_data_b",
4837};
4838
4839static const char * const scif3_groups[] = {
4840 "scif3_data_a",
4841 "scif3_clk",
4842 "scif3_ctrl",
4843 "scif3_data_b",
4844};
4845
4846static const char * const scif4_groups[] = {
4847 "scif4_data_a",
4848 "scif4_clk_a",
4849 "scif4_ctrl_a",
4850 "scif4_data_b",
4851 "scif4_clk_b",
4852 "scif4_ctrl_b",
4853 "scif4_data_c",
4854 "scif4_clk_c",
4855 "scif4_ctrl_c",
4856};
4857
4858static const char * const scif5_groups[] = {
4859 "scif5_data_a",
4860 "scif5_clk_a",
4861 "scif5_data_b",
4862 "scif5_clk_b",
4863};
4864
4865static const char * const scif_clk_groups[] = {
4866 "scif_clk_a",
4867 "scif_clk_b",
4868};
4869
4870static const char * const sdhi0_groups[] = {
4871 "sdhi0_data1",
4872 "sdhi0_data4",
4873 "sdhi0_ctrl",
4874 "sdhi0_cd",
4875 "sdhi0_wp",
4876};
4877
4878static const char * const sdhi1_groups[] = {
4879 "sdhi1_data1",
4880 "sdhi1_data4",
4881 "sdhi1_ctrl",
4882 "sdhi1_cd",
4883 "sdhi1_wp",
4884};
4885
4886static const char * const sdhi2_groups[] = {
4887 "sdhi2_data1",
4888 "sdhi2_data4",
4889 "sdhi2_data8",
4890 "sdhi2_ctrl",
4891 "sdhi2_cd_a",
4892 "sdhi2_wp_a",
4893 "sdhi2_cd_b",
4894 "sdhi2_wp_b",
4895 "sdhi2_ds",
4896};
4897
4898static const char * const sdhi3_groups[] = {
4899 "sdhi3_data1",
4900 "sdhi3_data4",
4901 "sdhi3_data8",
4902 "sdhi3_ctrl",
4903 "sdhi3_cd",
4904 "sdhi3_wp",
4905 "sdhi3_ds",
4906};
4907
4908static const char * const ssi_groups[] = {
4909 "ssi0_data",
4910 "ssi01239_ctrl",
4911 "ssi1_data_a",
4912 "ssi1_data_b",
4913 "ssi1_ctrl_a",
4914 "ssi1_ctrl_b",
4915 "ssi2_data_a",
4916 "ssi2_data_b",
4917 "ssi2_ctrl_a",
4918 "ssi2_ctrl_b",
4919 "ssi3_data",
4920 "ssi349_ctrl",
4921 "ssi4_data",
4922 "ssi4_ctrl",
4923 "ssi5_data",
4924 "ssi5_ctrl",
4925 "ssi6_data",
4926 "ssi6_ctrl",
4927 "ssi7_data",
4928 "ssi78_ctrl",
4929 "ssi8_data",
4930 "ssi9_data_a",
4931 "ssi9_data_b",
4932 "ssi9_ctrl_a",
4933 "ssi9_ctrl_b",
4934};
4935
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4936static const char * const tmu_groups[] = {
4937 "tmu_tclk1_a",
4938 "tmu_tclk1_b",
4939 "tmu_tclk2_a",
4940 "tmu_tclk2_b",
4941};
4942
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4943static const char * const usb0_groups[] = {
4944 "usb0",
4945};
4946
4947static const char * const usb1_groups[] = {
4948 "usb1",
4949};
4950
4951static const char * const usb30_groups[] = {
4952 "usb30",
4953};
4954
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4955static const char * const vin4_groups[] = {
4956 "vin4_data8_a",
4957 "vin4_data10_a",
4958 "vin4_data12_a",
4959 "vin4_data16_a",
4960 "vin4_data18_a",
4961 "vin4_data20_a",
4962 "vin4_data24_a",
4963 "vin4_data8_b",
4964 "vin4_data10_b",
4965 "vin4_data12_b",
4966 "vin4_data16_b",
4967 "vin4_data18_b",
4968 "vin4_data20_b",
4969 "vin4_data24_b",
4970 "vin4_sync",
4971 "vin4_field",
4972 "vin4_clkenb",
4973 "vin4_clk",
4974};
4975
4976static const char * const vin5_groups[] = {
4977 "vin5_data8",
4978 "vin5_data10",
4979 "vin5_data12",
4980 "vin5_data16",
4981 "vin5_sync",
4982 "vin5_field",
4983 "vin5_clkenb",
4984 "vin5_clk",
4985};
4986
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4987static const struct {
4988 struct sh_pfc_function common[48];
4989 struct sh_pfc_function automotive[6];
4990} pinmux_functions = {
4991 .common = {
4992 SH_PFC_FUNCTION(audio_clk),
4993 SH_PFC_FUNCTION(avb),
4994 SH_PFC_FUNCTION(can0),
4995 SH_PFC_FUNCTION(can1),
4996 SH_PFC_FUNCTION(can_clk),
4997 SH_PFC_FUNCTION(du),
4998 SH_PFC_FUNCTION(hdmi0),
4999 SH_PFC_FUNCTION(hscif0),
5000 SH_PFC_FUNCTION(hscif1),
5001 SH_PFC_FUNCTION(hscif2),
5002 SH_PFC_FUNCTION(hscif3),
5003 SH_PFC_FUNCTION(hscif4),
5004 SH_PFC_FUNCTION(i2c0),
5005 SH_PFC_FUNCTION(i2c1),
5006 SH_PFC_FUNCTION(i2c2),
5007 SH_PFC_FUNCTION(i2c3),
5008 SH_PFC_FUNCTION(i2c5),
5009 SH_PFC_FUNCTION(i2c6),
5010 SH_PFC_FUNCTION(intc_ex),
5011 SH_PFC_FUNCTION(msiof0),
5012 SH_PFC_FUNCTION(msiof1),
5013 SH_PFC_FUNCTION(msiof2),
5014 SH_PFC_FUNCTION(msiof3),
5015 SH_PFC_FUNCTION(pwm0),
5016 SH_PFC_FUNCTION(pwm1),
5017 SH_PFC_FUNCTION(pwm2),
5018 SH_PFC_FUNCTION(pwm3),
5019 SH_PFC_FUNCTION(pwm4),
5020 SH_PFC_FUNCTION(pwm5),
5021 SH_PFC_FUNCTION(pwm6),
5022 SH_PFC_FUNCTION(scif0),
5023 SH_PFC_FUNCTION(scif1),
5024 SH_PFC_FUNCTION(scif2),
5025 SH_PFC_FUNCTION(scif3),
5026 SH_PFC_FUNCTION(scif4),
5027 SH_PFC_FUNCTION(scif5),
5028 SH_PFC_FUNCTION(scif_clk),
5029 SH_PFC_FUNCTION(sdhi0),
5030 SH_PFC_FUNCTION(sdhi1),
5031 SH_PFC_FUNCTION(sdhi2),
5032 SH_PFC_FUNCTION(sdhi3),
5033 SH_PFC_FUNCTION(ssi),
5034 SH_PFC_FUNCTION(tmu),
5035 SH_PFC_FUNCTION(usb0),
5036 SH_PFC_FUNCTION(usb1),
5037 SH_PFC_FUNCTION(usb30),
5038 SH_PFC_FUNCTION(vin4),
5039 SH_PFC_FUNCTION(vin5),
5040 },
5041 .automotive = {
5042 SH_PFC_FUNCTION(canfd0),
5043 SH_PFC_FUNCTION(canfd1),
5044 SH_PFC_FUNCTION(drif0),
5045 SH_PFC_FUNCTION(drif1),
5046 SH_PFC_FUNCTION(drif2),
5047 SH_PFC_FUNCTION(drif3),
5048 }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5049};
5050
5051static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5052#define F_(x, y) FN_##y
5053#define FM(x) FN_##x
5054 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5055 0, 0,
5056 0, 0,
5057 0, 0,
5058 0, 0,
5059 0, 0,
5060 0, 0,
5061 0, 0,
5062 0, 0,
5063 0, 0,
5064 0, 0,
5065 0, 0,
5066 0, 0,
5067 0, 0,
5068 0, 0,
5069 0, 0,
5070 0, 0,
5071 GP_0_15_FN, GPSR0_15,
5072 GP_0_14_FN, GPSR0_14,
5073 GP_0_13_FN, GPSR0_13,
5074 GP_0_12_FN, GPSR0_12,
5075 GP_0_11_FN, GPSR0_11,
5076 GP_0_10_FN, GPSR0_10,
5077 GP_0_9_FN, GPSR0_9,
5078 GP_0_8_FN, GPSR0_8,
5079 GP_0_7_FN, GPSR0_7,
5080 GP_0_6_FN, GPSR0_6,
5081 GP_0_5_FN, GPSR0_5,
5082 GP_0_4_FN, GPSR0_4,
5083 GP_0_3_FN, GPSR0_3,
5084 GP_0_2_FN, GPSR0_2,
5085 GP_0_1_FN, GPSR0_1,
5086 GP_0_0_FN, GPSR0_0, }
5087 },
5088 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5089 0, 0,
5090 0, 0,
5091 0, 0,
5092 GP_1_28_FN, GPSR1_28,
5093 GP_1_27_FN, GPSR1_27,
5094 GP_1_26_FN, GPSR1_26,
5095 GP_1_25_FN, GPSR1_25,
5096 GP_1_24_FN, GPSR1_24,
5097 GP_1_23_FN, GPSR1_23,
5098 GP_1_22_FN, GPSR1_22,
5099 GP_1_21_FN, GPSR1_21,
5100 GP_1_20_FN, GPSR1_20,
5101 GP_1_19_FN, GPSR1_19,
5102 GP_1_18_FN, GPSR1_18,
5103 GP_1_17_FN, GPSR1_17,
5104 GP_1_16_FN, GPSR1_16,
5105 GP_1_15_FN, GPSR1_15,
5106 GP_1_14_FN, GPSR1_14,
5107 GP_1_13_FN, GPSR1_13,
5108 GP_1_12_FN, GPSR1_12,
5109 GP_1_11_FN, GPSR1_11,
5110 GP_1_10_FN, GPSR1_10,
5111 GP_1_9_FN, GPSR1_9,
5112 GP_1_8_FN, GPSR1_8,
5113 GP_1_7_FN, GPSR1_7,
5114 GP_1_6_FN, GPSR1_6,
5115 GP_1_5_FN, GPSR1_5,
5116 GP_1_4_FN, GPSR1_4,
5117 GP_1_3_FN, GPSR1_3,
5118 GP_1_2_FN, GPSR1_2,
5119 GP_1_1_FN, GPSR1_1,
5120 GP_1_0_FN, GPSR1_0, }
5121 },
5122 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5123 0, 0,
5124 0, 0,
5125 0, 0,
5126 0, 0,
5127 0, 0,
5128 0, 0,
5129 0, 0,
5130 0, 0,
5131 0, 0,
5132 0, 0,
5133 0, 0,
5134 0, 0,
5135 0, 0,
5136 0, 0,
5137 0, 0,
5138 0, 0,
5139 0, 0,
5140 GP_2_14_FN, GPSR2_14,
5141 GP_2_13_FN, GPSR2_13,
5142 GP_2_12_FN, GPSR2_12,
5143 GP_2_11_FN, GPSR2_11,
5144 GP_2_10_FN, GPSR2_10,
5145 GP_2_9_FN, GPSR2_9,
5146 GP_2_8_FN, GPSR2_8,
5147 GP_2_7_FN, GPSR2_7,
5148 GP_2_6_FN, GPSR2_6,
5149 GP_2_5_FN, GPSR2_5,
5150 GP_2_4_FN, GPSR2_4,
5151 GP_2_3_FN, GPSR2_3,
5152 GP_2_2_FN, GPSR2_2,
5153 GP_2_1_FN, GPSR2_1,
5154 GP_2_0_FN, GPSR2_0, }
5155 },
5156 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5157 0, 0,
5158 0, 0,
5159 0, 0,
5160 0, 0,
5161 0, 0,
5162 0, 0,
5163 0, 0,
5164 0, 0,
5165 0, 0,
5166 0, 0,
5167 0, 0,
5168 0, 0,
5169 0, 0,
5170 0, 0,
5171 0, 0,
5172 0, 0,
5173 GP_3_15_FN, GPSR3_15,
5174 GP_3_14_FN, GPSR3_14,
5175 GP_3_13_FN, GPSR3_13,
5176 GP_3_12_FN, GPSR3_12,
5177 GP_3_11_FN, GPSR3_11,
5178 GP_3_10_FN, GPSR3_10,
5179 GP_3_9_FN, GPSR3_9,
5180 GP_3_8_FN, GPSR3_8,
5181 GP_3_7_FN, GPSR3_7,
5182 GP_3_6_FN, GPSR3_6,
5183 GP_3_5_FN, GPSR3_5,
5184 GP_3_4_FN, GPSR3_4,
5185 GP_3_3_FN, GPSR3_3,
5186 GP_3_2_FN, GPSR3_2,
5187 GP_3_1_FN, GPSR3_1,
5188 GP_3_0_FN, GPSR3_0, }
5189 },
5190 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5191 0, 0,
5192 0, 0,
5193 0, 0,
5194 0, 0,
5195 0, 0,
5196 0, 0,
5197 0, 0,
5198 0, 0,
5199 0, 0,
5200 0, 0,
5201 0, 0,
5202 0, 0,
5203 0, 0,
5204 0, 0,
5205 GP_4_17_FN, GPSR4_17,
5206 GP_4_16_FN, GPSR4_16,
5207 GP_4_15_FN, GPSR4_15,
5208 GP_4_14_FN, GPSR4_14,
5209 GP_4_13_FN, GPSR4_13,
5210 GP_4_12_FN, GPSR4_12,
5211 GP_4_11_FN, GPSR4_11,
5212 GP_4_10_FN, GPSR4_10,
5213 GP_4_9_FN, GPSR4_9,
5214 GP_4_8_FN, GPSR4_8,
5215 GP_4_7_FN, GPSR4_7,
5216 GP_4_6_FN, GPSR4_6,
5217 GP_4_5_FN, GPSR4_5,
5218 GP_4_4_FN, GPSR4_4,
5219 GP_4_3_FN, GPSR4_3,
5220 GP_4_2_FN, GPSR4_2,
5221 GP_4_1_FN, GPSR4_1,
5222 GP_4_0_FN, GPSR4_0, }
5223 },
5224 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5225 0, 0,
5226 0, 0,
5227 0, 0,
5228 0, 0,
5229 0, 0,
5230 0, 0,
5231 GP_5_25_FN, GPSR5_25,
5232 GP_5_24_FN, GPSR5_24,
5233 GP_5_23_FN, GPSR5_23,
5234 GP_5_22_FN, GPSR5_22,
5235 GP_5_21_FN, GPSR5_21,
5236 GP_5_20_FN, GPSR5_20,
5237 GP_5_19_FN, GPSR5_19,
5238 GP_5_18_FN, GPSR5_18,
5239 GP_5_17_FN, GPSR5_17,
5240 GP_5_16_FN, GPSR5_16,
5241 GP_5_15_FN, GPSR5_15,
5242 GP_5_14_FN, GPSR5_14,
5243 GP_5_13_FN, GPSR5_13,
5244 GP_5_12_FN, GPSR5_12,
5245 GP_5_11_FN, GPSR5_11,
5246 GP_5_10_FN, GPSR5_10,
5247 GP_5_9_FN, GPSR5_9,
5248 GP_5_8_FN, GPSR5_8,
5249 GP_5_7_FN, GPSR5_7,
5250 GP_5_6_FN, GPSR5_6,
5251 GP_5_5_FN, GPSR5_5,
5252 GP_5_4_FN, GPSR5_4,
5253 GP_5_3_FN, GPSR5_3,
5254 GP_5_2_FN, GPSR5_2,
5255 GP_5_1_FN, GPSR5_1,
5256 GP_5_0_FN, GPSR5_0, }
5257 },
5258 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5259 GP_6_31_FN, GPSR6_31,
5260 GP_6_30_FN, GPSR6_30,
5261 GP_6_29_FN, GPSR6_29,
5262 GP_6_28_FN, GPSR6_28,
5263 GP_6_27_FN, GPSR6_27,
5264 GP_6_26_FN, GPSR6_26,
5265 GP_6_25_FN, GPSR6_25,
5266 GP_6_24_FN, GPSR6_24,
5267 GP_6_23_FN, GPSR6_23,
5268 GP_6_22_FN, GPSR6_22,
5269 GP_6_21_FN, GPSR6_21,
5270 GP_6_20_FN, GPSR6_20,
5271 GP_6_19_FN, GPSR6_19,
5272 GP_6_18_FN, GPSR6_18,
5273 GP_6_17_FN, GPSR6_17,
5274 GP_6_16_FN, GPSR6_16,
5275 GP_6_15_FN, GPSR6_15,
5276 GP_6_14_FN, GPSR6_14,
5277 GP_6_13_FN, GPSR6_13,
5278 GP_6_12_FN, GPSR6_12,
5279 GP_6_11_FN, GPSR6_11,
5280 GP_6_10_FN, GPSR6_10,
5281 GP_6_9_FN, GPSR6_9,
5282 GP_6_8_FN, GPSR6_8,
5283 GP_6_7_FN, GPSR6_7,
5284 GP_6_6_FN, GPSR6_6,
5285 GP_6_5_FN, GPSR6_5,
5286 GP_6_4_FN, GPSR6_4,
5287 GP_6_3_FN, GPSR6_3,
5288 GP_6_2_FN, GPSR6_2,
5289 GP_6_1_FN, GPSR6_1,
5290 GP_6_0_FN, GPSR6_0, }
5291 },
5292 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5293 0, 0,
5294 0, 0,
5295 0, 0,
5296 0, 0,
5297 0, 0,
5298 0, 0,
5299 0, 0,
5300 0, 0,
5301 0, 0,
5302 0, 0,
5303 0, 0,
5304 0, 0,
5305 0, 0,
5306 0, 0,
5307 0, 0,
5308 0, 0,
5309 0, 0,
5310 0, 0,
5311 0, 0,
5312 0, 0,
5313 0, 0,
5314 0, 0,
5315 0, 0,
5316 0, 0,
5317 0, 0,
5318 0, 0,
5319 0, 0,
5320 0, 0,
5321 GP_7_3_FN, GPSR7_3,
5322 GP_7_2_FN, GPSR7_2,
5323 GP_7_1_FN, GPSR7_1,
5324 GP_7_0_FN, GPSR7_0, }
5325 },
5326#undef F_
5327#undef FM
5328
5329#define F_(x, y) x,
5330#define FM(x) FN_##x,
5331 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5332 IP0_31_28
5333 IP0_27_24
5334 IP0_23_20
5335 IP0_19_16
5336 IP0_15_12
5337 IP0_11_8
5338 IP0_7_4
5339 IP0_3_0 }
5340 },
5341 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5342 IP1_31_28
5343 IP1_27_24
5344 IP1_23_20
5345 IP1_19_16
5346 IP1_15_12
5347 IP1_11_8
5348 IP1_7_4
5349 IP1_3_0 }
5350 },
5351 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5352 IP2_31_28
5353 IP2_27_24
5354 IP2_23_20
5355 IP2_19_16
5356 IP2_15_12
5357 IP2_11_8
5358 IP2_7_4
5359 IP2_3_0 }
5360 },
5361 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5362 IP3_31_28
5363 IP3_27_24
5364 IP3_23_20
5365 IP3_19_16
5366 IP3_15_12
5367 IP3_11_8
5368 IP3_7_4
5369 IP3_3_0 }
5370 },
5371 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5372 IP4_31_28
5373 IP4_27_24
5374 IP4_23_20
5375 IP4_19_16
5376 IP4_15_12
5377 IP4_11_8
5378 IP4_7_4
5379 IP4_3_0 }
5380 },
5381 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5382 IP5_31_28
5383 IP5_27_24
5384 IP5_23_20
5385 IP5_19_16
5386 IP5_15_12
5387 IP5_11_8
5388 IP5_7_4
5389 IP5_3_0 }
5390 },
5391 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5392 IP6_31_28
5393 IP6_27_24
5394 IP6_23_20
5395 IP6_19_16
5396 IP6_15_12
5397 IP6_11_8
5398 IP6_7_4
5399 IP6_3_0 }
5400 },
5401 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5402 IP7_31_28
5403 IP7_27_24
5404 IP7_23_20
5405 IP7_19_16
5406 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5407 IP7_11_8
5408 IP7_7_4
5409 IP7_3_0 }
5410 },
5411 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5412 IP8_31_28
5413 IP8_27_24
5414 IP8_23_20
5415 IP8_19_16
5416 IP8_15_12
5417 IP8_11_8
5418 IP8_7_4
5419 IP8_3_0 }
5420 },
5421 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5422 IP9_31_28
5423 IP9_27_24
5424 IP9_23_20
5425 IP9_19_16
5426 IP9_15_12
5427 IP9_11_8
5428 IP9_7_4
5429 IP9_3_0 }
5430 },
5431 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5432 IP10_31_28
5433 IP10_27_24
5434 IP10_23_20
5435 IP10_19_16
5436 IP10_15_12
5437 IP10_11_8
5438 IP10_7_4
5439 IP10_3_0 }
5440 },
5441 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5442 IP11_31_28
5443 IP11_27_24
5444 IP11_23_20
5445 IP11_19_16
5446 IP11_15_12
5447 IP11_11_8
5448 IP11_7_4
5449 IP11_3_0 }
5450 },
5451 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5452 IP12_31_28
5453 IP12_27_24
5454 IP12_23_20
5455 IP12_19_16
5456 IP12_15_12
5457 IP12_11_8
5458 IP12_7_4
5459 IP12_3_0 }
5460 },
5461 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5462 IP13_31_28
5463 IP13_27_24
5464 IP13_23_20
5465 IP13_19_16
5466 IP13_15_12
5467 IP13_11_8
5468 IP13_7_4
5469 IP13_3_0 }
5470 },
5471 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5472 IP14_31_28
5473 IP14_27_24
5474 IP14_23_20
5475 IP14_19_16
5476 IP14_15_12
5477 IP14_11_8
5478 IP14_7_4
5479 IP14_3_0 }
5480 },
5481 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5482 IP15_31_28
5483 IP15_27_24
5484 IP15_23_20
5485 IP15_19_16
5486 IP15_15_12
5487 IP15_11_8
5488 IP15_7_4
5489 IP15_3_0 }
5490 },
5491 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5492 IP16_31_28
5493 IP16_27_24
5494 IP16_23_20
5495 IP16_19_16
5496 IP16_15_12
5497 IP16_11_8
5498 IP16_7_4
5499 IP16_3_0 }
5500 },
5501 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5502 IP17_31_28
5503 IP17_27_24
5504 IP17_23_20
5505 IP17_19_16
5506 IP17_15_12
5507 IP17_11_8
5508 IP17_7_4
5509 IP17_3_0 }
5510 },
5511 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5512 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5513 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5514 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5515 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5516 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5517 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5518 IP18_7_4
5519 IP18_3_0 }
5520 },
5521#undef F_
5522#undef FM
5523
5524#define F_(x, y) x,
5525#define FM(x) FN_##x,
5526 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5527 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5528 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5529 MOD_SEL0_31_30_29
5530 MOD_SEL0_28_27
5531 MOD_SEL0_26_25_24
5532 MOD_SEL0_23
5533 MOD_SEL0_22
5534 MOD_SEL0_21
5535 MOD_SEL0_20
5536 MOD_SEL0_19
5537 MOD_SEL0_18_17
5538 MOD_SEL0_16
5539 0, 0, /* RESERVED 15 */
5540 MOD_SEL0_14_13
5541 MOD_SEL0_12
5542 MOD_SEL0_11
5543 MOD_SEL0_10
5544 MOD_SEL0_9_8
5545 MOD_SEL0_7_6
5546 MOD_SEL0_5
5547 MOD_SEL0_4_3
5548 /* RESERVED 2, 1, 0 */
5549 0, 0, 0, 0, 0, 0, 0, 0 }
5550 },
5551 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5552 2, 3, 1, 2, 3, 1, 1, 2, 1,
5553 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5554 MOD_SEL1_31_30
5555 MOD_SEL1_29_28_27
5556 MOD_SEL1_26
5557 MOD_SEL1_25_24
5558 MOD_SEL1_23_22_21
5559 MOD_SEL1_20
5560 MOD_SEL1_19
5561 MOD_SEL1_18_17
5562 MOD_SEL1_16
5563 MOD_SEL1_15_14
5564 MOD_SEL1_13
5565 MOD_SEL1_12
5566 MOD_SEL1_11
5567 MOD_SEL1_10
5568 MOD_SEL1_9
5569 0, 0, 0, 0, /* RESERVED 8, 7 */
5570 MOD_SEL1_6
5571 MOD_SEL1_5
5572 MOD_SEL1_4
5573 MOD_SEL1_3
5574 MOD_SEL1_2
5575 MOD_SEL1_1
5576 MOD_SEL1_0 }
5577 },
5578 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5579 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5580 4, 4, 4, 3, 1) {
5581 MOD_SEL2_31
5582 MOD_SEL2_30
5583 MOD_SEL2_29
5584 MOD_SEL2_28_27
5585 MOD_SEL2_26
5586 MOD_SEL2_25_24_23
5587 MOD_SEL2_22
5588 MOD_SEL2_21
5589 MOD_SEL2_20
5590 MOD_SEL2_19
5591 MOD_SEL2_18
5592 MOD_SEL2_17
5593 /* RESERVED 16 */
5594 0, 0,
5595 /* RESERVED 15, 14, 13, 12 */
5596 0, 0, 0, 0, 0, 0, 0, 0,
5597 0, 0, 0, 0, 0, 0, 0, 0,
5598 /* RESERVED 11, 10, 9, 8 */
5599 0, 0, 0, 0, 0, 0, 0, 0,
5600 0, 0, 0, 0, 0, 0, 0, 0,
5601 /* RESERVED 7, 6, 5, 4 */
5602 0, 0, 0, 0, 0, 0, 0, 0,
5603 0, 0, 0, 0, 0, 0, 0, 0,
5604 /* RESERVED 3, 2, 1 */
5605 0, 0, 0, 0, 0, 0, 0, 0,
5606 MOD_SEL2_0 }
5607 },
5608 { },
5609};
5610
5611static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5612 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5613 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5614 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5615 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5616 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5617 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5618 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5619 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5620 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5621 } },
5622 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5623 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5624 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5625 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5626 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5627 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5628 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5629 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5630 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5631 } },
5632 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5633 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5634 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5635 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5636 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5637 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5638 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5639 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5640 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5641 } },
5642 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5643 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5644 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5645 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5646 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5647 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5648 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5649 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5650 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5651 } },
5652 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5653 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5654 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5655 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5656 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5657 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5658 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5659 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5660 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5661 } },
5662 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5663 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5664 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5665 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5666 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5667 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5668 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5669 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5670 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5671 } },
5672 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5673 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5674 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5675 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5676 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5677 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5678 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5679 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5680 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5681 } },
5682 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5683 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5684 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5685 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5686 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5687 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5688 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5689 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5690 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5691 } },
5692 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5693 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5694 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5695 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5696 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5697 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5698 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5699 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5700 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5701 } },
5702 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5703 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5704 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5705 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5706 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5707 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5708 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5709 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5710 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5711 } },
5712 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5713 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5714 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5715 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5716 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5717 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5718 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5719 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5720 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5721 } },
5722 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5723 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5724 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5725 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5726 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5727 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5728 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5729 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5730 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5731 } },
5732 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5733 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
5734 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5735 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5736 } },
5737 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5738 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5739 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5740 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5741 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5742 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5743 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5744 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5745 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5746 } },
5747 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5748 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5749 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5750 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5751 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5752 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5753 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5754 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5755 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5756 } },
5757 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5758 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5759 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5760 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5761 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5762 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5763 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5764 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5765 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5766 } },
5767 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5768 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5769 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5770 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5771 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5772 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5773 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5774 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5775 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5776 } },
5777 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5778 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5779 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5780 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5781 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5782 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5783 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5784 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5785 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5786 } },
5787 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5788 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5789 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5790 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5791 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5792 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5793 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5794 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5795 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5796 } },
5797 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5798 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5799 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5800 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5801 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5802 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5803 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5804 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5805 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5806 } },
5807 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5808 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5809 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5810 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5811 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5812 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5813 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5814 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5815 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5816 } },
5817 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5818 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5819 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5820 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5821 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5822 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5823 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5824 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5825 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5826 } },
5827 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5828 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5829 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5830 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5831 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5832 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5833 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5834 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5835 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5836 } },
5837 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5838 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5839 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5840 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5841 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5842 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5843 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5844 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5845 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5846 } },
5847 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5848 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5849 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5850 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5851 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5852 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5853 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5854 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5855 } },
5856 { },
5857};
5858
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5859enum ioctrl_regs {
5860 POCCTRL,
5861};
5862
5863static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5864 [POCCTRL] = { 0xe6060380, },
5865 { /* sentinel */ },
5866};
5867
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5868static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5869{
5870 int bit = -EINVAL;
5871
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5872 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5873
5874 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5875 bit = pin & 0x1f;
5876
5877 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5878 bit = (pin & 0x1f) + 12;
5879
5880 return bit;
5881}
5882
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5883static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5884 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5885 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5886 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5887 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5888 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5889 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5890 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5891 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5892 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5893 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5894 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5895 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5896 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5897 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5898 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5899 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5900 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5901 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5902 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5903 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5904 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5905 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5906 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5907 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5908 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5909 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5910 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5911 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5912 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5913 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5914 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5915 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5916 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5917 } },
5918 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5919 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5920 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5921 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5922 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5923 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5924 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5925 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5926 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5927 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5928 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5929 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5930 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5931 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5932 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5933 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5934 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5935 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5936 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5937 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5938 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5939 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5940 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5941 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5942 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5943 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5944 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5945 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5946 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5947 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5948 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5949 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5950 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5951 } },
5952 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5953 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5954 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5955 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5956 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5957 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5958 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5959 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5960 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5961 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5962 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5963 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5964 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5965 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5966 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5967 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5968 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5969 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5970 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5971 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5972 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5973 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5974 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5975 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5976 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5977 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5978 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5979 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5980 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5981 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5982 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5983 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5984 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5985 } },
5986 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5987 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
5988 [ 1] = PIN_NONE,
5989 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
5990 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5991 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5992 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5993 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5994 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5995 [ 8] = PIN_NONE,
5996 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5997 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5998 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5999 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6000 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6001 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6002 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6003 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6004 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6005 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6006 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6007 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6008 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6009 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6010 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6011 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6012 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6013 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6014 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6015 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6016 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6017 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6018 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6019 } },
6020 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6021 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6022 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6023 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6024 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6025 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6026 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6027 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6028 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6029 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6030 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6031 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6032 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6033 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6034 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6035 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6036 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6037 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6038 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6039 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6040 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6041 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6042 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6043 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6044 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6045 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6046 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6047 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6048 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6049 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6050 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6051 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6052 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6053 } },
6054 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6055 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6056 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6057 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6058 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6059 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6060 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6061 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6062 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6063 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6064 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6065 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6066 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6067 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6068 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6069 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6070 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6071 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6072 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6073 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6074 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6075 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6076 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6077 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6078 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6079 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6080 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6081 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6082 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6083 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6084 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6085 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6086 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6087 } },
6088 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6089 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6090 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6091 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6092 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6093 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6094 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6095 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6096 [ 7] = PIN_NONE,
6097 [ 8] = PIN_NONE,
6098 [ 9] = PIN_NONE,
6099 [10] = PIN_NONE,
6100 [11] = PIN_NONE,
6101 [12] = PIN_NONE,
6102 [13] = PIN_NONE,
6103 [14] = PIN_NONE,
6104 [15] = PIN_NONE,
6105 [16] = PIN_NONE,
6106 [17] = PIN_NONE,
6107 [18] = PIN_NONE,
6108 [19] = PIN_NONE,
6109 [20] = PIN_NONE,
6110 [21] = PIN_NONE,
6111 [22] = PIN_NONE,
6112 [23] = PIN_NONE,
6113 [24] = PIN_NONE,
6114 [25] = PIN_NONE,
6115 [26] = PIN_NONE,
6116 [27] = PIN_NONE,
6117 [28] = PIN_NONE,
6118 [29] = PIN_NONE,
6119 [30] = PIN_NONE,
6120 [31] = PIN_NONE,
6121 } },
6122 { /* sentinel */ },
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6123};
6124
6125static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
6126 unsigned int pin)
6127{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6128 const struct pinmux_bias_reg *reg;
6129 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6130
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6131 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6132 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6133 return PIN_CONFIG_BIAS_DISABLE;
6134
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6135 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6136 return PIN_CONFIG_BIAS_DISABLE;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6137 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6138 return PIN_CONFIG_BIAS_PULL_UP;
6139 else
6140 return PIN_CONFIG_BIAS_PULL_DOWN;
6141}
6142
6143static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6144 unsigned int bias)
6145{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6146 const struct pinmux_bias_reg *reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6147 u32 enable, updown;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6148 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6149
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6150 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6151 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6152 return;
6153
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6154 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6155 if (bias != PIN_CONFIG_BIAS_DISABLE)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6156 enable |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6157
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6158 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6159 if (bias == PIN_CONFIG_BIAS_PULL_UP)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6160 updown |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6161
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6162 sh_pfc_write(pfc, reg->pud, updown);
6163 sh_pfc_write(pfc, reg->puen, enable);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6164}
6165
6166static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6167 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6168 .get_bias = r8a7796_pinmux_get_bias,
6169 .set_bias = r8a7796_pinmux_set_bias,
6170};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6171
6172#ifdef CONFIG_PINCTRL_PFC_R8A774A1
6173const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6174 .name = "r8a774a1_pfc",
6175 .ops = &r8a7796_pinmux_ops,
6176 .unlock_reg = 0xe6060000, /* PMMR */
6177
6178 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6179
6180 .pins = pinmux_pins,
6181 .nr_pins = ARRAY_SIZE(pinmux_pins),
6182 .groups = pinmux_groups.common,
6183 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6184 .functions = pinmux_functions.common,
6185 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6186
6187 .cfg_regs = pinmux_config_regs,
6188 .drive_regs = pinmux_drive_regs,
6189 .bias_regs = pinmux_bias_regs,
6190 .ioctrl_regs = pinmux_ioctrl_regs,
6191
6192 .pinmux_data = pinmux_data,
6193 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6194};
6195#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6196
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6197#ifdef CONFIG_PINCTRL_PFC_R8A7796
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6198const struct sh_pfc_soc_info r8a7796_pinmux_info = {
6199 .name = "r8a77960_pfc",
6200 .ops = &r8a7796_pinmux_ops,
6201 .unlock_reg = 0xe6060000, /* PMMR */
6202
6203 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6204
6205 .pins = pinmux_pins,
6206 .nr_pins = ARRAY_SIZE(pinmux_pins),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6207 .groups = pinmux_groups.common,
6208 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6209 ARRAY_SIZE(pinmux_groups.automotive),
6210 .functions = pinmux_functions.common,
6211 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6212 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6213
6214 .cfg_regs = pinmux_config_regs,
6215 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6216 .bias_regs = pinmux_bias_regs,
6217 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6218
6219 .pinmux_data = pinmux_data,
6220 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6221};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6222#endif