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git01.mediatek.com / filogic / uboot / 10e4779db8ae6c2784392fa7a1f690645918662d / . / drivers / pinctrl / renesas / pfc-r8a7796.c
blob: 50b93317c47f17fc975af6e067c00b576918e754 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
3 * R8A7796 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]12 */
13
14#include <common.h>
15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/kernel.h>
19
20#include "sh_pfc.h"
21
22#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
23 SH_PFC_PIN_CFG_PULL_UP | \
24 SH_PFC_PIN_CFG_PULL_DOWN)
25
26#define CPU_ALL_PORT(fn, sfx) \
27 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
36 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
39/*
40 * F_() : just information
41 * FM() : macro for FN_xxx / xxx_MARK
42 */
43
44/* GPSR0 */
45#define GPSR0_15 F_(D15, IP7_11_8)
46#define GPSR0_14 F_(D14, IP7_7_4)
47#define GPSR0_13 F_(D13, IP7_3_0)
48#define GPSR0_12 F_(D12, IP6_31_28)
49#define GPSR0_11 F_(D11, IP6_27_24)
50#define GPSR0_10 F_(D10, IP6_23_20)
51#define GPSR0_9 F_(D9, IP6_19_16)
52#define GPSR0_8 F_(D8, IP6_15_12)
53#define GPSR0_7 F_(D7, IP6_11_8)
54#define GPSR0_6 F_(D6, IP6_7_4)
55#define GPSR0_5 F_(D5, IP6_3_0)
56#define GPSR0_4 F_(D4, IP5_31_28)
57#define GPSR0_3 F_(D3, IP5_27_24)
58#define GPSR0_2 F_(D2, IP5_23_20)
59#define GPSR0_1 F_(D1, IP5_19_16)
60#define GPSR0_0 F_(D0, IP5_15_12)
61
62/* GPSR1 */
63#define GPSR1_28 FM(CLKOUT)
64#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
65#define GPSR1_26 F_(WE1_N, IP5_7_4)
66#define GPSR1_25 F_(WE0_N, IP5_3_0)
67#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
68#define GPSR1_23 F_(RD_N, IP4_27_24)
69#define GPSR1_22 F_(BS_N, IP4_23_20)
70#define GPSR1_21 F_(CS1_N, IP4_19_16)
71#define GPSR1_20 F_(CS0_N, IP4_15_12)
72#define GPSR1_19 F_(A19, IP4_11_8)
73#define GPSR1_18 F_(A18, IP4_7_4)
74#define GPSR1_17 F_(A17, IP4_3_0)
75#define GPSR1_16 F_(A16, IP3_31_28)
76#define GPSR1_15 F_(A15, IP3_27_24)
77#define GPSR1_14 F_(A14, IP3_23_20)
78#define GPSR1_13 F_(A13, IP3_19_16)
79#define GPSR1_12 F_(A12, IP3_15_12)
80#define GPSR1_11 F_(A11, IP3_11_8)
81#define GPSR1_10 F_(A10, IP3_7_4)
82#define GPSR1_9 F_(A9, IP3_3_0)
83#define GPSR1_8 F_(A8, IP2_31_28)
84#define GPSR1_7 F_(A7, IP2_27_24)
85#define GPSR1_6 F_(A6, IP2_23_20)
86#define GPSR1_5 F_(A5, IP2_19_16)
87#define GPSR1_4 F_(A4, IP2_15_12)
88#define GPSR1_3 F_(A3, IP2_11_8)
89#define GPSR1_2 F_(A2, IP2_7_4)
90#define GPSR1_1 F_(A1, IP2_3_0)
91#define GPSR1_0 F_(A0, IP1_31_28)
92
93/* GPSR2 */
94#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
95#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
96#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
97#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
98#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
99#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
100#define GPSR2_8 F_(PWM2_A, IP1_27_24)
101#define GPSR2_7 F_(PWM1_A, IP1_23_20)
102#define GPSR2_6 F_(PWM0, IP1_19_16)
103#define GPSR2_5 F_(IRQ5, IP1_15_12)
104#define GPSR2_4 F_(IRQ4, IP1_11_8)
105#define GPSR2_3 F_(IRQ3, IP1_7_4)
106#define GPSR2_2 F_(IRQ2, IP1_3_0)
107#define GPSR2_1 F_(IRQ1, IP0_31_28)
108#define GPSR2_0 F_(IRQ0, IP0_27_24)
109
110/* GPSR3 */
111#define GPSR3_15 F_(SD1_WP, IP11_23_20)
112#define GPSR3_14 F_(SD1_CD, IP11_19_16)
113#define GPSR3_13 F_(SD0_WP, IP11_15_12)
114#define GPSR3_12 F_(SD0_CD, IP11_11_8)
115#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
116#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
117#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
118#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
119#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
120#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
121#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
122#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
123#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
124#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
125#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
126#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
127
128/* GPSR4 */
129#define GPSR4_17 F_(SD3_DS, IP11_7_4)
130#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
131#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
132#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
133#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
134#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
135#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
136#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
137#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
138#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
139#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
140#define GPSR4_6 F_(SD2_DS, IP9_27_24)
141#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
142#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
143#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
144#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
145#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
146#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
147
148/* GPSR5 */
149#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
150#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
151#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
152#define GPSR5_22 FM(MSIOF0_RXD)
153#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
154#define GPSR5_20 FM(MSIOF0_TXD)
155#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
156#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
157#define GPSR5_17 FM(MSIOF0_SCK)
158#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
159#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
160#define GPSR5_14 F_(HTX0, IP13_19_16)
161#define GPSR5_13 F_(HRX0, IP13_15_12)
162#define GPSR5_12 F_(HSCK0, IP13_11_8)
163#define GPSR5_11 F_(RX2_A, IP13_7_4)
164#define GPSR5_10 F_(TX2_A, IP13_3_0)
165#define GPSR5_9 F_(SCK2, IP12_31_28)
166#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
167#define GPSR5_7 F_(CTS1_N, IP12_23_20)
168#define GPSR5_6 F_(TX1_A, IP12_19_16)
169#define GPSR5_5 F_(RX1_A, IP12_15_12)
170#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
171#define GPSR5_3 F_(CTS0_N, IP12_7_4)
172#define GPSR5_2 F_(TX0, IP12_3_0)
173#define GPSR5_1 F_(RX0, IP11_31_28)
174#define GPSR5_0 F_(SCK0, IP11_27_24)
175
176/* GPSR6 */
177#define GPSR6_31 F_(GP6_31, IP18_7_4)
178#define GPSR6_30 F_(GP6_30, IP18_3_0)
179#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
180#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
181#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
182#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
183#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
184#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
185#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
186#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
187#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
188#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
189#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
190#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
191#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
192#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
193#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
194#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
195#define GPSR6_13 FM(SSI_SDATA5)
196#define GPSR6_12 FM(SSI_WS5)
197#define GPSR6_11 FM(SSI_SCK5)
198#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
199#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
200#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
201#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
202#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
203#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
204#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
205#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
206#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
207#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
208#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
209
210/* GPSR7 */
211#define GPSR7_3 FM(GP7_03)
212#define GPSR7_2 FM(HDMI0_CEC)
213#define GPSR7_1 FM(AVS2)
214#define GPSR7_0 FM(AVS1)
215
216
217/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
218#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245
246/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
247#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276
277/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
278#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312
313/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
314#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
335#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342
343/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
344#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
364#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
365#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
366#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
367#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
368#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
370#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
371
372#define PINMUX_GPSR \
373\
374 GPSR6_31 \
375 GPSR6_30 \
376 GPSR6_29 \
377 GPSR1_28 GPSR6_28 \
378 GPSR1_27 GPSR6_27 \
379 GPSR1_26 GPSR6_26 \
380 GPSR1_25 GPSR5_25 GPSR6_25 \
381 GPSR1_24 GPSR5_24 GPSR6_24 \
382 GPSR1_23 GPSR5_23 GPSR6_23 \
383 GPSR1_22 GPSR5_22 GPSR6_22 \
384 GPSR1_21 GPSR5_21 GPSR6_21 \
385 GPSR1_20 GPSR5_20 GPSR6_20 \
386 GPSR1_19 GPSR5_19 GPSR6_19 \
387 GPSR1_18 GPSR5_18 GPSR6_18 \
388 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
389 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
390GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
391GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
392GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
393GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
394GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
395GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
396GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
397GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
398GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
399GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
400GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
401GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
402GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
403GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
404GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
405GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
406
407#define PINMUX_IPSR \
408\
409FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
410FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
411FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
412FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
413FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
414FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
415FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
416FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
417\
418FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
419FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
420FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
421FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
422FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
423FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
424FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
425FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
426\
427FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
428FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
429FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
430FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
431FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
432FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
433FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
434FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
435\
436FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
437FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
438FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
439FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
440FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
441FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
442FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
443FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
444\
445FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
446FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
447FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
448FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
449FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
450FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
451FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
452FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
453
454/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
455#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
456#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
457#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
458#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
459#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
460#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
461#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
462#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
463#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
464#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
465#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
466#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
467#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
468#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
469#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
470#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
471#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
472#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
473
474/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
475#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
476#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
477#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
478#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
479#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
480#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
481#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
482#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
483#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
484#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
485#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
486#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
487#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
488#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
489#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
490#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
491#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
492#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
493#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
494#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
495#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
496#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
497
498/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
499#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
500#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
501#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
502#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
503#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
504#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
505#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
506#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
507#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
508#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
509#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
510#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
511#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
512
513#define PINMUX_MOD_SELS \
514\
515MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
516 MOD_SEL2_30 \
517 MOD_SEL1_29_28_27 MOD_SEL2_29 \
518MOD_SEL0_28_27 MOD_SEL2_28_27 \
519MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
520 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
521MOD_SEL0_23 MOD_SEL1_23_22_21 \
522MOD_SEL0_22 MOD_SEL2_22 \
523MOD_SEL0_21 MOD_SEL2_21 \
524MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
525MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
526MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
527 MOD_SEL2_17 \
528MOD_SEL0_16 MOD_SEL1_16 \
529 MOD_SEL1_15_14 \
530MOD_SEL0_14_13 \
531 MOD_SEL1_13 \
532MOD_SEL0_12 MOD_SEL1_12 \
533MOD_SEL0_11 MOD_SEL1_11 \
534MOD_SEL0_10 MOD_SEL1_10 \
535MOD_SEL0_9_8 MOD_SEL1_9 \
536MOD_SEL0_7_6 \
537 MOD_SEL1_6 \
538MOD_SEL0_5 MOD_SEL1_5 \
539MOD_SEL0_4_3 MOD_SEL1_4 \
540 MOD_SEL1_3 \
541 MOD_SEL1_2 \
542 MOD_SEL1_1 \
543 MOD_SEL1_0 MOD_SEL2_0
544
545/*
546 * These pins are not able to be muxed but have other properties
547 * that can be set, such as drive-strength or pull-up/pull-down enable.
548 */
549#define PINMUX_STATIC \
550 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
551 FM(QSPI0_IO2) FM(QSPI0_IO3) \
552 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
553 FM(QSPI1_IO2) FM(QSPI1_IO3) \
554 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
555 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
556 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
557 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
558 FM(PRESETOUT) \
559 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
560 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
561
562enum {
563 PINMUX_RESERVED = 0,
564
565 PINMUX_DATA_BEGIN,
566 GP_ALL(DATA),
567 PINMUX_DATA_END,
568
569#define F_(x, y)
570#define FM(x) FN_##x,
571 PINMUX_FUNCTION_BEGIN,
572 GP_ALL(FN),
573 PINMUX_GPSR
574 PINMUX_IPSR
575 PINMUX_MOD_SELS
576 PINMUX_FUNCTION_END,
577#undef F_
578#undef FM
579
580#define F_(x, y)
581#define FM(x) x##_MARK,
582 PINMUX_MARK_BEGIN,
583 PINMUX_GPSR
584 PINMUX_IPSR
585 PINMUX_MOD_SELS
586 PINMUX_STATIC
587 PINMUX_MARK_END,
588#undef F_
589#undef FM
590};
591
592static const u16 pinmux_data[] = {
593 PINMUX_DATA_GP_ALL(),
594
595 PINMUX_SINGLE(AVS1),
596 PINMUX_SINGLE(AVS2),
597 PINMUX_SINGLE(CLKOUT),
598 PINMUX_SINGLE(GP7_03),
599 PINMUX_SINGLE(HDMI0_CEC),
600 PINMUX_SINGLE(MSIOF0_RXD),
601 PINMUX_SINGLE(MSIOF0_SCK),
602 PINMUX_SINGLE(MSIOF0_TXD),
603 PINMUX_SINGLE(SSI_SCK5),
604 PINMUX_SINGLE(SSI_SDATA5),
605 PINMUX_SINGLE(SSI_WS5),
606
607 /* IPSR0 */
608 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
609 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
610
611 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
612 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
613 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
614
615 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
616 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
617 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
618
619 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
620 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
621 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
622
623 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
624 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
626
627 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
628 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
629 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
630
631 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
632 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
633 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
634 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
637 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
638
639 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
640 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
641 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
642 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
645 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
646
647 /* IPSR1 */
648 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
649 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
650 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
651 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
652 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
653 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
654
655 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
656 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
657 PINMUX_IPSR_GPSR(IP1_7_4, A25),
658 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
659 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
660 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
661 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
662
663 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
664 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
665 PINMUX_IPSR_GPSR(IP1_11_8, A24),
666 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
667 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
668 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
669 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
670
671 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
672 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
673 PINMUX_IPSR_GPSR(IP1_15_12, A23),
674 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
675 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
676 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
677 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
678
679 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
680 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
681 PINMUX_IPSR_GPSR(IP1_19_16, A22),
682 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
683 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
684
685 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
686 PINMUX_IPSR_GPSR(IP1_23_20, A21),
687 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
688 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
689 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
690
691 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
692 PINMUX_IPSR_GPSR(IP1_27_24, A20),
693 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
694 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
695
696 PINMUX_IPSR_GPSR(IP1_31_28, A0),
697 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
698 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
699 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
700 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
701 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
702
703 /* IPSR2 */
704 PINMUX_IPSR_GPSR(IP2_3_0, A1),
705 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
706 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
707 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
708 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
709 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
710
711 PINMUX_IPSR_GPSR(IP2_7_4, A2),
712 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
713 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
714 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
715 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
716 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
717
718 PINMUX_IPSR_GPSR(IP2_11_8, A3),
719 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
720 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
721 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
722 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
723 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
724
725 PINMUX_IPSR_GPSR(IP2_15_12, A4),
726 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
727 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
728 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
729 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
730 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
731
732 PINMUX_IPSR_GPSR(IP2_19_16, A5),
733 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
734 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
735 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
736 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
737 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
738 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
739
740 PINMUX_IPSR_GPSR(IP2_23_20, A6),
741 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
742 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
743 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
744 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
745 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
746 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
747
748 PINMUX_IPSR_GPSR(IP2_27_24, A7),
749 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
750 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
751 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
752 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
753 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
754 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
755
756 PINMUX_IPSR_GPSR(IP2_31_28, A8),
757 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
758 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
759 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
760 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
761 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
762 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
763
764 /* IPSR3 */
765 PINMUX_IPSR_GPSR(IP3_3_0, A9),
766 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
767 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
768 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
769
770 PINMUX_IPSR_GPSR(IP3_7_4, A10),
771 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
774
775 PINMUX_IPSR_GPSR(IP3_11_8, A11),
776 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
777 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
778 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
779 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
780 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
781 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
782 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
783 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
784
785 PINMUX_IPSR_GPSR(IP3_15_12, A12),
786 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
787 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
788 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
789 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
790 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
791
792 PINMUX_IPSR_GPSR(IP3_19_16, A13),
793 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
794 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
795 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
796 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
797 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
798
799 PINMUX_IPSR_GPSR(IP3_23_20, A14),
800 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
801 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
802 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
803 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
804 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
805
806 PINMUX_IPSR_GPSR(IP3_27_24, A15),
807 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
808 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
809 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
810 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
811 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
812
813 PINMUX_IPSR_GPSR(IP3_31_28, A16),
814 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
815 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
816 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
817
818 /* IPSR4 */
819 PINMUX_IPSR_GPSR(IP4_3_0, A17),
820 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
821 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
822 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
823
824 PINMUX_IPSR_GPSR(IP4_7_4, A18),
825 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
826 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
827 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
828
829 PINMUX_IPSR_GPSR(IP4_11_8, A19),
830 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
831 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
832 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
833
834 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
835 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
836
837 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
838 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
839 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
840
841 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
842 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
843 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
844 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
845 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
846 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
847 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
848 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
849
850 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
851 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
852 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
855 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
856
857 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
858 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
859 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
860 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
861 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
862 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
863
864 /* IPSR5 */
865 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
866 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
867 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
868 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
869 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
870 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
871 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
872
873 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
874 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
875 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
876 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
877 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
878 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
879 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
880 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
881
882 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
883 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
884 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
885 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
886
887 PINMUX_IPSR_GPSR(IP5_15_12, D0),
888 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
889 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
890 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
891 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
892
893 PINMUX_IPSR_GPSR(IP5_19_16, D1),
894 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
895 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
896 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
897 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
898
899 PINMUX_IPSR_GPSR(IP5_23_20, D2),
900 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
901 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
902 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
903
904 PINMUX_IPSR_GPSR(IP5_27_24, D3),
905 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
906 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
907 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
908
909 PINMUX_IPSR_GPSR(IP5_31_28, D4),
910 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
911 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
912 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
913
914 /* IPSR6 */
915 PINMUX_IPSR_GPSR(IP6_3_0, D5),
916 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
917 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
918 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
919
920 PINMUX_IPSR_GPSR(IP6_7_4, D6),
921 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
922 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
923 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
924
925 PINMUX_IPSR_GPSR(IP6_11_8, D7),
926 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
927 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
928 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
929
930 PINMUX_IPSR_GPSR(IP6_15_12, D8),
931 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
932 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
933 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
934 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
935 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
936
937 PINMUX_IPSR_GPSR(IP6_19_16, D9),
938 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
939 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
941 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
942
943 PINMUX_IPSR_GPSR(IP6_23_20, D10),
944 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
945 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
946 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
947 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
948 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
949 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
950
951 PINMUX_IPSR_GPSR(IP6_27_24, D11),
952 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
953 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
954 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
955 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
956 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
957 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
958
959 PINMUX_IPSR_GPSR(IP6_31_28, D12),
960 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
961 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
962 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
963 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
964 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
965
966 /* IPSR7 */
967 PINMUX_IPSR_GPSR(IP7_3_0, D13),
968 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
969 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
970 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
971 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
972 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
973
974 PINMUX_IPSR_GPSR(IP7_7_4, D14),
975 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
976 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
977 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
978 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
979 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
980 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
981
982 PINMUX_IPSR_GPSR(IP7_11_8, D15),
983 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
984 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
985 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
986 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
987 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
988 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
989
990 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
991 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
992 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
993
994 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
995 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
996 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
997
998 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
999 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1000 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1001 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1002
1003 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1004 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1007
1008 /* IPSR8 */
1009 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1010 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1011 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1012 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1013
1014 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1015 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1016 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1017 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1018
1019 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1020 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1021 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1022
1023 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1024 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1025 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1026 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1027 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1028
1029 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1030 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1031 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1032 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1033 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1034 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1035
1036 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1037 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1038 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1039 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1040 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1041 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1042
1043 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1044 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1045 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1046 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1047 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1048 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1049
1050 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1051 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1052 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1053 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1054 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1055 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1056
1057 /* IPSR9 */
1058 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1059 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1060
1061 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1062 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1063
1064 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1065 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1066
1067 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1068 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1069
1070 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1071 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1072
1073 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1074 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1075
1076 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1077 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1078
1079 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1080 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1081
1082 /* IPSR10 */
1083 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1084 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1085
1086 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1087 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1088
1089 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1090 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1091
1092 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1093 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1094
1095 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1096 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1097
1098 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1099 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1100 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1101
1102 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1103 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1104 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1105
1106 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1107 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1108 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1109
1110 /* IPSR11 */
1111 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1112 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1113 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1114
1115 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1116 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1117
1118 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1119 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1120 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1121
1122 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1123 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1124
1125 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1126 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1127
1128 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1129 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1130
1131 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1132 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1134 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1136 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1137 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1139 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1140 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1141
1142 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1143 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1144 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1145 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1146 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1147
1148 /* IPSR12 */
1149 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1150 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1151 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1152 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1153 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1154
1155 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1156 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1157 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1158 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1159 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1160 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1161 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1162 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1163
1164 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1165 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1168 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1169 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1170 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1171 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1172
1173 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1175 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1176 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1177 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1178
1179 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1181 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1182 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1183 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1184
1185 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1186 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1187 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1188 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1189 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1190 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1191 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1192
1193 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1194 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1195 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1196 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1197 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1198 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1199 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1200
1201 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1202 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1203 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1204 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1205 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1206 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1207 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1208
1209 /* IPSR13 */
1210 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1212 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1214 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1215 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1216
1217 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1219 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1221 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1222 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1223
1224 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1226 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1227 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1228 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1229 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1230 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1231 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1232
1233 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1234 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1236 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1238 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1239
1240 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1241 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1243 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1245 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1246
1247 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1248 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1249 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1251 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1253 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1254 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1255
1256 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1257 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1258 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1260 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1261 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1262 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1263
1264 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1265 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1266 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1267 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1268
1269 /* IPSR14 */
1270 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1271 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1272 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1273 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1274 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1275 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1276 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1277 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1278
1279 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1280 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1282 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1284 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1285 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1286 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1287
1288 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1289 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1290 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1291
1292 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1293 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1294 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1295 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1296
1297 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1298 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1299 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1300
1301 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1302 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1303
1304 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1305 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1306
1307 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1308 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1309
1310 /* IPSR15 */
1311 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1312
1313 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1314 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1315
1316 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1317 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1318 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1319
1320 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1321 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1322 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1323 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1324
1325 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1326 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1332
1333 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1334 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1340
1341 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1342 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1348
1349 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1350 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1356
1357 /* IPSR16 */
1358 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1359 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1360
1361 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1362 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1363
1364 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1365 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1366
1367 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1368 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1369 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1370 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1371 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1374
1375 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1376 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1377 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1378 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1382
1383 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1384 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1385 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1386 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1391
1392 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1393 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1394 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1395 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1396 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1399
1400 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1401 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1402 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1403 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1404 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1405 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1406 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1407 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1408
1409 /* IPSR17 */
1410 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1411 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1412
1413 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1414 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1415 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1416 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1417 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1418
1419 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1420 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1421 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1422 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1424 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1426
1427 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1428 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1429 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1430 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1432 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1433
1434 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1435 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1437 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1438 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1440 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1443
1444 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1445 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1446 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1447 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1448 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1450 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1453
1454 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1455 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1456 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1457 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1458 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1460 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1461 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1462 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1463 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1464 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1465
1466 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1467 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1468 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1469 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1470 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1472 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1473 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1474 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1475
1476 /* IPSR18 */
1477 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1478 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1479 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1480 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1481 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1483 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1484 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1486
1487 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1488 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1489 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1490 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1491 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1493 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1494 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1496
1497 /* I2C */
1498 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1499 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1500 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1501
1502/*
1503 * Static pins can not be muxed between different functions but
1504 * still needs a mark entry in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux then pin
1507 * while still applying configuration to it
1508 */
1509#define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511#undef FM
1512};
1513
1514/*
1515 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521
1522static const struct sh_pfc_pin pinmux_pins[] = {
1523 PINMUX_GPIO_GP_ALL(),
1524
1525 /*
1526 * Pins not associated with a GPIO port.
1527 *
1528 * The pin positions are different between different r8a7796
1529 * packages, all that is needed for the pfc driver is a unique
1530 * number for each pin. To this end use the pin layout from
1531 * R-Car M3SiP to calculate a unique number for each pin.
1532 */
1533 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1575};
1576
1577/* - AUDIO CLOCK ------------------------------------------------------------ */
1578static const unsigned int audio_clk_a_a_pins[] = {
1579 /* CLK A */
1580 RCAR_GP_PIN(6, 22),
1581};
1582static const unsigned int audio_clk_a_a_mux[] = {
1583 AUDIO_CLKA_A_MARK,
1584};
1585static const unsigned int audio_clk_a_b_pins[] = {
1586 /* CLK A */
1587 RCAR_GP_PIN(5, 4),
1588};
1589static const unsigned int audio_clk_a_b_mux[] = {
1590 AUDIO_CLKA_B_MARK,
1591};
1592static const unsigned int audio_clk_a_c_pins[] = {
1593 /* CLK A */
1594 RCAR_GP_PIN(5, 19),
1595};
1596static const unsigned int audio_clk_a_c_mux[] = {
1597 AUDIO_CLKA_C_MARK,
1598};
1599static const unsigned int audio_clk_b_a_pins[] = {
1600 /* CLK B */
1601 RCAR_GP_PIN(5, 12),
1602};
1603static const unsigned int audio_clk_b_a_mux[] = {
1604 AUDIO_CLKB_A_MARK,
1605};
1606static const unsigned int audio_clk_b_b_pins[] = {
1607 /* CLK B */
1608 RCAR_GP_PIN(6, 23),
1609};
1610static const unsigned int audio_clk_b_b_mux[] = {
1611 AUDIO_CLKB_B_MARK,
1612};
1613static const unsigned int audio_clk_c_a_pins[] = {
1614 /* CLK C */
1615 RCAR_GP_PIN(5, 21),
1616};
1617static const unsigned int audio_clk_c_a_mux[] = {
1618 AUDIO_CLKC_A_MARK,
1619};
1620static const unsigned int audio_clk_c_b_pins[] = {
1621 /* CLK C */
1622 RCAR_GP_PIN(5, 0),
1623};
1624static const unsigned int audio_clk_c_b_mux[] = {
1625 AUDIO_CLKC_B_MARK,
1626};
1627static const unsigned int audio_clkout_a_pins[] = {
1628 /* CLKOUT */
1629 RCAR_GP_PIN(5, 18),
1630};
1631static const unsigned int audio_clkout_a_mux[] = {
1632 AUDIO_CLKOUT_A_MARK,
1633};
1634static const unsigned int audio_clkout_b_pins[] = {
1635 /* CLKOUT */
1636 RCAR_GP_PIN(6, 28),
1637};
1638static const unsigned int audio_clkout_b_mux[] = {
1639 AUDIO_CLKOUT_B_MARK,
1640};
1641static const unsigned int audio_clkout_c_pins[] = {
1642 /* CLKOUT */
1643 RCAR_GP_PIN(5, 3),
1644};
1645static const unsigned int audio_clkout_c_mux[] = {
1646 AUDIO_CLKOUT_C_MARK,
1647};
1648static const unsigned int audio_clkout_d_pins[] = {
1649 /* CLKOUT */
1650 RCAR_GP_PIN(5, 21),
1651};
1652static const unsigned int audio_clkout_d_mux[] = {
1653 AUDIO_CLKOUT_D_MARK,
1654};
1655static const unsigned int audio_clkout1_a_pins[] = {
1656 /* CLKOUT1 */
1657 RCAR_GP_PIN(5, 15),
1658};
1659static const unsigned int audio_clkout1_a_mux[] = {
1660 AUDIO_CLKOUT1_A_MARK,
1661};
1662static const unsigned int audio_clkout1_b_pins[] = {
1663 /* CLKOUT1 */
1664 RCAR_GP_PIN(6, 29),
1665};
1666static const unsigned int audio_clkout1_b_mux[] = {
1667 AUDIO_CLKOUT1_B_MARK,
1668};
1669static const unsigned int audio_clkout2_a_pins[] = {
1670 /* CLKOUT2 */
1671 RCAR_GP_PIN(5, 16),
1672};
1673static const unsigned int audio_clkout2_a_mux[] = {
1674 AUDIO_CLKOUT2_A_MARK,
1675};
1676static const unsigned int audio_clkout2_b_pins[] = {
1677 /* CLKOUT2 */
1678 RCAR_GP_PIN(6, 30),
1679};
1680static const unsigned int audio_clkout2_b_mux[] = {
1681 AUDIO_CLKOUT2_B_MARK,
1682};
1683
1684static const unsigned int audio_clkout3_a_pins[] = {
1685 /* CLKOUT3 */
1686 RCAR_GP_PIN(5, 19),
1687};
1688static const unsigned int audio_clkout3_a_mux[] = {
1689 AUDIO_CLKOUT3_A_MARK,
1690};
1691static const unsigned int audio_clkout3_b_pins[] = {
1692 /* CLKOUT3 */
1693 RCAR_GP_PIN(6, 31),
1694};
1695static const unsigned int audio_clkout3_b_mux[] = {
1696 AUDIO_CLKOUT3_B_MARK,
1697};
1698
1699/* - EtherAVB --------------------------------------------------------------- */
1700static const unsigned int avb_link_pins[] = {
1701 /* AVB_LINK */
1702 RCAR_GP_PIN(2, 12),
1703};
1704static const unsigned int avb_link_mux[] = {
1705 AVB_LINK_MARK,
1706};
1707static const unsigned int avb_magic_pins[] = {
1708 /* AVB_MAGIC_ */
1709 RCAR_GP_PIN(2, 10),
1710};
1711static const unsigned int avb_magic_mux[] = {
1712 AVB_MAGIC_MARK,
1713};
1714static const unsigned int avb_phy_int_pins[] = {
1715 /* AVB_PHY_INT */
1716 RCAR_GP_PIN(2, 11),
1717};
1718static const unsigned int avb_phy_int_mux[] = {
1719 AVB_PHY_INT_MARK,
1720};
1721static const unsigned int avb_mdc_pins[] = {
1722 /* AVB_MDC, AVB_MDIO */
1723 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1724};
1725static const unsigned int avb_mdc_mux[] = {
1726 AVB_MDC_MARK, AVB_MDIO_MARK,
1727};
1728static const unsigned int avb_mii_pins[] = {
1729 /*
1730 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1731 * AVB_TD1, AVB_TD2, AVB_TD3,
1732 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1733 * AVB_RD1, AVB_RD2, AVB_RD3,
1734 * AVB_TXCREFCLK
1735 */
1736 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1737 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1738 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1739 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1740 PIN_NUMBER('A', 12),
1741
1742};
1743static const unsigned int avb_mii_mux[] = {
1744 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1745 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1746 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1747 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1748 AVB_TXCREFCLK_MARK,
1749};
1750static const unsigned int avb_avtp_pps_pins[] = {
1751 /* AVB_AVTP_PPS */
1752 RCAR_GP_PIN(2, 6),
1753};
1754static const unsigned int avb_avtp_pps_mux[] = {
1755 AVB_AVTP_PPS_MARK,
1756};
1757static const unsigned int avb_avtp_match_a_pins[] = {
1758 /* AVB_AVTP_MATCH_A */
1759 RCAR_GP_PIN(2, 13),
1760};
1761static const unsigned int avb_avtp_match_a_mux[] = {
1762 AVB_AVTP_MATCH_A_MARK,
1763};
1764static const unsigned int avb_avtp_capture_a_pins[] = {
1765 /* AVB_AVTP_CAPTURE_A */
1766 RCAR_GP_PIN(2, 14),
1767};
1768static const unsigned int avb_avtp_capture_a_mux[] = {
1769 AVB_AVTP_CAPTURE_A_MARK,
1770};
1771static const unsigned int avb_avtp_match_b_pins[] = {
1772 /* AVB_AVTP_MATCH_B */
1773 RCAR_GP_PIN(1, 8),
1774};
1775static const unsigned int avb_avtp_match_b_mux[] = {
1776 AVB_AVTP_MATCH_B_MARK,
1777};
1778static const unsigned int avb_avtp_capture_b_pins[] = {
1779 /* AVB_AVTP_CAPTURE_B */
1780 RCAR_GP_PIN(1, 11),
1781};
1782static const unsigned int avb_avtp_capture_b_mux[] = {
1783 AVB_AVTP_CAPTURE_B_MARK,
1784};
1785
1786/* - CAN ------------------------------------------------------------------ */
1787static const unsigned int can0_data_a_pins[] = {
1788 /* TX, RX */
1789 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1790};
1791static const unsigned int can0_data_a_mux[] = {
1792 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1793};
1794static const unsigned int can0_data_b_pins[] = {
1795 /* TX, RX */
1796 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1797};
1798static const unsigned int can0_data_b_mux[] = {
1799 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1800};
1801static const unsigned int can1_data_pins[] = {
1802 /* TX, RX */
1803 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1804};
1805static const unsigned int can1_data_mux[] = {
1806 CAN1_TX_MARK, CAN1_RX_MARK,
1807};
1808
1809/* - CAN Clock -------------------------------------------------------------- */
1810static const unsigned int can_clk_pins[] = {
1811 /* CLK */
1812 RCAR_GP_PIN(1, 25),
1813};
1814static const unsigned int can_clk_mux[] = {
1815 CAN_CLK_MARK,
1816};
1817
1818/* - CAN FD --------------------------------------------------------------- */
1819static const unsigned int canfd0_data_a_pins[] = {
1820 /* TX, RX */
1821 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1822};
1823static const unsigned int canfd0_data_a_mux[] = {
1824 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1825};
1826static const unsigned int canfd0_data_b_pins[] = {
1827 /* TX, RX */
1828 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1829};
1830static const unsigned int canfd0_data_b_mux[] = {
1831 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1832};
1833static const unsigned int canfd1_data_pins[] = {
1834 /* TX, RX */
1835 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1836};
1837static const unsigned int canfd1_data_mux[] = {
1838 CANFD1_TX_MARK, CANFD1_RX_MARK,
1839};
1840
1841/* - DRIF0 --------------------------------------------------------------- */
1842static const unsigned int drif0_ctrl_a_pins[] = {
1843 /* CLK, SYNC */
1844 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1845};
1846static const unsigned int drif0_ctrl_a_mux[] = {
1847 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1848};
1849static const unsigned int drif0_data0_a_pins[] = {
1850 /* D0 */
1851 RCAR_GP_PIN(6, 10),
1852};
1853static const unsigned int drif0_data0_a_mux[] = {
1854 RIF0_D0_A_MARK,
1855};
1856static const unsigned int drif0_data1_a_pins[] = {
1857 /* D1 */
1858 RCAR_GP_PIN(6, 7),
1859};
1860static const unsigned int drif0_data1_a_mux[] = {
1861 RIF0_D1_A_MARK,
1862};
1863static const unsigned int drif0_ctrl_b_pins[] = {
1864 /* CLK, SYNC */
1865 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1866};
1867static const unsigned int drif0_ctrl_b_mux[] = {
1868 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1869};
1870static const unsigned int drif0_data0_b_pins[] = {
1871 /* D0 */
1872 RCAR_GP_PIN(5, 1),
1873};
1874static const unsigned int drif0_data0_b_mux[] = {
1875 RIF0_D0_B_MARK,
1876};
1877static const unsigned int drif0_data1_b_pins[] = {
1878 /* D1 */
1879 RCAR_GP_PIN(5, 2),
1880};
1881static const unsigned int drif0_data1_b_mux[] = {
1882 RIF0_D1_B_MARK,
1883};
1884static const unsigned int drif0_ctrl_c_pins[] = {
1885 /* CLK, SYNC */
1886 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1887};
1888static const unsigned int drif0_ctrl_c_mux[] = {
1889 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1890};
1891static const unsigned int drif0_data0_c_pins[] = {
1892 /* D0 */
1893 RCAR_GP_PIN(5, 13),
1894};
1895static const unsigned int drif0_data0_c_mux[] = {
1896 RIF0_D0_C_MARK,
1897};
1898static const unsigned int drif0_data1_c_pins[] = {
1899 /* D1 */
1900 RCAR_GP_PIN(5, 14),
1901};
1902static const unsigned int drif0_data1_c_mux[] = {
1903 RIF0_D1_C_MARK,
1904};
1905/* - DRIF1 --------------------------------------------------------------- */
1906static const unsigned int drif1_ctrl_a_pins[] = {
1907 /* CLK, SYNC */
1908 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1909};
1910static const unsigned int drif1_ctrl_a_mux[] = {
1911 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1912};
1913static const unsigned int drif1_data0_a_pins[] = {
1914 /* D0 */
1915 RCAR_GP_PIN(6, 19),
1916};
1917static const unsigned int drif1_data0_a_mux[] = {
1918 RIF1_D0_A_MARK,
1919};
1920static const unsigned int drif1_data1_a_pins[] = {
1921 /* D1 */
1922 RCAR_GP_PIN(6, 20),
1923};
1924static const unsigned int drif1_data1_a_mux[] = {
1925 RIF1_D1_A_MARK,
1926};
1927static const unsigned int drif1_ctrl_b_pins[] = {
1928 /* CLK, SYNC */
1929 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1930};
1931static const unsigned int drif1_ctrl_b_mux[] = {
1932 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1933};
1934static const unsigned int drif1_data0_b_pins[] = {
1935 /* D0 */
1936 RCAR_GP_PIN(5, 7),
1937};
1938static const unsigned int drif1_data0_b_mux[] = {
1939 RIF1_D0_B_MARK,
1940};
1941static const unsigned int drif1_data1_b_pins[] = {
1942 /* D1 */
1943 RCAR_GP_PIN(5, 8),
1944};
1945static const unsigned int drif1_data1_b_mux[] = {
1946 RIF1_D1_B_MARK,
1947};
1948static const unsigned int drif1_ctrl_c_pins[] = {
1949 /* CLK, SYNC */
1950 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1951};
1952static const unsigned int drif1_ctrl_c_mux[] = {
1953 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1954};
1955static const unsigned int drif1_data0_c_pins[] = {
1956 /* D0 */
1957 RCAR_GP_PIN(5, 6),
1958};
1959static const unsigned int drif1_data0_c_mux[] = {
1960 RIF1_D0_C_MARK,
1961};
1962static const unsigned int drif1_data1_c_pins[] = {
1963 /* D1 */
1964 RCAR_GP_PIN(5, 10),
1965};
1966static const unsigned int drif1_data1_c_mux[] = {
1967 RIF1_D1_C_MARK,
1968};
1969/* - DRIF2 --------------------------------------------------------------- */
1970static const unsigned int drif2_ctrl_a_pins[] = {
1971 /* CLK, SYNC */
1972 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1973};
1974static const unsigned int drif2_ctrl_a_mux[] = {
1975 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1976};
1977static const unsigned int drif2_data0_a_pins[] = {
1978 /* D0 */
1979 RCAR_GP_PIN(6, 7),
1980};
1981static const unsigned int drif2_data0_a_mux[] = {
1982 RIF2_D0_A_MARK,
1983};
1984static const unsigned int drif2_data1_a_pins[] = {
1985 /* D1 */
1986 RCAR_GP_PIN(6, 10),
1987};
1988static const unsigned int drif2_data1_a_mux[] = {
1989 RIF2_D1_A_MARK,
1990};
1991static const unsigned int drif2_ctrl_b_pins[] = {
1992 /* CLK, SYNC */
1993 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1994};
1995static const unsigned int drif2_ctrl_b_mux[] = {
1996 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1997};
1998static const unsigned int drif2_data0_b_pins[] = {
1999 /* D0 */
2000 RCAR_GP_PIN(6, 30),
2001};
2002static const unsigned int drif2_data0_b_mux[] = {
2003 RIF2_D0_B_MARK,
2004};
2005static const unsigned int drif2_data1_b_pins[] = {
2006 /* D1 */
2007 RCAR_GP_PIN(6, 31),
2008};
2009static const unsigned int drif2_data1_b_mux[] = {
2010 RIF2_D1_B_MARK,
2011};
2012/* - DRIF3 --------------------------------------------------------------- */
2013static const unsigned int drif3_ctrl_a_pins[] = {
2014 /* CLK, SYNC */
2015 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2016};
2017static const unsigned int drif3_ctrl_a_mux[] = {
2018 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2019};
2020static const unsigned int drif3_data0_a_pins[] = {
2021 /* D0 */
2022 RCAR_GP_PIN(6, 19),
2023};
2024static const unsigned int drif3_data0_a_mux[] = {
2025 RIF3_D0_A_MARK,
2026};
2027static const unsigned int drif3_data1_a_pins[] = {
2028 /* D1 */
2029 RCAR_GP_PIN(6, 20),
2030};
2031static const unsigned int drif3_data1_a_mux[] = {
2032 RIF3_D1_A_MARK,
2033};
2034static const unsigned int drif3_ctrl_b_pins[] = {
2035 /* CLK, SYNC */
2036 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2037};
2038static const unsigned int drif3_ctrl_b_mux[] = {
2039 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2040};
2041static const unsigned int drif3_data0_b_pins[] = {
2042 /* D0 */
2043 RCAR_GP_PIN(6, 28),
2044};
2045static const unsigned int drif3_data0_b_mux[] = {
2046 RIF3_D0_B_MARK,
2047};
2048static const unsigned int drif3_data1_b_pins[] = {
2049 /* D1 */
2050 RCAR_GP_PIN(6, 29),
2051};
2052static const unsigned int drif3_data1_b_mux[] = {
2053 RIF3_D1_B_MARK,
2054};
2055
2056/* - DU --------------------------------------------------------------------- */
2057static const unsigned int du_rgb666_pins[] = {
2058 /* R[7:2], G[7:2], B[7:2] */
2059 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2060 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2061 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2062 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2063 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2064 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2065};
2066static const unsigned int du_rgb666_mux[] = {
2067 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2068 DU_DR3_MARK, DU_DR2_MARK,
2069 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2070 DU_DG3_MARK, DU_DG2_MARK,
2071 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2072 DU_DB3_MARK, DU_DB2_MARK,
2073};
2074static const unsigned int du_rgb888_pins[] = {
2075 /* R[7:0], G[7:0], B[7:0] */
2076 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2077 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2078 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2079 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2080 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2081 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2082 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2083 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2084 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2085};
2086static const unsigned int du_rgb888_mux[] = {
2087 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2088 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2089 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2090 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2091 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2092 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2093};
2094static const unsigned int du_clk_out_0_pins[] = {
2095 /* CLKOUT */
2096 RCAR_GP_PIN(1, 27),
2097};
2098static const unsigned int du_clk_out_0_mux[] = {
2099 DU_DOTCLKOUT0_MARK
2100};
2101static const unsigned int du_clk_out_1_pins[] = {
2102 /* CLKOUT */
2103 RCAR_GP_PIN(2, 3),
2104};
2105static const unsigned int du_clk_out_1_mux[] = {
2106 DU_DOTCLKOUT1_MARK
2107};
2108static const unsigned int du_sync_pins[] = {
2109 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2110 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2111};
2112static const unsigned int du_sync_mux[] = {
2113 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2114};
2115static const unsigned int du_oddf_pins[] = {
2116 /* EXDISP/EXODDF/EXCDE */
2117 RCAR_GP_PIN(2, 2),
2118};
2119static const unsigned int du_oddf_mux[] = {
2120 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2121};
2122static const unsigned int du_cde_pins[] = {
2123 /* CDE */
2124 RCAR_GP_PIN(2, 0),
2125};
2126static const unsigned int du_cde_mux[] = {
2127 DU_CDE_MARK,
2128};
2129static const unsigned int du_disp_pins[] = {
2130 /* DISP */
2131 RCAR_GP_PIN(2, 1),
2132};
2133static const unsigned int du_disp_mux[] = {
2134 DU_DISP_MARK,
2135};
2136
2137/* - HSCIF0 ----------------------------------------------------------------- */
2138static const unsigned int hscif0_data_pins[] = {
2139 /* RX, TX */
2140 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2141};
2142static const unsigned int hscif0_data_mux[] = {
2143 HRX0_MARK, HTX0_MARK,
2144};
2145static const unsigned int hscif0_clk_pins[] = {
2146 /* SCK */
2147 RCAR_GP_PIN(5, 12),
2148};
2149static const unsigned int hscif0_clk_mux[] = {
2150 HSCK0_MARK,
2151};
2152static const unsigned int hscif0_ctrl_pins[] = {
2153 /* RTS, CTS */
2154 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2155};
2156static const unsigned int hscif0_ctrl_mux[] = {
2157 HRTS0_N_MARK, HCTS0_N_MARK,
2158};
2159/* - HSCIF1 ----------------------------------------------------------------- */
2160static const unsigned int hscif1_data_a_pins[] = {
2161 /* RX, TX */
2162 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2163};
2164static const unsigned int hscif1_data_a_mux[] = {
2165 HRX1_A_MARK, HTX1_A_MARK,
2166};
2167static const unsigned int hscif1_clk_a_pins[] = {
2168 /* SCK */
2169 RCAR_GP_PIN(6, 21),
2170};
2171static const unsigned int hscif1_clk_a_mux[] = {
2172 HSCK1_A_MARK,
2173};
2174static const unsigned int hscif1_ctrl_a_pins[] = {
2175 /* RTS, CTS */
2176 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2177};
2178static const unsigned int hscif1_ctrl_a_mux[] = {
2179 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2180};
2181
2182static const unsigned int hscif1_data_b_pins[] = {
2183 /* RX, TX */
2184 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2185};
2186static const unsigned int hscif1_data_b_mux[] = {
2187 HRX1_B_MARK, HTX1_B_MARK,
2188};
2189static const unsigned int hscif1_clk_b_pins[] = {
2190 /* SCK */
2191 RCAR_GP_PIN(5, 0),
2192};
2193static const unsigned int hscif1_clk_b_mux[] = {
2194 HSCK1_B_MARK,
2195};
2196static const unsigned int hscif1_ctrl_b_pins[] = {
2197 /* RTS, CTS */
2198 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2199};
2200static const unsigned int hscif1_ctrl_b_mux[] = {
2201 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2202};
2203/* - HSCIF2 ----------------------------------------------------------------- */
2204static const unsigned int hscif2_data_a_pins[] = {
2205 /* RX, TX */
2206 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2207};
2208static const unsigned int hscif2_data_a_mux[] = {
2209 HRX2_A_MARK, HTX2_A_MARK,
2210};
2211static const unsigned int hscif2_clk_a_pins[] = {
2212 /* SCK */
2213 RCAR_GP_PIN(6, 10),
2214};
2215static const unsigned int hscif2_clk_a_mux[] = {
2216 HSCK2_A_MARK,
2217};
2218static const unsigned int hscif2_ctrl_a_pins[] = {
2219 /* RTS, CTS */
2220 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2221};
2222static const unsigned int hscif2_ctrl_a_mux[] = {
2223 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2224};
2225
2226static const unsigned int hscif2_data_b_pins[] = {
2227 /* RX, TX */
2228 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2229};
2230static const unsigned int hscif2_data_b_mux[] = {
2231 HRX2_B_MARK, HTX2_B_MARK,
2232};
2233static const unsigned int hscif2_clk_b_pins[] = {
2234 /* SCK */
2235 RCAR_GP_PIN(6, 21),
2236};
2237static const unsigned int hscif2_clk_b_mux[] = {
2238 HSCK2_B_MARK,
2239};
2240static const unsigned int hscif2_ctrl_b_pins[] = {
2241 /* RTS, CTS */
2242 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2243};
2244static const unsigned int hscif2_ctrl_b_mux[] = {
2245 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2246};
2247
2248static const unsigned int hscif2_data_c_pins[] = {
2249 /* RX, TX */
2250 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2251};
2252static const unsigned int hscif2_data_c_mux[] = {
2253 HRX2_C_MARK, HTX2_C_MARK,
2254};
2255static const unsigned int hscif2_clk_c_pins[] = {
2256 /* SCK */
2257 RCAR_GP_PIN(6, 24),
2258};
2259static const unsigned int hscif2_clk_c_mux[] = {
2260 HSCK2_C_MARK,
2261};
2262static const unsigned int hscif2_ctrl_c_pins[] = {
2263 /* RTS, CTS */
2264 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2265};
2266static const unsigned int hscif2_ctrl_c_mux[] = {
2267 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2268};
2269/* - HSCIF3 ----------------------------------------------------------------- */
2270static const unsigned int hscif3_data_a_pins[] = {
2271 /* RX, TX */
2272 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2273};
2274static const unsigned int hscif3_data_a_mux[] = {
2275 HRX3_A_MARK, HTX3_A_MARK,
2276};
2277static const unsigned int hscif3_clk_pins[] = {
2278 /* SCK */
2279 RCAR_GP_PIN(1, 22),
2280};
2281static const unsigned int hscif3_clk_mux[] = {
2282 HSCK3_MARK,
2283};
2284static const unsigned int hscif3_ctrl_pins[] = {
2285 /* RTS, CTS */
2286 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2287};
2288static const unsigned int hscif3_ctrl_mux[] = {
2289 HRTS3_N_MARK, HCTS3_N_MARK,
2290};
2291
2292static const unsigned int hscif3_data_b_pins[] = {
2293 /* RX, TX */
2294 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2295};
2296static const unsigned int hscif3_data_b_mux[] = {
2297 HRX3_B_MARK, HTX3_B_MARK,
2298};
2299static const unsigned int hscif3_data_c_pins[] = {
2300 /* RX, TX */
2301 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2302};
2303static const unsigned int hscif3_data_c_mux[] = {
2304 HRX3_C_MARK, HTX3_C_MARK,
2305};
2306static const unsigned int hscif3_data_d_pins[] = {
2307 /* RX, TX */
2308 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2309};
2310static const unsigned int hscif3_data_d_mux[] = {
2311 HRX3_D_MARK, HTX3_D_MARK,
2312};
2313/* - HSCIF4 ----------------------------------------------------------------- */
2314static const unsigned int hscif4_data_a_pins[] = {
2315 /* RX, TX */
2316 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2317};
2318static const unsigned int hscif4_data_a_mux[] = {
2319 HRX4_A_MARK, HTX4_A_MARK,
2320};
2321static const unsigned int hscif4_clk_pins[] = {
2322 /* SCK */
2323 RCAR_GP_PIN(1, 11),
2324};
2325static const unsigned int hscif4_clk_mux[] = {
2326 HSCK4_MARK,
2327};
2328static const unsigned int hscif4_ctrl_pins[] = {
2329 /* RTS, CTS */
2330 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2331};
2332static const unsigned int hscif4_ctrl_mux[] = {
2333 HRTS4_N_MARK, HCTS4_N_MARK,
2334};
2335
2336static const unsigned int hscif4_data_b_pins[] = {
2337 /* RX, TX */
2338 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2339};
2340static const unsigned int hscif4_data_b_mux[] = {
2341 HRX4_B_MARK, HTX4_B_MARK,
2342};
2343
2344/* - I2C -------------------------------------------------------------------- */
2345static const unsigned int i2c1_a_pins[] = {
2346 /* SDA, SCL */
2347 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2348};
2349static const unsigned int i2c1_a_mux[] = {
2350 SDA1_A_MARK, SCL1_A_MARK,
2351};
2352static const unsigned int i2c1_b_pins[] = {
2353 /* SDA, SCL */
2354 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2355};
2356static const unsigned int i2c1_b_mux[] = {
2357 SDA1_B_MARK, SCL1_B_MARK,
2358};
2359static const unsigned int i2c2_a_pins[] = {
2360 /* SDA, SCL */
2361 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2362};
2363static const unsigned int i2c2_a_mux[] = {
2364 SDA2_A_MARK, SCL2_A_MARK,
2365};
2366static const unsigned int i2c2_b_pins[] = {
2367 /* SDA, SCL */
2368 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2369};
2370static const unsigned int i2c2_b_mux[] = {
2371 SDA2_B_MARK, SCL2_B_MARK,
2372};
2373static const unsigned int i2c6_a_pins[] = {
2374 /* SDA, SCL */
2375 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2376};
2377static const unsigned int i2c6_a_mux[] = {
2378 SDA6_A_MARK, SCL6_A_MARK,
2379};
2380static const unsigned int i2c6_b_pins[] = {
2381 /* SDA, SCL */
2382 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2383};
2384static const unsigned int i2c6_b_mux[] = {
2385 SDA6_B_MARK, SCL6_B_MARK,
2386};
2387static const unsigned int i2c6_c_pins[] = {
2388 /* SDA, SCL */
2389 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2390};
2391static const unsigned int i2c6_c_mux[] = {
2392 SDA6_C_MARK, SCL6_C_MARK,
2393};
2394
2395/* - MSIOF0 ----------------------------------------------------------------- */
2396static const unsigned int msiof0_clk_pins[] = {
2397 /* SCK */
2398 RCAR_GP_PIN(5, 17),
2399};
2400static const unsigned int msiof0_clk_mux[] = {
2401 MSIOF0_SCK_MARK,
2402};
2403static const unsigned int msiof0_sync_pins[] = {
2404 /* SYNC */
2405 RCAR_GP_PIN(5, 18),
2406};
2407static const unsigned int msiof0_sync_mux[] = {
2408 MSIOF0_SYNC_MARK,
2409};
2410static const unsigned int msiof0_ss1_pins[] = {
2411 /* SS1 */
2412 RCAR_GP_PIN(5, 19),
2413};
2414static const unsigned int msiof0_ss1_mux[] = {
2415 MSIOF0_SS1_MARK,
2416};
2417static const unsigned int msiof0_ss2_pins[] = {
2418 /* SS2 */
2419 RCAR_GP_PIN(5, 21),
2420};
2421static const unsigned int msiof0_ss2_mux[] = {
2422 MSIOF0_SS2_MARK,
2423};
2424static const unsigned int msiof0_txd_pins[] = {
2425 /* TXD */
2426 RCAR_GP_PIN(5, 20),
2427};
2428static const unsigned int msiof0_txd_mux[] = {
2429 MSIOF0_TXD_MARK,
2430};
2431static const unsigned int msiof0_rxd_pins[] = {
2432 /* RXD */
2433 RCAR_GP_PIN(5, 22),
2434};
2435static const unsigned int msiof0_rxd_mux[] = {
2436 MSIOF0_RXD_MARK,
2437};
2438/* - MSIOF1 ----------------------------------------------------------------- */
2439static const unsigned int msiof1_clk_a_pins[] = {
2440 /* SCK */
2441 RCAR_GP_PIN(6, 8),
2442};
2443static const unsigned int msiof1_clk_a_mux[] = {
2444 MSIOF1_SCK_A_MARK,
2445};
2446static const unsigned int msiof1_sync_a_pins[] = {
2447 /* SYNC */
2448 RCAR_GP_PIN(6, 9),
2449};
2450static const unsigned int msiof1_sync_a_mux[] = {
2451 MSIOF1_SYNC_A_MARK,
2452};
2453static const unsigned int msiof1_ss1_a_pins[] = {
2454 /* SS1 */
2455 RCAR_GP_PIN(6, 5),
2456};
2457static const unsigned int msiof1_ss1_a_mux[] = {
2458 MSIOF1_SS1_A_MARK,
2459};
2460static const unsigned int msiof1_ss2_a_pins[] = {
2461 /* SS2 */
2462 RCAR_GP_PIN(6, 6),
2463};
2464static const unsigned int msiof1_ss2_a_mux[] = {
2465 MSIOF1_SS2_A_MARK,
2466};
2467static const unsigned int msiof1_txd_a_pins[] = {
2468 /* TXD */
2469 RCAR_GP_PIN(6, 7),
2470};
2471static const unsigned int msiof1_txd_a_mux[] = {
2472 MSIOF1_TXD_A_MARK,
2473};
2474static const unsigned int msiof1_rxd_a_pins[] = {
2475 /* RXD */
2476 RCAR_GP_PIN(6, 10),
2477};
2478static const unsigned int msiof1_rxd_a_mux[] = {
2479 MSIOF1_RXD_A_MARK,
2480};
2481static const unsigned int msiof1_clk_b_pins[] = {
2482 /* SCK */
2483 RCAR_GP_PIN(5, 9),
2484};
2485static const unsigned int msiof1_clk_b_mux[] = {
2486 MSIOF1_SCK_B_MARK,
2487};
2488static const unsigned int msiof1_sync_b_pins[] = {
2489 /* SYNC */
2490 RCAR_GP_PIN(5, 3),
2491};
2492static const unsigned int msiof1_sync_b_mux[] = {
2493 MSIOF1_SYNC_B_MARK,
2494};
2495static const unsigned int msiof1_ss1_b_pins[] = {
2496 /* SS1 */
2497 RCAR_GP_PIN(5, 4),
2498};
2499static const unsigned int msiof1_ss1_b_mux[] = {
2500 MSIOF1_SS1_B_MARK,
2501};
2502static const unsigned int msiof1_ss2_b_pins[] = {
2503 /* SS2 */
2504 RCAR_GP_PIN(5, 0),
2505};
2506static const unsigned int msiof1_ss2_b_mux[] = {
2507 MSIOF1_SS2_B_MARK,
2508};
2509static const unsigned int msiof1_txd_b_pins[] = {
2510 /* TXD */
2511 RCAR_GP_PIN(5, 8),
2512};
2513static const unsigned int msiof1_txd_b_mux[] = {
2514 MSIOF1_TXD_B_MARK,
2515};
2516static const unsigned int msiof1_rxd_b_pins[] = {
2517 /* RXD */
2518 RCAR_GP_PIN(5, 7),
2519};
2520static const unsigned int msiof1_rxd_b_mux[] = {
2521 MSIOF1_RXD_B_MARK,
2522};
2523static const unsigned int msiof1_clk_c_pins[] = {
2524 /* SCK */
2525 RCAR_GP_PIN(6, 17),
2526};
2527static const unsigned int msiof1_clk_c_mux[] = {
2528 MSIOF1_SCK_C_MARK,
2529};
2530static const unsigned int msiof1_sync_c_pins[] = {
2531 /* SYNC */
2532 RCAR_GP_PIN(6, 18),
2533};
2534static const unsigned int msiof1_sync_c_mux[] = {
2535 MSIOF1_SYNC_C_MARK,
2536};
2537static const unsigned int msiof1_ss1_c_pins[] = {
2538 /* SS1 */
2539 RCAR_GP_PIN(6, 21),
2540};
2541static const unsigned int msiof1_ss1_c_mux[] = {
2542 MSIOF1_SS1_C_MARK,
2543};
2544static const unsigned int msiof1_ss2_c_pins[] = {
2545 /* SS2 */
2546 RCAR_GP_PIN(6, 27),
2547};
2548static const unsigned int msiof1_ss2_c_mux[] = {
2549 MSIOF1_SS2_C_MARK,
2550};
2551static const unsigned int msiof1_txd_c_pins[] = {
2552 /* TXD */
2553 RCAR_GP_PIN(6, 20),
2554};
2555static const unsigned int msiof1_txd_c_mux[] = {
2556 MSIOF1_TXD_C_MARK,
2557};
2558static const unsigned int msiof1_rxd_c_pins[] = {
2559 /* RXD */
2560 RCAR_GP_PIN(6, 19),
2561};
2562static const unsigned int msiof1_rxd_c_mux[] = {
2563 MSIOF1_RXD_C_MARK,
2564};
2565static const unsigned int msiof1_clk_d_pins[] = {
2566 /* SCK */
2567 RCAR_GP_PIN(5, 12),
2568};
2569static const unsigned int msiof1_clk_d_mux[] = {
2570 MSIOF1_SCK_D_MARK,
2571};
2572static const unsigned int msiof1_sync_d_pins[] = {
2573 /* SYNC */
2574 RCAR_GP_PIN(5, 15),
2575};
2576static const unsigned int msiof1_sync_d_mux[] = {
2577 MSIOF1_SYNC_D_MARK,
2578};
2579static const unsigned int msiof1_ss1_d_pins[] = {
2580 /* SS1 */
2581 RCAR_GP_PIN(5, 16),
2582};
2583static const unsigned int msiof1_ss1_d_mux[] = {
2584 MSIOF1_SS1_D_MARK,
2585};
2586static const unsigned int msiof1_ss2_d_pins[] = {
2587 /* SS2 */
2588 RCAR_GP_PIN(5, 21),
2589};
2590static const unsigned int msiof1_ss2_d_mux[] = {
2591 MSIOF1_SS2_D_MARK,
2592};
2593static const unsigned int msiof1_txd_d_pins[] = {
2594 /* TXD */
2595 RCAR_GP_PIN(5, 14),
2596};
2597static const unsigned int msiof1_txd_d_mux[] = {
2598 MSIOF1_TXD_D_MARK,
2599};
2600static const unsigned int msiof1_rxd_d_pins[] = {
2601 /* RXD */
2602 RCAR_GP_PIN(5, 13),
2603};
2604static const unsigned int msiof1_rxd_d_mux[] = {
2605 MSIOF1_RXD_D_MARK,
2606};
2607static const unsigned int msiof1_clk_e_pins[] = {
2608 /* SCK */
2609 RCAR_GP_PIN(3, 0),
2610};
2611static const unsigned int msiof1_clk_e_mux[] = {
2612 MSIOF1_SCK_E_MARK,
2613};
2614static const unsigned int msiof1_sync_e_pins[] = {
2615 /* SYNC */
2616 RCAR_GP_PIN(3, 1),
2617};
2618static const unsigned int msiof1_sync_e_mux[] = {
2619 MSIOF1_SYNC_E_MARK,
2620};
2621static const unsigned int msiof1_ss1_e_pins[] = {
2622 /* SS1 */
2623 RCAR_GP_PIN(3, 4),
2624};
2625static const unsigned int msiof1_ss1_e_mux[] = {
2626 MSIOF1_SS1_E_MARK,
2627};
2628static const unsigned int msiof1_ss2_e_pins[] = {
2629 /* SS2 */
2630 RCAR_GP_PIN(3, 5),
2631};
2632static const unsigned int msiof1_ss2_e_mux[] = {
2633 MSIOF1_SS2_E_MARK,
2634};
2635static const unsigned int msiof1_txd_e_pins[] = {
2636 /* TXD */
2637 RCAR_GP_PIN(3, 3),
2638};
2639static const unsigned int msiof1_txd_e_mux[] = {
2640 MSIOF1_TXD_E_MARK,
2641};
2642static const unsigned int msiof1_rxd_e_pins[] = {
2643 /* RXD */
2644 RCAR_GP_PIN(3, 2),
2645};
2646static const unsigned int msiof1_rxd_e_mux[] = {
2647 MSIOF1_RXD_E_MARK,
2648};
2649static const unsigned int msiof1_clk_f_pins[] = {
2650 /* SCK */
2651 RCAR_GP_PIN(5, 23),
2652};
2653static const unsigned int msiof1_clk_f_mux[] = {
2654 MSIOF1_SCK_F_MARK,
2655};
2656static const unsigned int msiof1_sync_f_pins[] = {
2657 /* SYNC */
2658 RCAR_GP_PIN(5, 24),
2659};
2660static const unsigned int msiof1_sync_f_mux[] = {
2661 MSIOF1_SYNC_F_MARK,
2662};
2663static const unsigned int msiof1_ss1_f_pins[] = {
2664 /* SS1 */
2665 RCAR_GP_PIN(6, 1),
2666};
2667static const unsigned int msiof1_ss1_f_mux[] = {
2668 MSIOF1_SS1_F_MARK,
2669};
2670static const unsigned int msiof1_ss2_f_pins[] = {
2671 /* SS2 */
2672 RCAR_GP_PIN(6, 2),
2673};
2674static const unsigned int msiof1_ss2_f_mux[] = {
2675 MSIOF1_SS2_F_MARK,
2676};
2677static const unsigned int msiof1_txd_f_pins[] = {
2678 /* TXD */
2679 RCAR_GP_PIN(6, 0),
2680};
2681static const unsigned int msiof1_txd_f_mux[] = {
2682 MSIOF1_TXD_F_MARK,
2683};
2684static const unsigned int msiof1_rxd_f_pins[] = {
2685 /* RXD */
2686 RCAR_GP_PIN(5, 25),
2687};
2688static const unsigned int msiof1_rxd_f_mux[] = {
2689 MSIOF1_RXD_F_MARK,
2690};
2691static const unsigned int msiof1_clk_g_pins[] = {
2692 /* SCK */
2693 RCAR_GP_PIN(3, 6),
2694};
2695static const unsigned int msiof1_clk_g_mux[] = {
2696 MSIOF1_SCK_G_MARK,
2697};
2698static const unsigned int msiof1_sync_g_pins[] = {
2699 /* SYNC */
2700 RCAR_GP_PIN(3, 7),
2701};
2702static const unsigned int msiof1_sync_g_mux[] = {
2703 MSIOF1_SYNC_G_MARK,
2704};
2705static const unsigned int msiof1_ss1_g_pins[] = {
2706 /* SS1 */
2707 RCAR_GP_PIN(3, 10),
2708};
2709static const unsigned int msiof1_ss1_g_mux[] = {
2710 MSIOF1_SS1_G_MARK,
2711};
2712static const unsigned int msiof1_ss2_g_pins[] = {
2713 /* SS2 */
2714 RCAR_GP_PIN(3, 11),
2715};
2716static const unsigned int msiof1_ss2_g_mux[] = {
2717 MSIOF1_SS2_G_MARK,
2718};
2719static const unsigned int msiof1_txd_g_pins[] = {
2720 /* TXD */
2721 RCAR_GP_PIN(3, 9),
2722};
2723static const unsigned int msiof1_txd_g_mux[] = {
2724 MSIOF1_TXD_G_MARK,
2725};
2726static const unsigned int msiof1_rxd_g_pins[] = {
2727 /* RXD */
2728 RCAR_GP_PIN(3, 8),
2729};
2730static const unsigned int msiof1_rxd_g_mux[] = {
2731 MSIOF1_RXD_G_MARK,
2732};
2733/* - MSIOF2 ----------------------------------------------------------------- */
2734static const unsigned int msiof2_clk_a_pins[] = {
2735 /* SCK */
2736 RCAR_GP_PIN(1, 9),
2737};
2738static const unsigned int msiof2_clk_a_mux[] = {
2739 MSIOF2_SCK_A_MARK,
2740};
2741static const unsigned int msiof2_sync_a_pins[] = {
2742 /* SYNC */
2743 RCAR_GP_PIN(1, 8),
2744};
2745static const unsigned int msiof2_sync_a_mux[] = {
2746 MSIOF2_SYNC_A_MARK,
2747};
2748static const unsigned int msiof2_ss1_a_pins[] = {
2749 /* SS1 */
2750 RCAR_GP_PIN(1, 6),
2751};
2752static const unsigned int msiof2_ss1_a_mux[] = {
2753 MSIOF2_SS1_A_MARK,
2754};
2755static const unsigned int msiof2_ss2_a_pins[] = {
2756 /* SS2 */
2757 RCAR_GP_PIN(1, 7),
2758};
2759static const unsigned int msiof2_ss2_a_mux[] = {
2760 MSIOF2_SS2_A_MARK,
2761};
2762static const unsigned int msiof2_txd_a_pins[] = {
2763 /* TXD */
2764 RCAR_GP_PIN(1, 11),
2765};
2766static const unsigned int msiof2_txd_a_mux[] = {
2767 MSIOF2_TXD_A_MARK,
2768};
2769static const unsigned int msiof2_rxd_a_pins[] = {
2770 /* RXD */
2771 RCAR_GP_PIN(1, 10),
2772};
2773static const unsigned int msiof2_rxd_a_mux[] = {
2774 MSIOF2_RXD_A_MARK,
2775};
2776static const unsigned int msiof2_clk_b_pins[] = {
2777 /* SCK */
2778 RCAR_GP_PIN(0, 4),
2779};
2780static const unsigned int msiof2_clk_b_mux[] = {
2781 MSIOF2_SCK_B_MARK,
2782};
2783static const unsigned int msiof2_sync_b_pins[] = {
2784 /* SYNC */
2785 RCAR_GP_PIN(0, 5),
2786};
2787static const unsigned int msiof2_sync_b_mux[] = {
2788 MSIOF2_SYNC_B_MARK,
2789};
2790static const unsigned int msiof2_ss1_b_pins[] = {
2791 /* SS1 */
2792 RCAR_GP_PIN(0, 0),
2793};
2794static const unsigned int msiof2_ss1_b_mux[] = {
2795 MSIOF2_SS1_B_MARK,
2796};
2797static const unsigned int msiof2_ss2_b_pins[] = {
2798 /* SS2 */
2799 RCAR_GP_PIN(0, 1),
2800};
2801static const unsigned int msiof2_ss2_b_mux[] = {
2802 MSIOF2_SS2_B_MARK,
2803};
2804static const unsigned int msiof2_txd_b_pins[] = {
2805 /* TXD */
2806 RCAR_GP_PIN(0, 7),
2807};
2808static const unsigned int msiof2_txd_b_mux[] = {
2809 MSIOF2_TXD_B_MARK,
2810};
2811static const unsigned int msiof2_rxd_b_pins[] = {
2812 /* RXD */
2813 RCAR_GP_PIN(0, 6),
2814};
2815static const unsigned int msiof2_rxd_b_mux[] = {
2816 MSIOF2_RXD_B_MARK,
2817};
2818static const unsigned int msiof2_clk_c_pins[] = {
2819 /* SCK */
2820 RCAR_GP_PIN(2, 12),
2821};
2822static const unsigned int msiof2_clk_c_mux[] = {
2823 MSIOF2_SCK_C_MARK,
2824};
2825static const unsigned int msiof2_sync_c_pins[] = {
2826 /* SYNC */
2827 RCAR_GP_PIN(2, 11),
2828};
2829static const unsigned int msiof2_sync_c_mux[] = {
2830 MSIOF2_SYNC_C_MARK,
2831};
2832static const unsigned int msiof2_ss1_c_pins[] = {
2833 /* SS1 */
2834 RCAR_GP_PIN(2, 10),
2835};
2836static const unsigned int msiof2_ss1_c_mux[] = {
2837 MSIOF2_SS1_C_MARK,
2838};
2839static const unsigned int msiof2_ss2_c_pins[] = {
2840 /* SS2 */
2841 RCAR_GP_PIN(2, 9),
2842};
2843static const unsigned int msiof2_ss2_c_mux[] = {
2844 MSIOF2_SS2_C_MARK,
2845};
2846static const unsigned int msiof2_txd_c_pins[] = {
2847 /* TXD */
2848 RCAR_GP_PIN(2, 14),
2849};
2850static const unsigned int msiof2_txd_c_mux[] = {
2851 MSIOF2_TXD_C_MARK,
2852};
2853static const unsigned int msiof2_rxd_c_pins[] = {
2854 /* RXD */
2855 RCAR_GP_PIN(2, 13),
2856};
2857static const unsigned int msiof2_rxd_c_mux[] = {
2858 MSIOF2_RXD_C_MARK,
2859};
2860static const unsigned int msiof2_clk_d_pins[] = {
2861 /* SCK */
2862 RCAR_GP_PIN(0, 8),
2863};
2864static const unsigned int msiof2_clk_d_mux[] = {
2865 MSIOF2_SCK_D_MARK,
2866};
2867static const unsigned int msiof2_sync_d_pins[] = {
2868 /* SYNC */
2869 RCAR_GP_PIN(0, 9),
2870};
2871static const unsigned int msiof2_sync_d_mux[] = {
2872 MSIOF2_SYNC_D_MARK,
2873};
2874static const unsigned int msiof2_ss1_d_pins[] = {
2875 /* SS1 */
2876 RCAR_GP_PIN(0, 12),
2877};
2878static const unsigned int msiof2_ss1_d_mux[] = {
2879 MSIOF2_SS1_D_MARK,
2880};
2881static const unsigned int msiof2_ss2_d_pins[] = {
2882 /* SS2 */
2883 RCAR_GP_PIN(0, 13),
2884};
2885static const unsigned int msiof2_ss2_d_mux[] = {
2886 MSIOF2_SS2_D_MARK,
2887};
2888static const unsigned int msiof2_txd_d_pins[] = {
2889 /* TXD */
2890 RCAR_GP_PIN(0, 11),
2891};
2892static const unsigned int msiof2_txd_d_mux[] = {
2893 MSIOF2_TXD_D_MARK,
2894};
2895static const unsigned int msiof2_rxd_d_pins[] = {
2896 /* RXD */
2897 RCAR_GP_PIN(0, 10),
2898};
2899static const unsigned int msiof2_rxd_d_mux[] = {
2900 MSIOF2_RXD_D_MARK,
2901};
2902/* - MSIOF3 ----------------------------------------------------------------- */
2903static const unsigned int msiof3_clk_a_pins[] = {
2904 /* SCK */
2905 RCAR_GP_PIN(0, 0),
2906};
2907static const unsigned int msiof3_clk_a_mux[] = {
2908 MSIOF3_SCK_A_MARK,
2909};
2910static const unsigned int msiof3_sync_a_pins[] = {
2911 /* SYNC */
2912 RCAR_GP_PIN(0, 1),
2913};
2914static const unsigned int msiof3_sync_a_mux[] = {
2915 MSIOF3_SYNC_A_MARK,
2916};
2917static const unsigned int msiof3_ss1_a_pins[] = {
2918 /* SS1 */
2919 RCAR_GP_PIN(0, 14),
2920};
2921static const unsigned int msiof3_ss1_a_mux[] = {
2922 MSIOF3_SS1_A_MARK,
2923};
2924static const unsigned int msiof3_ss2_a_pins[] = {
2925 /* SS2 */
2926 RCAR_GP_PIN(0, 15),
2927};
2928static const unsigned int msiof3_ss2_a_mux[] = {
2929 MSIOF3_SS2_A_MARK,
2930};
2931static const unsigned int msiof3_txd_a_pins[] = {
2932 /* TXD */
2933 RCAR_GP_PIN(0, 3),
2934};
2935static const unsigned int msiof3_txd_a_mux[] = {
2936 MSIOF3_TXD_A_MARK,
2937};
2938static const unsigned int msiof3_rxd_a_pins[] = {
2939 /* RXD */
2940 RCAR_GP_PIN(0, 2),
2941};
2942static const unsigned int msiof3_rxd_a_mux[] = {
2943 MSIOF3_RXD_A_MARK,
2944};
2945static const unsigned int msiof3_clk_b_pins[] = {
2946 /* SCK */
2947 RCAR_GP_PIN(1, 2),
2948};
2949static const unsigned int msiof3_clk_b_mux[] = {
2950 MSIOF3_SCK_B_MARK,
2951};
2952static const unsigned int msiof3_sync_b_pins[] = {
2953 /* SYNC */
2954 RCAR_GP_PIN(1, 0),
2955};
2956static const unsigned int msiof3_sync_b_mux[] = {
2957 MSIOF3_SYNC_B_MARK,
2958};
2959static const unsigned int msiof3_ss1_b_pins[] = {
2960 /* SS1 */
2961 RCAR_GP_PIN(1, 4),
2962};
2963static const unsigned int msiof3_ss1_b_mux[] = {
2964 MSIOF3_SS1_B_MARK,
2965};
2966static const unsigned int msiof3_ss2_b_pins[] = {
2967 /* SS2 */
2968 RCAR_GP_PIN(1, 5),
2969};
2970static const unsigned int msiof3_ss2_b_mux[] = {
2971 MSIOF3_SS2_B_MARK,
2972};
2973static const unsigned int msiof3_txd_b_pins[] = {
2974 /* TXD */
2975 RCAR_GP_PIN(1, 1),
2976};
2977static const unsigned int msiof3_txd_b_mux[] = {
2978 MSIOF3_TXD_B_MARK,
2979};
2980static const unsigned int msiof3_rxd_b_pins[] = {
2981 /* RXD */
2982 RCAR_GP_PIN(1, 3),
2983};
2984static const unsigned int msiof3_rxd_b_mux[] = {
2985 MSIOF3_RXD_B_MARK,
2986};
2987static const unsigned int msiof3_clk_c_pins[] = {
2988 /* SCK */
2989 RCAR_GP_PIN(1, 12),
2990};
2991static const unsigned int msiof3_clk_c_mux[] = {
2992 MSIOF3_SCK_C_MARK,
2993};
2994static const unsigned int msiof3_sync_c_pins[] = {
2995 /* SYNC */
2996 RCAR_GP_PIN(1, 13),
2997};
2998static const unsigned int msiof3_sync_c_mux[] = {
2999 MSIOF3_SYNC_C_MARK,
3000};
3001static const unsigned int msiof3_txd_c_pins[] = {
3002 /* TXD */
3003 RCAR_GP_PIN(1, 15),
3004};
3005static const unsigned int msiof3_txd_c_mux[] = {
3006 MSIOF3_TXD_C_MARK,
3007};
3008static const unsigned int msiof3_rxd_c_pins[] = {
3009 /* RXD */
3010 RCAR_GP_PIN(1, 14),
3011};
3012static const unsigned int msiof3_rxd_c_mux[] = {
3013 MSIOF3_RXD_C_MARK,
3014};
3015static const unsigned int msiof3_clk_d_pins[] = {
3016 /* SCK */
3017 RCAR_GP_PIN(1, 22),
3018};
3019static const unsigned int msiof3_clk_d_mux[] = {
3020 MSIOF3_SCK_D_MARK,
3021};
3022static const unsigned int msiof3_sync_d_pins[] = {
3023 /* SYNC */
3024 RCAR_GP_PIN(1, 23),
3025};
3026static const unsigned int msiof3_sync_d_mux[] = {
3027 MSIOF3_SYNC_D_MARK,
3028};
3029static const unsigned int msiof3_ss1_d_pins[] = {
3030 /* SS1 */
3031 RCAR_GP_PIN(1, 26),
3032};
3033static const unsigned int msiof3_ss1_d_mux[] = {
3034 MSIOF3_SS1_D_MARK,
3035};
3036static const unsigned int msiof3_txd_d_pins[] = {
3037 /* TXD */
3038 RCAR_GP_PIN(1, 25),
3039};
3040static const unsigned int msiof3_txd_d_mux[] = {
3041 MSIOF3_TXD_D_MARK,
3042};
3043static const unsigned int msiof3_rxd_d_pins[] = {
3044 /* RXD */
3045 RCAR_GP_PIN(1, 24),
3046};
3047static const unsigned int msiof3_rxd_d_mux[] = {
3048 MSIOF3_RXD_D_MARK,
3049};
3050
3051static const unsigned int msiof3_clk_e_pins[] = {
3052 /* SCK */
3053 RCAR_GP_PIN(2, 3),
3054};
3055static const unsigned int msiof3_clk_e_mux[] = {
3056 MSIOF3_SCK_E_MARK,
3057};
3058static const unsigned int msiof3_sync_e_pins[] = {
3059 /* SYNC */
3060 RCAR_GP_PIN(2, 2),
3061};
3062static const unsigned int msiof3_sync_e_mux[] = {
3063 MSIOF3_SYNC_E_MARK,
3064};
3065static const unsigned int msiof3_ss1_e_pins[] = {
3066 /* SS1 */
3067 RCAR_GP_PIN(2, 1),
3068};
3069static const unsigned int msiof3_ss1_e_mux[] = {
3070 MSIOF3_SS1_E_MARK,
3071};
3072static const unsigned int msiof3_ss2_e_pins[] = {
3073 /* SS1 */
3074 RCAR_GP_PIN(2, 0),
3075};
3076static const unsigned int msiof3_ss2_e_mux[] = {
3077 MSIOF3_SS2_E_MARK,
3078};
3079static const unsigned int msiof3_txd_e_pins[] = {
3080 /* TXD */
3081 RCAR_GP_PIN(2, 5),
3082};
3083static const unsigned int msiof3_txd_e_mux[] = {
3084 MSIOF3_TXD_E_MARK,
3085};
3086static const unsigned int msiof3_rxd_e_pins[] = {
3087 /* RXD */
3088 RCAR_GP_PIN(2, 4),
3089};
3090static const unsigned int msiof3_rxd_e_mux[] = {
3091 MSIOF3_RXD_E_MARK,
3092};
3093
3094/* - PWM0 --------------------------------------------------------------------*/
3095static const unsigned int pwm0_pins[] = {
3096 /* PWM */
3097 RCAR_GP_PIN(2, 6),
3098};
3099static const unsigned int pwm0_mux[] = {
3100 PWM0_MARK,
3101};
3102/* - PWM1 --------------------------------------------------------------------*/
3103static const unsigned int pwm1_a_pins[] = {
3104 /* PWM */
3105 RCAR_GP_PIN(2, 7),
3106};
3107static const unsigned int pwm1_a_mux[] = {
3108 PWM1_A_MARK,
3109};
3110static const unsigned int pwm1_b_pins[] = {
3111 /* PWM */
3112 RCAR_GP_PIN(1, 8),
3113};
3114static const unsigned int pwm1_b_mux[] = {
3115 PWM1_B_MARK,
3116};
3117/* - PWM2 --------------------------------------------------------------------*/
3118static const unsigned int pwm2_a_pins[] = {
3119 /* PWM */
3120 RCAR_GP_PIN(2, 8),
3121};
3122static const unsigned int pwm2_a_mux[] = {
3123 PWM2_A_MARK,
3124};
3125static const unsigned int pwm2_b_pins[] = {
3126 /* PWM */
3127 RCAR_GP_PIN(1, 11),
3128};
3129static const unsigned int pwm2_b_mux[] = {
3130 PWM2_B_MARK,
3131};
3132/* - PWM3 --------------------------------------------------------------------*/
3133static const unsigned int pwm3_a_pins[] = {
3134 /* PWM */
3135 RCAR_GP_PIN(1, 0),
3136};
3137static const unsigned int pwm3_a_mux[] = {
3138 PWM3_A_MARK,
3139};
3140static const unsigned int pwm3_b_pins[] = {
3141 /* PWM */
3142 RCAR_GP_PIN(2, 2),
3143};
3144static const unsigned int pwm3_b_mux[] = {
3145 PWM3_B_MARK,
3146};
3147/* - PWM4 --------------------------------------------------------------------*/
3148static const unsigned int pwm4_a_pins[] = {
3149 /* PWM */
3150 RCAR_GP_PIN(1, 1),
3151};
3152static const unsigned int pwm4_a_mux[] = {
3153 PWM4_A_MARK,
3154};
3155static const unsigned int pwm4_b_pins[] = {
3156 /* PWM */
3157 RCAR_GP_PIN(2, 3),
3158};
3159static const unsigned int pwm4_b_mux[] = {
3160 PWM4_B_MARK,
3161};
3162/* - PWM5 --------------------------------------------------------------------*/
3163static const unsigned int pwm5_a_pins[] = {
3164 /* PWM */
3165 RCAR_GP_PIN(1, 2),
3166};
3167static const unsigned int pwm5_a_mux[] = {
3168 PWM5_A_MARK,
3169};
3170static const unsigned int pwm5_b_pins[] = {
3171 /* PWM */
3172 RCAR_GP_PIN(2, 4),
3173};
3174static const unsigned int pwm5_b_mux[] = {
3175 PWM5_B_MARK,
3176};
3177/* - PWM6 --------------------------------------------------------------------*/
3178static const unsigned int pwm6_a_pins[] = {
3179 /* PWM */
3180 RCAR_GP_PIN(1, 3),
3181};
3182static const unsigned int pwm6_a_mux[] = {
3183 PWM6_A_MARK,
3184};
3185static const unsigned int pwm6_b_pins[] = {
3186 /* PWM */
3187 RCAR_GP_PIN(2, 5),
3188};
3189static const unsigned int pwm6_b_mux[] = {
3190 PWM6_B_MARK,
3191};
3192
3193/* - SCIF0 ------------------------------------------------------------------ */
3194static const unsigned int scif0_data_pins[] = {
3195 /* RX, TX */
3196 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3197};
3198static const unsigned int scif0_data_mux[] = {
3199 RX0_MARK, TX0_MARK,
3200};
3201static const unsigned int scif0_clk_pins[] = {
3202 /* SCK */
3203 RCAR_GP_PIN(5, 0),
3204};
3205static const unsigned int scif0_clk_mux[] = {
3206 SCK0_MARK,
3207};
3208static const unsigned int scif0_ctrl_pins[] = {
3209 /* RTS, CTS */
3210 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3211};
3212static const unsigned int scif0_ctrl_mux[] = {
3213 RTS0_N_TANS_MARK, CTS0_N_MARK,
3214};
3215/* - SCIF1 ------------------------------------------------------------------ */
3216static const unsigned int scif1_data_a_pins[] = {
3217 /* RX, TX */
3218 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3219};
3220static const unsigned int scif1_data_a_mux[] = {
3221 RX1_A_MARK, TX1_A_MARK,
3222};
3223static const unsigned int scif1_clk_pins[] = {
3224 /* SCK */
3225 RCAR_GP_PIN(6, 21),
3226};
3227static const unsigned int scif1_clk_mux[] = {
3228 SCK1_MARK,
3229};
3230static const unsigned int scif1_ctrl_pins[] = {
3231 /* RTS, CTS */
3232 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3233};
3234static const unsigned int scif1_ctrl_mux[] = {
3235 RTS1_N_TANS_MARK, CTS1_N_MARK,
3236};
3237
3238static const unsigned int scif1_data_b_pins[] = {
3239 /* RX, TX */
3240 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3241};
3242static const unsigned int scif1_data_b_mux[] = {
3243 RX1_B_MARK, TX1_B_MARK,
3244};
3245/* - SCIF2 ------------------------------------------------------------------ */
3246static const unsigned int scif2_data_a_pins[] = {
3247 /* RX, TX */
3248 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3249};
3250static const unsigned int scif2_data_a_mux[] = {
3251 RX2_A_MARK, TX2_A_MARK,
3252};
3253static const unsigned int scif2_clk_pins[] = {
3254 /* SCK */
3255 RCAR_GP_PIN(5, 9),
3256};
3257static const unsigned int scif2_clk_mux[] = {
3258 SCK2_MARK,
3259};
3260static const unsigned int scif2_data_b_pins[] = {
3261 /* RX, TX */
3262 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3263};
3264static const unsigned int scif2_data_b_mux[] = {
3265 RX2_B_MARK, TX2_B_MARK,
3266};
3267/* - SCIF3 ------------------------------------------------------------------ */
3268static const unsigned int scif3_data_a_pins[] = {
3269 /* RX, TX */
3270 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3271};
3272static const unsigned int scif3_data_a_mux[] = {
3273 RX3_A_MARK, TX3_A_MARK,
3274};
3275static const unsigned int scif3_clk_pins[] = {
3276 /* SCK */
3277 RCAR_GP_PIN(1, 22),
3278};
3279static const unsigned int scif3_clk_mux[] = {
3280 SCK3_MARK,
3281};
3282static const unsigned int scif3_ctrl_pins[] = {
3283 /* RTS, CTS */
3284 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3285};
3286static const unsigned int scif3_ctrl_mux[] = {
3287 RTS3_N_TANS_MARK, CTS3_N_MARK,
3288};
3289static const unsigned int scif3_data_b_pins[] = {
3290 /* RX, TX */
3291 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3292};
3293static const unsigned int scif3_data_b_mux[] = {
3294 RX3_B_MARK, TX3_B_MARK,
3295};
3296/* - SCIF4 ------------------------------------------------------------------ */
3297static const unsigned int scif4_data_a_pins[] = {
3298 /* RX, TX */
3299 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3300};
3301static const unsigned int scif4_data_a_mux[] = {
3302 RX4_A_MARK, TX4_A_MARK,
3303};
3304static const unsigned int scif4_clk_a_pins[] = {
3305 /* SCK */
3306 RCAR_GP_PIN(2, 10),
3307};
3308static const unsigned int scif4_clk_a_mux[] = {
3309 SCK4_A_MARK,
3310};
3311static const unsigned int scif4_ctrl_a_pins[] = {
3312 /* RTS, CTS */
3313 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3314};
3315static const unsigned int scif4_ctrl_a_mux[] = {
3316 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3317};
3318static const unsigned int scif4_data_b_pins[] = {
3319 /* RX, TX */
3320 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3321};
3322static const unsigned int scif4_data_b_mux[] = {
3323 RX4_B_MARK, TX4_B_MARK,
3324};
3325static const unsigned int scif4_clk_b_pins[] = {
3326 /* SCK */
3327 RCAR_GP_PIN(1, 5),
3328};
3329static const unsigned int scif4_clk_b_mux[] = {
3330 SCK4_B_MARK,
3331};
3332static const unsigned int scif4_ctrl_b_pins[] = {
3333 /* RTS, CTS */
3334 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3335};
3336static const unsigned int scif4_ctrl_b_mux[] = {
3337 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3338};
3339static const unsigned int scif4_data_c_pins[] = {
3340 /* RX, TX */
3341 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3342};
3343static const unsigned int scif4_data_c_mux[] = {
3344 RX4_C_MARK, TX4_C_MARK,
3345};
3346static const unsigned int scif4_clk_c_pins[] = {
3347 /* SCK */
3348 RCAR_GP_PIN(0, 8),
3349};
3350static const unsigned int scif4_clk_c_mux[] = {
3351 SCK4_C_MARK,
3352};
3353static const unsigned int scif4_ctrl_c_pins[] = {
3354 /* RTS, CTS */
3355 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3356};
3357static const unsigned int scif4_ctrl_c_mux[] = {
3358 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3359};
3360/* - SCIF5 ------------------------------------------------------------------ */
3361static const unsigned int scif5_data_a_pins[] = {
3362 /* RX, TX */
3363 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3364};
3365static const unsigned int scif5_data_a_mux[] = {
3366 RX5_A_MARK, TX5_A_MARK,
3367};
3368static const unsigned int scif5_clk_a_pins[] = {
3369 /* SCK */
3370 RCAR_GP_PIN(6, 21),
3371};
3372static const unsigned int scif5_clk_a_mux[] = {
3373 SCK5_A_MARK,
3374};
3375
3376static const unsigned int scif5_data_b_pins[] = {
3377 /* RX, TX */
3378 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3379};
3380static const unsigned int scif5_data_b_mux[] = {
3381 RX5_B_MARK, TX5_B_MARK,
3382};
3383static const unsigned int scif5_clk_b_pins[] = {
3384 /* SCK */
3385 RCAR_GP_PIN(5, 0),
3386};
3387static const unsigned int scif5_clk_b_mux[] = {
3388 SCK5_B_MARK,
3389};
3390
3391/* - SCIF Clock ------------------------------------------------------------- */
3392static const unsigned int scif_clk_a_pins[] = {
3393 /* SCIF_CLK */
3394 RCAR_GP_PIN(6, 23),
3395};
3396static const unsigned int scif_clk_a_mux[] = {
3397 SCIF_CLK_A_MARK,
3398};
3399static const unsigned int scif_clk_b_pins[] = {
3400 /* SCIF_CLK */
3401 RCAR_GP_PIN(5, 9),
3402};
3403static const unsigned int scif_clk_b_mux[] = {
3404 SCIF_CLK_B_MARK,
3405};
3406
3407/* - SDHI0 ------------------------------------------------------------------ */
3408static const unsigned int sdhi0_data1_pins[] = {
3409 /* D0 */
3410 RCAR_GP_PIN(3, 2),
3411};
3412static const unsigned int sdhi0_data1_mux[] = {
3413 SD0_DAT0_MARK,
3414};
3415static const unsigned int sdhi0_data4_pins[] = {
3416 /* D[0:3] */
3417 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3418 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3419};
3420static const unsigned int sdhi0_data4_mux[] = {
3421 SD0_DAT0_MARK, SD0_DAT1_MARK,
3422 SD0_DAT2_MARK, SD0_DAT3_MARK,
3423};
3424static const unsigned int sdhi0_ctrl_pins[] = {
3425 /* CLK, CMD */
3426 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3427};
3428static const unsigned int sdhi0_ctrl_mux[] = {
3429 SD0_CLK_MARK, SD0_CMD_MARK,
3430};
3431static const unsigned int sdhi0_cd_pins[] = {
3432 /* CD */
3433 RCAR_GP_PIN(3, 12),
3434};
3435static const unsigned int sdhi0_cd_mux[] = {
3436 SD0_CD_MARK,
3437};
3438static const unsigned int sdhi0_wp_pins[] = {
3439 /* WP */
3440 RCAR_GP_PIN(3, 13),
3441};
3442static const unsigned int sdhi0_wp_mux[] = {
3443 SD0_WP_MARK,
3444};
3445/* - SDHI1 ------------------------------------------------------------------ */
3446static const unsigned int sdhi1_data1_pins[] = {
3447 /* D0 */
3448 RCAR_GP_PIN(3, 8),
3449};
3450static const unsigned int sdhi1_data1_mux[] = {
3451 SD1_DAT0_MARK,
3452};
3453static const unsigned int sdhi1_data4_pins[] = {
3454 /* D[0:3] */
3455 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3456 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3457};
3458static const unsigned int sdhi1_data4_mux[] = {
3459 SD1_DAT0_MARK, SD1_DAT1_MARK,
3460 SD1_DAT2_MARK, SD1_DAT3_MARK,
3461};
3462static const unsigned int sdhi1_ctrl_pins[] = {
3463 /* CLK, CMD */
3464 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3465};
3466static const unsigned int sdhi1_ctrl_mux[] = {
3467 SD1_CLK_MARK, SD1_CMD_MARK,
3468};
3469static const unsigned int sdhi1_cd_pins[] = {
3470 /* CD */
3471 RCAR_GP_PIN(3, 14),
3472};
3473static const unsigned int sdhi1_cd_mux[] = {
3474 SD1_CD_MARK,
3475};
3476static const unsigned int sdhi1_wp_pins[] = {
3477 /* WP */
3478 RCAR_GP_PIN(3, 15),
3479};
3480static const unsigned int sdhi1_wp_mux[] = {
3481 SD1_WP_MARK,
3482};
3483/* - SDHI2 ------------------------------------------------------------------ */
3484static const unsigned int sdhi2_data1_pins[] = {
3485 /* D0 */
3486 RCAR_GP_PIN(4, 2),
3487};
3488static const unsigned int sdhi2_data1_mux[] = {
3489 SD2_DAT0_MARK,
3490};
3491static const unsigned int sdhi2_data4_pins[] = {
3492 /* D[0:3] */
3493 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3494 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3495};
3496static const unsigned int sdhi2_data4_mux[] = {
3497 SD2_DAT0_MARK, SD2_DAT1_MARK,
3498 SD2_DAT2_MARK, SD2_DAT3_MARK,
3499};
3500static const unsigned int sdhi2_data8_pins[] = {
3501 /* D[0:7] */
3502 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3503 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3504 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3505 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3506};
3507static const unsigned int sdhi2_data8_mux[] = {
3508 SD2_DAT0_MARK, SD2_DAT1_MARK,
3509 SD2_DAT2_MARK, SD2_DAT3_MARK,
3510 SD2_DAT4_MARK, SD2_DAT5_MARK,
3511 SD2_DAT6_MARK, SD2_DAT7_MARK,
3512};
3513static const unsigned int sdhi2_ctrl_pins[] = {
3514 /* CLK, CMD */
3515 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3516};
3517static const unsigned int sdhi2_ctrl_mux[] = {
3518 SD2_CLK_MARK, SD2_CMD_MARK,
3519};
3520static const unsigned int sdhi2_cd_a_pins[] = {
3521 /* CD */
3522 RCAR_GP_PIN(4, 13),
3523};
3524static const unsigned int sdhi2_cd_a_mux[] = {
3525 SD2_CD_A_MARK,
3526};
3527static const unsigned int sdhi2_cd_b_pins[] = {
3528 /* CD */
3529 RCAR_GP_PIN(5, 10),
3530};
3531static const unsigned int sdhi2_cd_b_mux[] = {
3532 SD2_CD_B_MARK,
3533};
3534static const unsigned int sdhi2_wp_a_pins[] = {
3535 /* WP */
3536 RCAR_GP_PIN(4, 14),
3537};
3538static const unsigned int sdhi2_wp_a_mux[] = {
3539 SD2_WP_A_MARK,
3540};
3541static const unsigned int sdhi2_wp_b_pins[] = {
3542 /* WP */
3543 RCAR_GP_PIN(5, 11),
3544};
3545static const unsigned int sdhi2_wp_b_mux[] = {
3546 SD2_WP_B_MARK,
3547};
3548static const unsigned int sdhi2_ds_pins[] = {
3549 /* DS */
3550 RCAR_GP_PIN(4, 6),
3551};
3552static const unsigned int sdhi2_ds_mux[] = {
3553 SD2_DS_MARK,
3554};
3555/* - SDHI3 ------------------------------------------------------------------ */
3556static const unsigned int sdhi3_data1_pins[] = {
3557 /* D0 */
3558 RCAR_GP_PIN(4, 9),
3559};
3560static const unsigned int sdhi3_data1_mux[] = {
3561 SD3_DAT0_MARK,
3562};
3563static const unsigned int sdhi3_data4_pins[] = {
3564 /* D[0:3] */
3565 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3566 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3567};
3568static const unsigned int sdhi3_data4_mux[] = {
3569 SD3_DAT0_MARK, SD3_DAT1_MARK,
3570 SD3_DAT2_MARK, SD3_DAT3_MARK,
3571};
3572static const unsigned int sdhi3_data8_pins[] = {
3573 /* D[0:7] */
3574 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3575 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3576 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3577 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3578};
3579static const unsigned int sdhi3_data8_mux[] = {
3580 SD3_DAT0_MARK, SD3_DAT1_MARK,
3581 SD3_DAT2_MARK, SD3_DAT3_MARK,
3582 SD3_DAT4_MARK, SD3_DAT5_MARK,
3583 SD3_DAT6_MARK, SD3_DAT7_MARK,
3584};
3585static const unsigned int sdhi3_ctrl_pins[] = {
3586 /* CLK, CMD */
3587 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3588};
3589static const unsigned int sdhi3_ctrl_mux[] = {
3590 SD3_CLK_MARK, SD3_CMD_MARK,
3591};
3592static const unsigned int sdhi3_cd_pins[] = {
3593 /* CD */
3594 RCAR_GP_PIN(4, 15),
3595};
3596static const unsigned int sdhi3_cd_mux[] = {
3597 SD3_CD_MARK,
3598};
3599static const unsigned int sdhi3_wp_pins[] = {
3600 /* WP */
3601 RCAR_GP_PIN(4, 16),
3602};
3603static const unsigned int sdhi3_wp_mux[] = {
3604 SD3_WP_MARK,
3605};
3606static const unsigned int sdhi3_ds_pins[] = {
3607 /* DS */
3608 RCAR_GP_PIN(4, 17),
3609};
3610static const unsigned int sdhi3_ds_mux[] = {
3611 SD3_DS_MARK,
3612};
3613
3614/* - SSI -------------------------------------------------------------------- */
3615static const unsigned int ssi0_data_pins[] = {
3616 /* SDATA */
3617 RCAR_GP_PIN(6, 2),
3618};
3619static const unsigned int ssi0_data_mux[] = {
3620 SSI_SDATA0_MARK,
3621};
3622static const unsigned int ssi01239_ctrl_pins[] = {
3623 /* SCK, WS */
3624 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3625};
3626static const unsigned int ssi01239_ctrl_mux[] = {
3627 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3628};
3629static const unsigned int ssi1_data_a_pins[] = {
3630 /* SDATA */
3631 RCAR_GP_PIN(6, 3),
3632};
3633static const unsigned int ssi1_data_a_mux[] = {
3634 SSI_SDATA1_A_MARK,
3635};
3636static const unsigned int ssi1_data_b_pins[] = {
3637 /* SDATA */
3638 RCAR_GP_PIN(5, 12),
3639};
3640static const unsigned int ssi1_data_b_mux[] = {
3641 SSI_SDATA1_B_MARK,
3642};
3643static const unsigned int ssi1_ctrl_a_pins[] = {
3644 /* SCK, WS */
3645 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3646};
3647static const unsigned int ssi1_ctrl_a_mux[] = {
3648 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3649};
3650static const unsigned int ssi1_ctrl_b_pins[] = {
3651 /* SCK, WS */
3652 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3653};
3654static const unsigned int ssi1_ctrl_b_mux[] = {
3655 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3656};
3657static const unsigned int ssi2_data_a_pins[] = {
3658 /* SDATA */
3659 RCAR_GP_PIN(6, 4),
3660};
3661static const unsigned int ssi2_data_a_mux[] = {
3662 SSI_SDATA2_A_MARK,
3663};
3664static const unsigned int ssi2_data_b_pins[] = {
3665 /* SDATA */
3666 RCAR_GP_PIN(5, 13),
3667};
3668static const unsigned int ssi2_data_b_mux[] = {
3669 SSI_SDATA2_B_MARK,
3670};
3671static const unsigned int ssi2_ctrl_a_pins[] = {
3672 /* SCK, WS */
3673 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3674};
3675static const unsigned int ssi2_ctrl_a_mux[] = {
3676 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3677};
3678static const unsigned int ssi2_ctrl_b_pins[] = {
3679 /* SCK, WS */
3680 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3681};
3682static const unsigned int ssi2_ctrl_b_mux[] = {
3683 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3684};
3685static const unsigned int ssi3_data_pins[] = {
3686 /* SDATA */
3687 RCAR_GP_PIN(6, 7),
3688};
3689static const unsigned int ssi3_data_mux[] = {
3690 SSI_SDATA3_MARK,
3691};
3692static const unsigned int ssi349_ctrl_pins[] = {
3693 /* SCK, WS */
3694 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3695};
3696static const unsigned int ssi349_ctrl_mux[] = {
3697 SSI_SCK349_MARK, SSI_WS349_MARK,
3698};
3699static const unsigned int ssi4_data_pins[] = {
3700 /* SDATA */
3701 RCAR_GP_PIN(6, 10),
3702};
3703static const unsigned int ssi4_data_mux[] = {
3704 SSI_SDATA4_MARK,
3705};
3706static const unsigned int ssi4_ctrl_pins[] = {
3707 /* SCK, WS */
3708 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3709};
3710static const unsigned int ssi4_ctrl_mux[] = {
3711 SSI_SCK4_MARK, SSI_WS4_MARK,
3712};
3713static const unsigned int ssi5_data_pins[] = {
3714 /* SDATA */
3715 RCAR_GP_PIN(6, 13),
3716};
3717static const unsigned int ssi5_data_mux[] = {
3718 SSI_SDATA5_MARK,
3719};
3720static const unsigned int ssi5_ctrl_pins[] = {
3721 /* SCK, WS */
3722 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3723};
3724static const unsigned int ssi5_ctrl_mux[] = {
3725 SSI_SCK5_MARK, SSI_WS5_MARK,
3726};
3727static const unsigned int ssi6_data_pins[] = {
3728 /* SDATA */
3729 RCAR_GP_PIN(6, 16),
3730};
3731static const unsigned int ssi6_data_mux[] = {
3732 SSI_SDATA6_MARK,
3733};
3734static const unsigned int ssi6_ctrl_pins[] = {
3735 /* SCK, WS */
3736 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3737};
3738static const unsigned int ssi6_ctrl_mux[] = {
3739 SSI_SCK6_MARK, SSI_WS6_MARK,
3740};
3741static const unsigned int ssi7_data_pins[] = {
3742 /* SDATA */
3743 RCAR_GP_PIN(6, 19),
3744};
3745static const unsigned int ssi7_data_mux[] = {
3746 SSI_SDATA7_MARK,
3747};
3748static const unsigned int ssi78_ctrl_pins[] = {
3749 /* SCK, WS */
3750 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3751};
3752static const unsigned int ssi78_ctrl_mux[] = {
3753 SSI_SCK78_MARK, SSI_WS78_MARK,
3754};
3755static const unsigned int ssi8_data_pins[] = {
3756 /* SDATA */
3757 RCAR_GP_PIN(6, 20),
3758};
3759static const unsigned int ssi8_data_mux[] = {
3760 SSI_SDATA8_MARK,
3761};
3762static const unsigned int ssi9_data_a_pins[] = {
3763 /* SDATA */
3764 RCAR_GP_PIN(6, 21),
3765};
3766static const unsigned int ssi9_data_a_mux[] = {
3767 SSI_SDATA9_A_MARK,
3768};
3769static const unsigned int ssi9_data_b_pins[] = {
3770 /* SDATA */
3771 RCAR_GP_PIN(5, 14),
3772};
3773static const unsigned int ssi9_data_b_mux[] = {
3774 SSI_SDATA9_B_MARK,
3775};
3776static const unsigned int ssi9_ctrl_a_pins[] = {
3777 /* SCK, WS */
3778 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3779};
3780static const unsigned int ssi9_ctrl_a_mux[] = {
3781 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3782};
3783static const unsigned int ssi9_ctrl_b_pins[] = {
3784 /* SCK, WS */
3785 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3786};
3787static const unsigned int ssi9_ctrl_b_mux[] = {
3788 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3789};
3790
3791/* - USB0 ------------------------------------------------------------------- */
3792static const unsigned int usb0_pins[] = {
3793 /* PWEN, OVC */
3794 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3795};
3796static const unsigned int usb0_mux[] = {
3797 USB0_PWEN_MARK, USB0_OVC_MARK,
3798};
3799/* - USB1 ------------------------------------------------------------------- */
3800static const unsigned int usb1_pins[] = {
3801 /* PWEN, OVC */
3802 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3803};
3804static const unsigned int usb1_mux[] = {
3805 USB1_PWEN_MARK, USB1_OVC_MARK,
3806};
3807
3808/* - USB30 ------------------------------------------------------------------ */
3809static const unsigned int usb30_pins[] = {
3810 /* PWEN, OVC */
3811 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3812};
3813static const unsigned int usb30_mux[] = {
3814 USB30_PWEN_MARK, USB30_OVC_MARK,
3815};
3816
3817static const struct sh_pfc_pin_group pinmux_groups[] = {
3818 SH_PFC_PIN_GROUP(audio_clk_a_a),
3819 SH_PFC_PIN_GROUP(audio_clk_a_b),
3820 SH_PFC_PIN_GROUP(audio_clk_a_c),
3821 SH_PFC_PIN_GROUP(audio_clk_b_a),
3822 SH_PFC_PIN_GROUP(audio_clk_b_b),
3823 SH_PFC_PIN_GROUP(audio_clk_c_a),
3824 SH_PFC_PIN_GROUP(audio_clk_c_b),
3825 SH_PFC_PIN_GROUP(audio_clkout_a),
3826 SH_PFC_PIN_GROUP(audio_clkout_b),
3827 SH_PFC_PIN_GROUP(audio_clkout_c),
3828 SH_PFC_PIN_GROUP(audio_clkout_d),
3829 SH_PFC_PIN_GROUP(audio_clkout1_a),
3830 SH_PFC_PIN_GROUP(audio_clkout1_b),
3831 SH_PFC_PIN_GROUP(audio_clkout2_a),
3832 SH_PFC_PIN_GROUP(audio_clkout2_b),
3833 SH_PFC_PIN_GROUP(audio_clkout3_a),
3834 SH_PFC_PIN_GROUP(audio_clkout3_b),
3835 SH_PFC_PIN_GROUP(avb_link),
3836 SH_PFC_PIN_GROUP(avb_magic),
3837 SH_PFC_PIN_GROUP(avb_phy_int),
3838 SH_PFC_PIN_GROUP(avb_mdc),
3839 SH_PFC_PIN_GROUP(avb_mii),
3840 SH_PFC_PIN_GROUP(avb_avtp_pps),
3841 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3842 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3843 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3844 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3845 SH_PFC_PIN_GROUP(can0_data_a),
3846 SH_PFC_PIN_GROUP(can0_data_b),
3847 SH_PFC_PIN_GROUP(can1_data),
3848 SH_PFC_PIN_GROUP(can_clk),
3849 SH_PFC_PIN_GROUP(canfd0_data_a),
3850 SH_PFC_PIN_GROUP(canfd0_data_b),
3851 SH_PFC_PIN_GROUP(canfd1_data),
3852 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3853 SH_PFC_PIN_GROUP(drif0_data0_a),
3854 SH_PFC_PIN_GROUP(drif0_data1_a),
3855 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3856 SH_PFC_PIN_GROUP(drif0_data0_b),
3857 SH_PFC_PIN_GROUP(drif0_data1_b),
3858 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3859 SH_PFC_PIN_GROUP(drif0_data0_c),
3860 SH_PFC_PIN_GROUP(drif0_data1_c),
3861 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3862 SH_PFC_PIN_GROUP(drif1_data0_a),
3863 SH_PFC_PIN_GROUP(drif1_data1_a),
3864 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3865 SH_PFC_PIN_GROUP(drif1_data0_b),
3866 SH_PFC_PIN_GROUP(drif1_data1_b),
3867 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3868 SH_PFC_PIN_GROUP(drif1_data0_c),
3869 SH_PFC_PIN_GROUP(drif1_data1_c),
3870 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3871 SH_PFC_PIN_GROUP(drif2_data0_a),
3872 SH_PFC_PIN_GROUP(drif2_data1_a),
3873 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3874 SH_PFC_PIN_GROUP(drif2_data0_b),
3875 SH_PFC_PIN_GROUP(drif2_data1_b),
3876 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3877 SH_PFC_PIN_GROUP(drif3_data0_a),
3878 SH_PFC_PIN_GROUP(drif3_data1_a),
3879 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3880 SH_PFC_PIN_GROUP(drif3_data0_b),
3881 SH_PFC_PIN_GROUP(drif3_data1_b),
3882 SH_PFC_PIN_GROUP(du_rgb666),
3883 SH_PFC_PIN_GROUP(du_rgb888),
3884 SH_PFC_PIN_GROUP(du_clk_out_0),
3885 SH_PFC_PIN_GROUP(du_clk_out_1),
3886 SH_PFC_PIN_GROUP(du_sync),
3887 SH_PFC_PIN_GROUP(du_oddf),
3888 SH_PFC_PIN_GROUP(du_cde),
3889 SH_PFC_PIN_GROUP(du_disp),
3890 SH_PFC_PIN_GROUP(hscif0_data),
3891 SH_PFC_PIN_GROUP(hscif0_clk),
3892 SH_PFC_PIN_GROUP(hscif0_ctrl),
3893 SH_PFC_PIN_GROUP(hscif1_data_a),
3894 SH_PFC_PIN_GROUP(hscif1_clk_a),
3895 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3896 SH_PFC_PIN_GROUP(hscif1_data_b),
3897 SH_PFC_PIN_GROUP(hscif1_clk_b),
3898 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3899 SH_PFC_PIN_GROUP(hscif2_data_a),
3900 SH_PFC_PIN_GROUP(hscif2_clk_a),
3901 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3902 SH_PFC_PIN_GROUP(hscif2_data_b),
3903 SH_PFC_PIN_GROUP(hscif2_clk_b),
3904 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3905 SH_PFC_PIN_GROUP(hscif2_data_c),
3906 SH_PFC_PIN_GROUP(hscif2_clk_c),
3907 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3908 SH_PFC_PIN_GROUP(hscif3_data_a),
3909 SH_PFC_PIN_GROUP(hscif3_clk),
3910 SH_PFC_PIN_GROUP(hscif3_ctrl),
3911 SH_PFC_PIN_GROUP(hscif3_data_b),
3912 SH_PFC_PIN_GROUP(hscif3_data_c),
3913 SH_PFC_PIN_GROUP(hscif3_data_d),
3914 SH_PFC_PIN_GROUP(hscif4_data_a),
3915 SH_PFC_PIN_GROUP(hscif4_clk),
3916 SH_PFC_PIN_GROUP(hscif4_ctrl),
3917 SH_PFC_PIN_GROUP(hscif4_data_b),
3918 SH_PFC_PIN_GROUP(i2c1_a),
3919 SH_PFC_PIN_GROUP(i2c1_b),
3920 SH_PFC_PIN_GROUP(i2c2_a),
3921 SH_PFC_PIN_GROUP(i2c2_b),
3922 SH_PFC_PIN_GROUP(i2c6_a),
3923 SH_PFC_PIN_GROUP(i2c6_b),
3924 SH_PFC_PIN_GROUP(i2c6_c),
3925 SH_PFC_PIN_GROUP(msiof0_clk),
3926 SH_PFC_PIN_GROUP(msiof0_sync),
3927 SH_PFC_PIN_GROUP(msiof0_ss1),
3928 SH_PFC_PIN_GROUP(msiof0_ss2),
3929 SH_PFC_PIN_GROUP(msiof0_txd),
3930 SH_PFC_PIN_GROUP(msiof0_rxd),
3931 SH_PFC_PIN_GROUP(msiof1_clk_a),
3932 SH_PFC_PIN_GROUP(msiof1_sync_a),
3933 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3934 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3935 SH_PFC_PIN_GROUP(msiof1_txd_a),
3936 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3937 SH_PFC_PIN_GROUP(msiof1_clk_b),
3938 SH_PFC_PIN_GROUP(msiof1_sync_b),
3939 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3940 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3941 SH_PFC_PIN_GROUP(msiof1_txd_b),
3942 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3943 SH_PFC_PIN_GROUP(msiof1_clk_c),
3944 SH_PFC_PIN_GROUP(msiof1_sync_c),
3945 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3946 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3947 SH_PFC_PIN_GROUP(msiof1_txd_c),
3948 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3949 SH_PFC_PIN_GROUP(msiof1_clk_d),
3950 SH_PFC_PIN_GROUP(msiof1_sync_d),
3951 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3952 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3953 SH_PFC_PIN_GROUP(msiof1_txd_d),
3954 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3955 SH_PFC_PIN_GROUP(msiof1_clk_e),
3956 SH_PFC_PIN_GROUP(msiof1_sync_e),
3957 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3958 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3959 SH_PFC_PIN_GROUP(msiof1_txd_e),
3960 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3961 SH_PFC_PIN_GROUP(msiof1_clk_f),
3962 SH_PFC_PIN_GROUP(msiof1_sync_f),
3963 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3964 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3965 SH_PFC_PIN_GROUP(msiof1_txd_f),
3966 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3967 SH_PFC_PIN_GROUP(msiof1_clk_g),
3968 SH_PFC_PIN_GROUP(msiof1_sync_g),
3969 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3970 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3971 SH_PFC_PIN_GROUP(msiof1_txd_g),
3972 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3973 SH_PFC_PIN_GROUP(msiof2_clk_a),
3974 SH_PFC_PIN_GROUP(msiof2_sync_a),
3975 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3976 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3977 SH_PFC_PIN_GROUP(msiof2_txd_a),
3978 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3979 SH_PFC_PIN_GROUP(msiof2_clk_b),
3980 SH_PFC_PIN_GROUP(msiof2_sync_b),
3981 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3982 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3983 SH_PFC_PIN_GROUP(msiof2_txd_b),
3984 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3985 SH_PFC_PIN_GROUP(msiof2_clk_c),
3986 SH_PFC_PIN_GROUP(msiof2_sync_c),
3987 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3988 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3989 SH_PFC_PIN_GROUP(msiof2_txd_c),
3990 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3991 SH_PFC_PIN_GROUP(msiof2_clk_d),
3992 SH_PFC_PIN_GROUP(msiof2_sync_d),
3993 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3994 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3995 SH_PFC_PIN_GROUP(msiof2_txd_d),
3996 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3997 SH_PFC_PIN_GROUP(msiof3_clk_a),
3998 SH_PFC_PIN_GROUP(msiof3_sync_a),
3999 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4000 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4001 SH_PFC_PIN_GROUP(msiof3_txd_a),
4002 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4003 SH_PFC_PIN_GROUP(msiof3_clk_b),
4004 SH_PFC_PIN_GROUP(msiof3_sync_b),
4005 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4006 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4007 SH_PFC_PIN_GROUP(msiof3_txd_b),
4008 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4009 SH_PFC_PIN_GROUP(msiof3_clk_c),
4010 SH_PFC_PIN_GROUP(msiof3_sync_c),
4011 SH_PFC_PIN_GROUP(msiof3_txd_c),
4012 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4013 SH_PFC_PIN_GROUP(msiof3_clk_d),
4014 SH_PFC_PIN_GROUP(msiof3_sync_d),
4015 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4016 SH_PFC_PIN_GROUP(msiof3_txd_d),
4017 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4018 SH_PFC_PIN_GROUP(msiof3_clk_e),
4019 SH_PFC_PIN_GROUP(msiof3_sync_e),
4020 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4021 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4022 SH_PFC_PIN_GROUP(msiof3_txd_e),
4023 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4024 SH_PFC_PIN_GROUP(pwm0),
4025 SH_PFC_PIN_GROUP(pwm1_a),
4026 SH_PFC_PIN_GROUP(pwm1_b),
4027 SH_PFC_PIN_GROUP(pwm2_a),
4028 SH_PFC_PIN_GROUP(pwm2_b),
4029 SH_PFC_PIN_GROUP(pwm3_a),
4030 SH_PFC_PIN_GROUP(pwm3_b),
4031 SH_PFC_PIN_GROUP(pwm4_a),
4032 SH_PFC_PIN_GROUP(pwm4_b),
4033 SH_PFC_PIN_GROUP(pwm5_a),
4034 SH_PFC_PIN_GROUP(pwm5_b),
4035 SH_PFC_PIN_GROUP(pwm6_a),
4036 SH_PFC_PIN_GROUP(pwm6_b),
4037 SH_PFC_PIN_GROUP(scif0_data),
4038 SH_PFC_PIN_GROUP(scif0_clk),
4039 SH_PFC_PIN_GROUP(scif0_ctrl),
4040 SH_PFC_PIN_GROUP(scif1_data_a),
4041 SH_PFC_PIN_GROUP(scif1_clk),
4042 SH_PFC_PIN_GROUP(scif1_ctrl),
4043 SH_PFC_PIN_GROUP(scif1_data_b),
4044 SH_PFC_PIN_GROUP(scif2_data_a),
4045 SH_PFC_PIN_GROUP(scif2_clk),
4046 SH_PFC_PIN_GROUP(scif2_data_b),
4047 SH_PFC_PIN_GROUP(scif3_data_a),
4048 SH_PFC_PIN_GROUP(scif3_clk),
4049 SH_PFC_PIN_GROUP(scif3_ctrl),
4050 SH_PFC_PIN_GROUP(scif3_data_b),
4051 SH_PFC_PIN_GROUP(scif4_data_a),
4052 SH_PFC_PIN_GROUP(scif4_clk_a),
4053 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4054 SH_PFC_PIN_GROUP(scif4_data_b),
4055 SH_PFC_PIN_GROUP(scif4_clk_b),
4056 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4057 SH_PFC_PIN_GROUP(scif4_data_c),
4058 SH_PFC_PIN_GROUP(scif4_clk_c),
4059 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4060 SH_PFC_PIN_GROUP(scif5_data_a),
4061 SH_PFC_PIN_GROUP(scif5_clk_a),
4062 SH_PFC_PIN_GROUP(scif5_data_b),
4063 SH_PFC_PIN_GROUP(scif5_clk_b),
4064 SH_PFC_PIN_GROUP(scif_clk_a),
4065 SH_PFC_PIN_GROUP(scif_clk_b),
4066 SH_PFC_PIN_GROUP(sdhi0_data1),
4067 SH_PFC_PIN_GROUP(sdhi0_data4),
4068 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4069 SH_PFC_PIN_GROUP(sdhi0_cd),
4070 SH_PFC_PIN_GROUP(sdhi0_wp),
4071 SH_PFC_PIN_GROUP(sdhi1_data1),
4072 SH_PFC_PIN_GROUP(sdhi1_data4),
4073 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4074 SH_PFC_PIN_GROUP(sdhi1_cd),
4075 SH_PFC_PIN_GROUP(sdhi1_wp),
4076 SH_PFC_PIN_GROUP(sdhi2_data1),
4077 SH_PFC_PIN_GROUP(sdhi2_data4),
4078 SH_PFC_PIN_GROUP(sdhi2_data8),
4079 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4080 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4081 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4082 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4083 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4084 SH_PFC_PIN_GROUP(sdhi2_ds),
4085 SH_PFC_PIN_GROUP(sdhi3_data1),
4086 SH_PFC_PIN_GROUP(sdhi3_data4),
4087 SH_PFC_PIN_GROUP(sdhi3_data8),
4088 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4089 SH_PFC_PIN_GROUP(sdhi3_cd),
4090 SH_PFC_PIN_GROUP(sdhi3_wp),
4091 SH_PFC_PIN_GROUP(sdhi3_ds),
4092 SH_PFC_PIN_GROUP(ssi0_data),
4093 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4094 SH_PFC_PIN_GROUP(ssi1_data_a),
4095 SH_PFC_PIN_GROUP(ssi1_data_b),
4096 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4097 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4098 SH_PFC_PIN_GROUP(ssi2_data_a),
4099 SH_PFC_PIN_GROUP(ssi2_data_b),
4100 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4101 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4102 SH_PFC_PIN_GROUP(ssi3_data),
4103 SH_PFC_PIN_GROUP(ssi349_ctrl),
4104 SH_PFC_PIN_GROUP(ssi4_data),
4105 SH_PFC_PIN_GROUP(ssi4_ctrl),
4106 SH_PFC_PIN_GROUP(ssi5_data),
4107 SH_PFC_PIN_GROUP(ssi5_ctrl),
4108 SH_PFC_PIN_GROUP(ssi6_data),
4109 SH_PFC_PIN_GROUP(ssi6_ctrl),
4110 SH_PFC_PIN_GROUP(ssi7_data),
4111 SH_PFC_PIN_GROUP(ssi78_ctrl),
4112 SH_PFC_PIN_GROUP(ssi8_data),
4113 SH_PFC_PIN_GROUP(ssi9_data_a),
4114 SH_PFC_PIN_GROUP(ssi9_data_b),
4115 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4116 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4117 SH_PFC_PIN_GROUP(usb0),
4118 SH_PFC_PIN_GROUP(usb1),
4119 SH_PFC_PIN_GROUP(usb30),
4120};
4121
4122static const char * const audio_clk_groups[] = {
4123 "audio_clk_a_a",
4124 "audio_clk_a_b",
4125 "audio_clk_a_c",
4126 "audio_clk_b_a",
4127 "audio_clk_b_b",
4128 "audio_clk_c_a",
4129 "audio_clk_c_b",
4130 "audio_clkout_a",
4131 "audio_clkout_b",
4132 "audio_clkout_c",
4133 "audio_clkout_d",
4134 "audio_clkout1_a",
4135 "audio_clkout1_b",
4136 "audio_clkout2_a",
4137 "audio_clkout2_b",
4138 "audio_clkout3_a",
4139 "audio_clkout3_b",
4140};
4141
4142static const char * const avb_groups[] = {
4143 "avb_link",
4144 "avb_magic",
4145 "avb_phy_int",
4146 "avb_mdc",
4147 "avb_mii",
4148 "avb_avtp_pps",
4149 "avb_avtp_match_a",
4150 "avb_avtp_capture_a",
4151 "avb_avtp_match_b",
4152 "avb_avtp_capture_b",
4153};
4154
4155static const char * const can0_groups[] = {
4156 "can0_data_a",
4157 "can0_data_b",
4158};
4159
4160static const char * const can1_groups[] = {
4161 "can1_data",
4162};
4163
4164static const char * const can_clk_groups[] = {
4165 "can_clk",
4166};
4167
4168static const char * const canfd0_groups[] = {
4169 "canfd0_data_a",
4170 "canfd0_data_b",
4171};
4172
4173static const char * const canfd1_groups[] = {
4174 "canfd1_data",
4175};
4176
4177static const char * const drif0_groups[] = {
4178 "drif0_ctrl_a",
4179 "drif0_data0_a",
4180 "drif0_data1_a",
4181 "drif0_ctrl_b",
4182 "drif0_data0_b",
4183 "drif0_data1_b",
4184 "drif0_ctrl_c",
4185 "drif0_data0_c",
4186 "drif0_data1_c",
4187};
4188
4189static const char * const drif1_groups[] = {
4190 "drif1_ctrl_a",
4191 "drif1_data0_a",
4192 "drif1_data1_a",
4193 "drif1_ctrl_b",
4194 "drif1_data0_b",
4195 "drif1_data1_b",
4196 "drif1_ctrl_c",
4197 "drif1_data0_c",
4198 "drif1_data1_c",
4199};
4200
4201static const char * const drif2_groups[] = {
4202 "drif2_ctrl_a",
4203 "drif2_data0_a",
4204 "drif2_data1_a",
4205 "drif2_ctrl_b",
4206 "drif2_data0_b",
4207 "drif2_data1_b",
4208};
4209
4210static const char * const drif3_groups[] = {
4211 "drif3_ctrl_a",
4212 "drif3_data0_a",
4213 "drif3_data1_a",
4214 "drif3_ctrl_b",
4215 "drif3_data0_b",
4216 "drif3_data1_b",
4217};
4218
4219static const char * const du_groups[] = {
4220 "du_rgb666",
4221 "du_rgb888",
4222 "du_clk_out_0",
4223 "du_clk_out_1",
4224 "du_sync",
4225 "du_oddf",
4226 "du_cde",
4227 "du_disp",
4228};
4229
4230static const char * const hscif0_groups[] = {
4231 "hscif0_data",
4232 "hscif0_clk",
4233 "hscif0_ctrl",
4234};
4235
4236static const char * const hscif1_groups[] = {
4237 "hscif1_data_a",
4238 "hscif1_clk_a",
4239 "hscif1_ctrl_a",
4240 "hscif1_data_b",
4241 "hscif1_clk_b",
4242 "hscif1_ctrl_b",
4243};
4244
4245static const char * const hscif2_groups[] = {
4246 "hscif2_data_a",
4247 "hscif2_clk_a",
4248 "hscif2_ctrl_a",
4249 "hscif2_data_b",
4250 "hscif2_clk_b",
4251 "hscif2_ctrl_b",
4252 "hscif2_data_c",
4253 "hscif2_clk_c",
4254 "hscif2_ctrl_c",
4255};
4256
4257static const char * const hscif3_groups[] = {
4258 "hscif3_data_a",
4259 "hscif3_clk",
4260 "hscif3_ctrl",
4261 "hscif3_data_b",
4262 "hscif3_data_c",
4263 "hscif3_data_d",
4264};
4265
4266static const char * const hscif4_groups[] = {
4267 "hscif4_data_a",
4268 "hscif4_clk",
4269 "hscif4_ctrl",
4270 "hscif4_data_b",
4271};
4272
4273static const char * const i2c1_groups[] = {
4274 "i2c1_a",
4275 "i2c1_b",
4276};
4277
4278static const char * const i2c2_groups[] = {
4279 "i2c2_a",
4280 "i2c2_b",
4281};
4282
4283static const char * const i2c6_groups[] = {
4284 "i2c6_a",
4285 "i2c6_b",
4286 "i2c6_c",
4287};
4288
4289static const char * const msiof0_groups[] = {
4290 "msiof0_clk",
4291 "msiof0_sync",
4292 "msiof0_ss1",
4293 "msiof0_ss2",
4294 "msiof0_txd",
4295 "msiof0_rxd",
4296};
4297
4298static const char * const msiof1_groups[] = {
4299 "msiof1_clk_a",
4300 "msiof1_sync_a",
4301 "msiof1_ss1_a",
4302 "msiof1_ss2_a",
4303 "msiof1_txd_a",
4304 "msiof1_rxd_a",
4305 "msiof1_clk_b",
4306 "msiof1_sync_b",
4307 "msiof1_ss1_b",
4308 "msiof1_ss2_b",
4309 "msiof1_txd_b",
4310 "msiof1_rxd_b",
4311 "msiof1_clk_c",
4312 "msiof1_sync_c",
4313 "msiof1_ss1_c",
4314 "msiof1_ss2_c",
4315 "msiof1_txd_c",
4316 "msiof1_rxd_c",
4317 "msiof1_clk_d",
4318 "msiof1_sync_d",
4319 "msiof1_ss1_d",
4320 "msiof1_ss2_d",
4321 "msiof1_txd_d",
4322 "msiof1_rxd_d",
4323 "msiof1_clk_e",
4324 "msiof1_sync_e",
4325 "msiof1_ss1_e",
4326 "msiof1_ss2_e",
4327 "msiof1_txd_e",
4328 "msiof1_rxd_e",
4329 "msiof1_clk_f",
4330 "msiof1_sync_f",
4331 "msiof1_ss1_f",
4332 "msiof1_ss2_f",
4333 "msiof1_txd_f",
4334 "msiof1_rxd_f",
4335 "msiof1_clk_g",
4336 "msiof1_sync_g",
4337 "msiof1_ss1_g",
4338 "msiof1_ss2_g",
4339 "msiof1_txd_g",
4340 "msiof1_rxd_g",
4341};
4342
4343static const char * const msiof2_groups[] = {
4344 "msiof2_clk_a",
4345 "msiof2_sync_a",
4346 "msiof2_ss1_a",
4347 "msiof2_ss2_a",
4348 "msiof2_txd_a",
4349 "msiof2_rxd_a",
4350 "msiof2_clk_b",
4351 "msiof2_sync_b",
4352 "msiof2_ss1_b",
4353 "msiof2_ss2_b",
4354 "msiof2_txd_b",
4355 "msiof2_rxd_b",
4356 "msiof2_clk_c",
4357 "msiof2_sync_c",
4358 "msiof2_ss1_c",
4359 "msiof2_ss2_c",
4360 "msiof2_txd_c",
4361 "msiof2_rxd_c",
4362 "msiof2_clk_d",
4363 "msiof2_sync_d",
4364 "msiof2_ss1_d",
4365 "msiof2_ss2_d",
4366 "msiof2_txd_d",
4367 "msiof2_rxd_d",
4368};
4369
4370static const char * const msiof3_groups[] = {
4371 "msiof3_clk_a",
4372 "msiof3_sync_a",
4373 "msiof3_ss1_a",
4374 "msiof3_ss2_a",
4375 "msiof3_txd_a",
4376 "msiof3_rxd_a",
4377 "msiof3_clk_b",
4378 "msiof3_sync_b",
4379 "msiof3_ss1_b",
4380 "msiof3_ss2_b",
4381 "msiof3_txd_b",
4382 "msiof3_rxd_b",
4383 "msiof3_clk_c",
4384 "msiof3_sync_c",
4385 "msiof3_txd_c",
4386 "msiof3_rxd_c",
4387 "msiof3_clk_d",
4388 "msiof3_sync_d",
4389 "msiof3_ss1_d",
4390 "msiof3_txd_d",
4391 "msiof3_rxd_d",
4392 "msiof3_clk_e",
4393 "msiof3_sync_e",
4394 "msiof3_ss1_e",
4395 "msiof3_ss2_e",
4396 "msiof3_txd_e",
4397 "msiof3_rxd_e",
4398};
4399
4400static const char * const pwm0_groups[] = {
4401 "pwm0",
4402};
4403
4404static const char * const pwm1_groups[] = {
4405 "pwm1_a",
4406 "pwm1_b",
4407};
4408
4409static const char * const pwm2_groups[] = {
4410 "pwm2_a",
4411 "pwm2_b",
4412};
4413
4414static const char * const pwm3_groups[] = {
4415 "pwm3_a",
4416 "pwm3_b",
4417};
4418
4419static const char * const pwm4_groups[] = {
4420 "pwm4_a",
4421 "pwm4_b",
4422};
4423
4424static const char * const pwm5_groups[] = {
4425 "pwm5_a",
4426 "pwm5_b",
4427};
4428
4429static const char * const pwm6_groups[] = {
4430 "pwm6_a",
4431 "pwm6_b",
4432};
4433
4434static const char * const scif0_groups[] = {
4435 "scif0_data",
4436 "scif0_clk",
4437 "scif0_ctrl",
4438};
4439
4440static const char * const scif1_groups[] = {
4441 "scif1_data_a",
4442 "scif1_clk",
4443 "scif1_ctrl",
4444 "scif1_data_b",
4445};
4446
4447static const char * const scif2_groups[] = {
4448 "scif2_data_a",
4449 "scif2_clk",
4450 "scif2_data_b",
4451};
4452
4453static const char * const scif3_groups[] = {
4454 "scif3_data_a",
4455 "scif3_clk",
4456 "scif3_ctrl",
4457 "scif3_data_b",
4458};
4459
4460static const char * const scif4_groups[] = {
4461 "scif4_data_a",
4462 "scif4_clk_a",
4463 "scif4_ctrl_a",
4464 "scif4_data_b",
4465 "scif4_clk_b",
4466 "scif4_ctrl_b",
4467 "scif4_data_c",
4468 "scif4_clk_c",
4469 "scif4_ctrl_c",
4470};
4471
4472static const char * const scif5_groups[] = {
4473 "scif5_data_a",
4474 "scif5_clk_a",
4475 "scif5_data_b",
4476 "scif5_clk_b",
4477};
4478
4479static const char * const scif_clk_groups[] = {
4480 "scif_clk_a",
4481 "scif_clk_b",
4482};
4483
4484static const char * const sdhi0_groups[] = {
4485 "sdhi0_data1",
4486 "sdhi0_data4",
4487 "sdhi0_ctrl",
4488 "sdhi0_cd",
4489 "sdhi0_wp",
4490};
4491
4492static const char * const sdhi1_groups[] = {
4493 "sdhi1_data1",
4494 "sdhi1_data4",
4495 "sdhi1_ctrl",
4496 "sdhi1_cd",
4497 "sdhi1_wp",
4498};
4499
4500static const char * const sdhi2_groups[] = {
4501 "sdhi2_data1",
4502 "sdhi2_data4",
4503 "sdhi2_data8",
4504 "sdhi2_ctrl",
4505 "sdhi2_cd_a",
4506 "sdhi2_wp_a",
4507 "sdhi2_cd_b",
4508 "sdhi2_wp_b",
4509 "sdhi2_ds",
4510};
4511
4512static const char * const sdhi3_groups[] = {
4513 "sdhi3_data1",
4514 "sdhi3_data4",
4515 "sdhi3_data8",
4516 "sdhi3_ctrl",
4517 "sdhi3_cd",
4518 "sdhi3_wp",
4519 "sdhi3_ds",
4520};
4521
4522static const char * const ssi_groups[] = {
4523 "ssi0_data",
4524 "ssi01239_ctrl",
4525 "ssi1_data_a",
4526 "ssi1_data_b",
4527 "ssi1_ctrl_a",
4528 "ssi1_ctrl_b",
4529 "ssi2_data_a",
4530 "ssi2_data_b",
4531 "ssi2_ctrl_a",
4532 "ssi2_ctrl_b",
4533 "ssi3_data",
4534 "ssi349_ctrl",
4535 "ssi4_data",
4536 "ssi4_ctrl",
4537 "ssi5_data",
4538 "ssi5_ctrl",
4539 "ssi6_data",
4540 "ssi6_ctrl",
4541 "ssi7_data",
4542 "ssi78_ctrl",
4543 "ssi8_data",
4544 "ssi9_data_a",
4545 "ssi9_data_b",
4546 "ssi9_ctrl_a",
4547 "ssi9_ctrl_b",
4548};
4549
4550static const char * const usb0_groups[] = {
4551 "usb0",
4552};
4553
4554static const char * const usb1_groups[] = {
4555 "usb1",
4556};
4557
4558static const char * const usb30_groups[] = {
4559 "usb30",
4560};
4561
4562static const struct sh_pfc_function pinmux_functions[] = {
4563 SH_PFC_FUNCTION(audio_clk),
4564 SH_PFC_FUNCTION(avb),
4565 SH_PFC_FUNCTION(can0),
4566 SH_PFC_FUNCTION(can1),
4567 SH_PFC_FUNCTION(can_clk),
4568 SH_PFC_FUNCTION(canfd0),
4569 SH_PFC_FUNCTION(canfd1),
4570 SH_PFC_FUNCTION(drif0),
4571 SH_PFC_FUNCTION(drif1),
4572 SH_PFC_FUNCTION(drif2),
4573 SH_PFC_FUNCTION(drif3),
4574 SH_PFC_FUNCTION(du),
4575 SH_PFC_FUNCTION(hscif0),
4576 SH_PFC_FUNCTION(hscif1),
4577 SH_PFC_FUNCTION(hscif2),
4578 SH_PFC_FUNCTION(hscif3),
4579 SH_PFC_FUNCTION(hscif4),
4580 SH_PFC_FUNCTION(i2c1),
4581 SH_PFC_FUNCTION(i2c2),
4582 SH_PFC_FUNCTION(i2c6),
4583 SH_PFC_FUNCTION(msiof0),
4584 SH_PFC_FUNCTION(msiof1),
4585 SH_PFC_FUNCTION(msiof2),
4586 SH_PFC_FUNCTION(msiof3),
4587 SH_PFC_FUNCTION(pwm0),
4588 SH_PFC_FUNCTION(pwm1),
4589 SH_PFC_FUNCTION(pwm2),
4590 SH_PFC_FUNCTION(pwm3),
4591 SH_PFC_FUNCTION(pwm4),
4592 SH_PFC_FUNCTION(pwm5),
4593 SH_PFC_FUNCTION(pwm6),
4594 SH_PFC_FUNCTION(scif0),
4595 SH_PFC_FUNCTION(scif1),
4596 SH_PFC_FUNCTION(scif2),
4597 SH_PFC_FUNCTION(scif3),
4598 SH_PFC_FUNCTION(scif4),
4599 SH_PFC_FUNCTION(scif5),
4600 SH_PFC_FUNCTION(scif_clk),
4601 SH_PFC_FUNCTION(sdhi0),
4602 SH_PFC_FUNCTION(sdhi1),
4603 SH_PFC_FUNCTION(sdhi2),
4604 SH_PFC_FUNCTION(sdhi3),
4605 SH_PFC_FUNCTION(ssi),
4606 SH_PFC_FUNCTION(usb0),
4607 SH_PFC_FUNCTION(usb1),
4608 SH_PFC_FUNCTION(usb30),
4609};
4610
4611static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4612#define F_(x, y) FN_##y
4613#define FM(x) FN_##x
4614 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4615 0, 0,
4616 0, 0,
4617 0, 0,
4618 0, 0,
4619 0, 0,
4620 0, 0,
4621 0, 0,
4622 0, 0,
4623 0, 0,
4624 0, 0,
4625 0, 0,
4626 0, 0,
4627 0, 0,
4628 0, 0,
4629 0, 0,
4630 0, 0,
4631 GP_0_15_FN, GPSR0_15,
4632 GP_0_14_FN, GPSR0_14,
4633 GP_0_13_FN, GPSR0_13,
4634 GP_0_12_FN, GPSR0_12,
4635 GP_0_11_FN, GPSR0_11,
4636 GP_0_10_FN, GPSR0_10,
4637 GP_0_9_FN, GPSR0_9,
4638 GP_0_8_FN, GPSR0_8,
4639 GP_0_7_FN, GPSR0_7,
4640 GP_0_6_FN, GPSR0_6,
4641 GP_0_5_FN, GPSR0_5,
4642 GP_0_4_FN, GPSR0_4,
4643 GP_0_3_FN, GPSR0_3,
4644 GP_0_2_FN, GPSR0_2,
4645 GP_0_1_FN, GPSR0_1,
4646 GP_0_0_FN, GPSR0_0, }
4647 },
4648 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4649 0, 0,
4650 0, 0,
4651 0, 0,
4652 GP_1_28_FN, GPSR1_28,
4653 GP_1_27_FN, GPSR1_27,
4654 GP_1_26_FN, GPSR1_26,
4655 GP_1_25_FN, GPSR1_25,
4656 GP_1_24_FN, GPSR1_24,
4657 GP_1_23_FN, GPSR1_23,
4658 GP_1_22_FN, GPSR1_22,
4659 GP_1_21_FN, GPSR1_21,
4660 GP_1_20_FN, GPSR1_20,
4661 GP_1_19_FN, GPSR1_19,
4662 GP_1_18_FN, GPSR1_18,
4663 GP_1_17_FN, GPSR1_17,
4664 GP_1_16_FN, GPSR1_16,
4665 GP_1_15_FN, GPSR1_15,
4666 GP_1_14_FN, GPSR1_14,
4667 GP_1_13_FN, GPSR1_13,
4668 GP_1_12_FN, GPSR1_12,
4669 GP_1_11_FN, GPSR1_11,
4670 GP_1_10_FN, GPSR1_10,
4671 GP_1_9_FN, GPSR1_9,
4672 GP_1_8_FN, GPSR1_8,
4673 GP_1_7_FN, GPSR1_7,
4674 GP_1_6_FN, GPSR1_6,
4675 GP_1_5_FN, GPSR1_5,
4676 GP_1_4_FN, GPSR1_4,
4677 GP_1_3_FN, GPSR1_3,
4678 GP_1_2_FN, GPSR1_2,
4679 GP_1_1_FN, GPSR1_1,
4680 GP_1_0_FN, GPSR1_0, }
4681 },
4682 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4683 0, 0,
4684 0, 0,
4685 0, 0,
4686 0, 0,
4687 0, 0,
4688 0, 0,
4689 0, 0,
4690 0, 0,
4691 0, 0,
4692 0, 0,
4693 0, 0,
4694 0, 0,
4695 0, 0,
4696 0, 0,
4697 0, 0,
4698 0, 0,
4699 0, 0,
4700 GP_2_14_FN, GPSR2_14,
4701 GP_2_13_FN, GPSR2_13,
4702 GP_2_12_FN, GPSR2_12,
4703 GP_2_11_FN, GPSR2_11,
4704 GP_2_10_FN, GPSR2_10,
4705 GP_2_9_FN, GPSR2_9,
4706 GP_2_8_FN, GPSR2_8,
4707 GP_2_7_FN, GPSR2_7,
4708 GP_2_6_FN, GPSR2_6,
4709 GP_2_5_FN, GPSR2_5,
4710 GP_2_4_FN, GPSR2_4,
4711 GP_2_3_FN, GPSR2_3,
4712 GP_2_2_FN, GPSR2_2,
4713 GP_2_1_FN, GPSR2_1,
4714 GP_2_0_FN, GPSR2_0, }
4715 },
4716 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4717 0, 0,
4718 0, 0,
4719 0, 0,
4720 0, 0,
4721 0, 0,
4722 0, 0,
4723 0, 0,
4724 0, 0,
4725 0, 0,
4726 0, 0,
4727 0, 0,
4728 0, 0,
4729 0, 0,
4730 0, 0,
4731 0, 0,
4732 0, 0,
4733 GP_3_15_FN, GPSR3_15,
4734 GP_3_14_FN, GPSR3_14,
4735 GP_3_13_FN, GPSR3_13,
4736 GP_3_12_FN, GPSR3_12,
4737 GP_3_11_FN, GPSR3_11,
4738 GP_3_10_FN, GPSR3_10,
4739 GP_3_9_FN, GPSR3_9,
4740 GP_3_8_FN, GPSR3_8,
4741 GP_3_7_FN, GPSR3_7,
4742 GP_3_6_FN, GPSR3_6,
4743 GP_3_5_FN, GPSR3_5,
4744 GP_3_4_FN, GPSR3_4,
4745 GP_3_3_FN, GPSR3_3,
4746 GP_3_2_FN, GPSR3_2,
4747 GP_3_1_FN, GPSR3_1,
4748 GP_3_0_FN, GPSR3_0, }
4749 },
4750 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4751 0, 0,
4752 0, 0,
4753 0, 0,
4754 0, 0,
4755 0, 0,
4756 0, 0,
4757 0, 0,
4758 0, 0,
4759 0, 0,
4760 0, 0,
4761 0, 0,
4762 0, 0,
4763 0, 0,
4764 0, 0,
4765 GP_4_17_FN, GPSR4_17,
4766 GP_4_16_FN, GPSR4_16,
4767 GP_4_15_FN, GPSR4_15,
4768 GP_4_14_FN, GPSR4_14,
4769 GP_4_13_FN, GPSR4_13,
4770 GP_4_12_FN, GPSR4_12,
4771 GP_4_11_FN, GPSR4_11,
4772 GP_4_10_FN, GPSR4_10,
4773 GP_4_9_FN, GPSR4_9,
4774 GP_4_8_FN, GPSR4_8,
4775 GP_4_7_FN, GPSR4_7,
4776 GP_4_6_FN, GPSR4_6,
4777 GP_4_5_FN, GPSR4_5,
4778 GP_4_4_FN, GPSR4_4,
4779 GP_4_3_FN, GPSR4_3,
4780 GP_4_2_FN, GPSR4_2,
4781 GP_4_1_FN, GPSR4_1,
4782 GP_4_0_FN, GPSR4_0, }
4783 },
4784 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4785 0, 0,
4786 0, 0,
4787 0, 0,
4788 0, 0,
4789 0, 0,
4790 0, 0,
4791 GP_5_25_FN, GPSR5_25,
4792 GP_5_24_FN, GPSR5_24,
4793 GP_5_23_FN, GPSR5_23,
4794 GP_5_22_FN, GPSR5_22,
4795 GP_5_21_FN, GPSR5_21,
4796 GP_5_20_FN, GPSR5_20,
4797 GP_5_19_FN, GPSR5_19,
4798 GP_5_18_FN, GPSR5_18,
4799 GP_5_17_FN, GPSR5_17,
4800 GP_5_16_FN, GPSR5_16,
4801 GP_5_15_FN, GPSR5_15,
4802 GP_5_14_FN, GPSR5_14,
4803 GP_5_13_FN, GPSR5_13,
4804 GP_5_12_FN, GPSR5_12,
4805 GP_5_11_FN, GPSR5_11,
4806 GP_5_10_FN, GPSR5_10,
4807 GP_5_9_FN, GPSR5_9,
4808 GP_5_8_FN, GPSR5_8,
4809 GP_5_7_FN, GPSR5_7,
4810 GP_5_6_FN, GPSR5_6,
4811 GP_5_5_FN, GPSR5_5,
4812 GP_5_4_FN, GPSR5_4,
4813 GP_5_3_FN, GPSR5_3,
4814 GP_5_2_FN, GPSR5_2,
4815 GP_5_1_FN, GPSR5_1,
4816 GP_5_0_FN, GPSR5_0, }
4817 },
4818 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4819 GP_6_31_FN, GPSR6_31,
4820 GP_6_30_FN, GPSR6_30,
4821 GP_6_29_FN, GPSR6_29,
4822 GP_6_28_FN, GPSR6_28,
4823 GP_6_27_FN, GPSR6_27,
4824 GP_6_26_FN, GPSR6_26,
4825 GP_6_25_FN, GPSR6_25,
4826 GP_6_24_FN, GPSR6_24,
4827 GP_6_23_FN, GPSR6_23,
4828 GP_6_22_FN, GPSR6_22,
4829 GP_6_21_FN, GPSR6_21,
4830 GP_6_20_FN, GPSR6_20,
4831 GP_6_19_FN, GPSR6_19,
4832 GP_6_18_FN, GPSR6_18,
4833 GP_6_17_FN, GPSR6_17,
4834 GP_6_16_FN, GPSR6_16,
4835 GP_6_15_FN, GPSR6_15,
4836 GP_6_14_FN, GPSR6_14,
4837 GP_6_13_FN, GPSR6_13,
4838 GP_6_12_FN, GPSR6_12,
4839 GP_6_11_FN, GPSR6_11,
4840 GP_6_10_FN, GPSR6_10,
4841 GP_6_9_FN, GPSR6_9,
4842 GP_6_8_FN, GPSR6_8,
4843 GP_6_7_FN, GPSR6_7,
4844 GP_6_6_FN, GPSR6_6,
4845 GP_6_5_FN, GPSR6_5,
4846 GP_6_4_FN, GPSR6_4,
4847 GP_6_3_FN, GPSR6_3,
4848 GP_6_2_FN, GPSR6_2,
4849 GP_6_1_FN, GPSR6_1,
4850 GP_6_0_FN, GPSR6_0, }
4851 },
4852 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4853 0, 0,
4854 0, 0,
4855 0, 0,
4856 0, 0,
4857 0, 0,
4858 0, 0,
4859 0, 0,
4860 0, 0,
4861 0, 0,
4862 0, 0,
4863 0, 0,
4864 0, 0,
4865 0, 0,
4866 0, 0,
4867 0, 0,
4868 0, 0,
4869 0, 0,
4870 0, 0,
4871 0, 0,
4872 0, 0,
4873 0, 0,
4874 0, 0,
4875 0, 0,
4876 0, 0,
4877 0, 0,
4878 0, 0,
4879 0, 0,
4880 0, 0,
4881 GP_7_3_FN, GPSR7_3,
4882 GP_7_2_FN, GPSR7_2,
4883 GP_7_1_FN, GPSR7_1,
4884 GP_7_0_FN, GPSR7_0, }
4885 },
4886#undef F_
4887#undef FM
4888
4889#define F_(x, y) x,
4890#define FM(x) FN_##x,
4891 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4892 IP0_31_28
4893 IP0_27_24
4894 IP0_23_20
4895 IP0_19_16
4896 IP0_15_12
4897 IP0_11_8
4898 IP0_7_4
4899 IP0_3_0 }
4900 },
4901 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4902 IP1_31_28
4903 IP1_27_24
4904 IP1_23_20
4905 IP1_19_16
4906 IP1_15_12
4907 IP1_11_8
4908 IP1_7_4
4909 IP1_3_0 }
4910 },
4911 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4912 IP2_31_28
4913 IP2_27_24
4914 IP2_23_20
4915 IP2_19_16
4916 IP2_15_12
4917 IP2_11_8
4918 IP2_7_4
4919 IP2_3_0 }
4920 },
4921 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4922 IP3_31_28
4923 IP3_27_24
4924 IP3_23_20
4925 IP3_19_16
4926 IP3_15_12
4927 IP3_11_8
4928 IP3_7_4
4929 IP3_3_0 }
4930 },
4931 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4932 IP4_31_28
4933 IP4_27_24
4934 IP4_23_20
4935 IP4_19_16
4936 IP4_15_12
4937 IP4_11_8
4938 IP4_7_4
4939 IP4_3_0 }
4940 },
4941 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4942 IP5_31_28
4943 IP5_27_24
4944 IP5_23_20
4945 IP5_19_16
4946 IP5_15_12
4947 IP5_11_8
4948 IP5_7_4
4949 IP5_3_0 }
4950 },
4951 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4952 IP6_31_28
4953 IP6_27_24
4954 IP6_23_20
4955 IP6_19_16
4956 IP6_15_12
4957 IP6_11_8
4958 IP6_7_4
4959 IP6_3_0 }
4960 },
4961 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4962 IP7_31_28
4963 IP7_27_24
4964 IP7_23_20
4965 IP7_19_16
4966 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4967 IP7_11_8
4968 IP7_7_4
4969 IP7_3_0 }
4970 },
4971 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4972 IP8_31_28
4973 IP8_27_24
4974 IP8_23_20
4975 IP8_19_16
4976 IP8_15_12
4977 IP8_11_8
4978 IP8_7_4
4979 IP8_3_0 }
4980 },
4981 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4982 IP9_31_28
4983 IP9_27_24
4984 IP9_23_20
4985 IP9_19_16
4986 IP9_15_12
4987 IP9_11_8
4988 IP9_7_4
4989 IP9_3_0 }
4990 },
4991 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4992 IP10_31_28
4993 IP10_27_24
4994 IP10_23_20
4995 IP10_19_16
4996 IP10_15_12
4997 IP10_11_8
4998 IP10_7_4
4999 IP10_3_0 }
5000 },
5001 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5002 IP11_31_28
5003 IP11_27_24
5004 IP11_23_20
5005 IP11_19_16
5006 IP11_15_12
5007 IP11_11_8
5008 IP11_7_4
5009 IP11_3_0 }
5010 },
5011 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5012 IP12_31_28
5013 IP12_27_24
5014 IP12_23_20
5015 IP12_19_16
5016 IP12_15_12
5017 IP12_11_8
5018 IP12_7_4
5019 IP12_3_0 }
5020 },
5021 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5022 IP13_31_28
5023 IP13_27_24
5024 IP13_23_20
5025 IP13_19_16
5026 IP13_15_12
5027 IP13_11_8
5028 IP13_7_4
5029 IP13_3_0 }
5030 },
5031 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5032 IP14_31_28
5033 IP14_27_24
5034 IP14_23_20
5035 IP14_19_16
5036 IP14_15_12
5037 IP14_11_8
5038 IP14_7_4
5039 IP14_3_0 }
5040 },
5041 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5042 IP15_31_28
5043 IP15_27_24
5044 IP15_23_20
5045 IP15_19_16
5046 IP15_15_12
5047 IP15_11_8
5048 IP15_7_4
5049 IP15_3_0 }
5050 },
5051 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5052 IP16_31_28
5053 IP16_27_24
5054 IP16_23_20
5055 IP16_19_16
5056 IP16_15_12
5057 IP16_11_8
5058 IP16_7_4
5059 IP16_3_0 }
5060 },
5061 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5062 IP17_31_28
5063 IP17_27_24
5064 IP17_23_20
5065 IP17_19_16
5066 IP17_15_12
5067 IP17_11_8
5068 IP17_7_4
5069 IP17_3_0 }
5070 },
5071 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5072 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5073 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5074 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5075 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5076 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5077 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5078 IP18_7_4
5079 IP18_3_0 }
5080 },
5081#undef F_
5082#undef FM
5083
5084#define F_(x, y) x,
5085#define FM(x) FN_##x,
5086 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5087 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5088 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5089 MOD_SEL0_31_30_29
5090 MOD_SEL0_28_27
5091 MOD_SEL0_26_25_24
5092 MOD_SEL0_23
5093 MOD_SEL0_22
5094 MOD_SEL0_21
5095 MOD_SEL0_20
5096 MOD_SEL0_19
5097 MOD_SEL0_18_17
5098 MOD_SEL0_16
5099 0, 0, /* RESERVED 15 */
5100 MOD_SEL0_14_13
5101 MOD_SEL0_12
5102 MOD_SEL0_11
5103 MOD_SEL0_10
5104 MOD_SEL0_9_8
5105 MOD_SEL0_7_6
5106 MOD_SEL0_5
5107 MOD_SEL0_4_3
5108 /* RESERVED 2, 1, 0 */
5109 0, 0, 0, 0, 0, 0, 0, 0 }
5110 },
5111 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5112 2, 3, 1, 2, 3, 1, 1, 2, 1,
5113 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5114 MOD_SEL1_31_30
5115 MOD_SEL1_29_28_27
5116 MOD_SEL1_26
5117 MOD_SEL1_25_24
5118 MOD_SEL1_23_22_21
5119 MOD_SEL1_20
5120 MOD_SEL1_19
5121 MOD_SEL1_18_17
5122 MOD_SEL1_16
5123 MOD_SEL1_15_14
5124 MOD_SEL1_13
5125 MOD_SEL1_12
5126 MOD_SEL1_11
5127 MOD_SEL1_10
5128 MOD_SEL1_9
5129 0, 0, 0, 0, /* RESERVED 8, 7 */
5130 MOD_SEL1_6
5131 MOD_SEL1_5
5132 MOD_SEL1_4
5133 MOD_SEL1_3
5134 MOD_SEL1_2
5135 MOD_SEL1_1
5136 MOD_SEL1_0 }
5137 },
5138 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5139 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5140 4, 4, 4, 3, 1) {
5141 MOD_SEL2_31
5142 MOD_SEL2_30
5143 MOD_SEL2_29
5144 MOD_SEL2_28_27
5145 MOD_SEL2_26
5146 MOD_SEL2_25_24_23
5147 MOD_SEL2_22
5148 MOD_SEL2_21
5149 MOD_SEL2_20
5150 MOD_SEL2_19
5151 MOD_SEL2_18
5152 MOD_SEL2_17
5153 /* RESERVED 16 */
5154 0, 0,
5155 /* RESERVED 15, 14, 13, 12 */
5156 0, 0, 0, 0, 0, 0, 0, 0,
5157 0, 0, 0, 0, 0, 0, 0, 0,
5158 /* RESERVED 11, 10, 9, 8 */
5159 0, 0, 0, 0, 0, 0, 0, 0,
5160 0, 0, 0, 0, 0, 0, 0, 0,
5161 /* RESERVED 7, 6, 5, 4 */
5162 0, 0, 0, 0, 0, 0, 0, 0,
5163 0, 0, 0, 0, 0, 0, 0, 0,
5164 /* RESERVED 3, 2, 1 */
5165 0, 0, 0, 0, 0, 0, 0, 0,
5166 MOD_SEL2_0 }
5167 },
5168 { },
5169};
5170
5171static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5172 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5173 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5174 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5175 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5176 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5177 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5178 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5179 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5180 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5181 } },
5182 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5183 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5184 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5185 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5186 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5187 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5188 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5189 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5190 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5191 } },
5192 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5193 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5194 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5195 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5196 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5197 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5198 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5199 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5200 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5201 } },
5202 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5203 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5204 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5205 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5206 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5207 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5208 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5209 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5210 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5211 } },
5212 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5213 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5214 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5215 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5216 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5217 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5218 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5219 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5220 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5221 } },
5222 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5223 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5224 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5225 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5226 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5227 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5228 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5229 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5230 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5231 } },
5232 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5233 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5234 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5235 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5236 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5237 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5238 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5239 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5240 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5241 } },
5242 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5243 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5244 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5245 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5246 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5247 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5248 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5249 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5250 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5251 } },
5252 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5253 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5254 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5255 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5256 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5257 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5258 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5259 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5260 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5261 } },
5262 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5263 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5264 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5265 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5266 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5267 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5268 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5269 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5270 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5271 } },
5272 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5273 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5274 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5275 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5276 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5277 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5278 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5279 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5280 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5281 } },
5282 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5283 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5284 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5285 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5286 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5287 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5288 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5289 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5290 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5291 } },
5292 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5293 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
5294 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5295 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5296 } },
5297 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5298 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5299 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5300 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5301 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5302 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5303 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5304 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5305 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5306 } },
5307 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5308 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5309 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5310 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5311 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5312 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5313 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5314 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5315 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5316 } },
5317 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5318 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5319 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5320 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5321 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5322 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5323 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5324 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5325 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5326 } },
5327 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5328 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5329 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5330 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5331 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5332 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5333 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5334 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5335 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5336 } },
5337 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5338 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5339 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5340 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5341 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5342 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5343 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5344 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5345 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5346 } },
5347 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5348 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
5349 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5350 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5351 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5352 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
5353 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5354 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5355 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5356 } },
5357 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5358 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5359 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5360 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5361 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5362 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5363 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5364 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5365 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5366 } },
5367 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5368 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5369 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5370 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5371 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5372 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5373 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5374 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5375 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5376 } },
5377 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5378 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5379 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5380 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5381 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5382 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5383 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5384 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5385 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5386 } },
5387 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5388 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5389 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5390 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5391 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5392 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5393 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5394 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5395 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5396 } },
5397 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5398 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5399 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5400 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5401 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5402 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5403 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5404 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5405 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5406 } },
5407 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5408 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5409 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5410 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5411 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5412 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5413 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5414 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5415 } },
5416 { },
5417};
5418
5419static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5420{
5421 int bit = -EINVAL;
5422
5423 *pocctrl = 0xe6060380;
5424
5425 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5426 bit = pin & 0x1f;
5427
5428 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5429 bit = (pin & 0x1f) + 12;
5430
5431 return bit;
5432}
5433
5434#define PUEN 0xe6060400
5435#define PUD 0xe6060440
5436
5437#define PU0 0x00
5438#define PU1 0x04
5439#define PU2 0x08
5440#define PU3 0x0c
5441#define PU4 0x10
5442#define PU5 0x14
5443#define PU6 0x18
5444
5445static const struct sh_pfc_bias_info bias_info[] = {
5446 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
5447 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
5448 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
5449 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
5450 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
5451 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
5452 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
5453 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
5454 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
5455 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
5456 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
5457 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
5458 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
5459 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
5460 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
5461 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
5462 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
5463 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
5464 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
5465 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
5466 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
5467 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
5468 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
5469 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
5470 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
5471 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
5472 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
5473 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
5474 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
5475 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
5476 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
5477 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
5478
5479 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
5480 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
5481 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
5482 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
5483 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
5484 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
5485 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
5486 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
5487 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
5488 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
5489 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
5490 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
5491 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
5492 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
5493 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
5494 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
5495 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
5496 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
5497 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
5498 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
5499 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
5500 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
5501 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
5502 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
5503 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
5504 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
5505 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
5506 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
5507 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
5508 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
5509 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
5510 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
5511
5512 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
5513 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
5514 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */
5515 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
5516 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
5517 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
5518 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
5519 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
5520 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
5521 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
5522 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
5523 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
5524 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
5525 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
5526 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
5527 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
5528 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
5529 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
5530 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
5531 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
5532 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
5533 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
5534 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
5535 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
5536 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
5537 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
5538 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
5539 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
5540 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
5541 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
5542 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
5543 { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */
5544
5545 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
5546 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
5547 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
5548 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
5549 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
5550 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
5551 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
5552 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
5553 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
5554 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
5555 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
5556 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
5557 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
5558 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
5559 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
5560 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
5561 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
5562 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
5563 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
5564 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
5565 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
5566 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
5567 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
5568 /* bit 8 n/a */
5569 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
5570 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
5571 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
5572 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
5573 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
5574 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */
5575 /* bit 1 n/a on M3*/
5576 { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */
5577
5578 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
5579 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
5580 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
5581 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
5582 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
5583 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
5584 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
5585 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
5586 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
5587 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
5588 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
5589 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
5590 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
5591 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
5592 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
5593 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
5594 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
5595 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
5596 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
5597 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
5598 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
5599 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
5600 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
5601 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
5602 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
5603 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
5604 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
5605 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
5606 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
5607 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
5608 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
5609 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
5610
5611 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
5612 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
5613 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
5614 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
5615 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
5616 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
5617 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
5618 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
5619 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
5620 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
5621 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
5622 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
5623 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
5624 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
5625 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
5626 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
5627 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
5628 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
5629 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
5630 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
5631 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
5632 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
5633 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
5634 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
5635 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
5636 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
5637 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
5638 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
5639 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
5640 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
5641 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
5642 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
5643
5644 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */
5645 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */
5646 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
5647 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
5648 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
5649 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
5650 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
5651};
5652
5653static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
5654 unsigned int pin)
5655{
5656 const struct sh_pfc_bias_info *info;
5657 u32 reg;
5658 u32 bit;
5659
5660 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5661 if (!info)
5662 return PIN_CONFIG_BIAS_DISABLE;
5663
5664 reg = info->reg;
5665 bit = BIT(info->bit);
5666
5667 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
5668 return PIN_CONFIG_BIAS_DISABLE;
5669 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
5670 return PIN_CONFIG_BIAS_PULL_UP;
5671 else
5672 return PIN_CONFIG_BIAS_PULL_DOWN;
5673}
5674
5675static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5676 unsigned int bias)
5677{
5678 const struct sh_pfc_bias_info *info;
5679 u32 enable, updown;
5680 u32 reg;
5681 u32 bit;
5682
5683 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5684 if (!info)
5685 return;
5686
5687 reg = info->reg;
5688 bit = BIT(info->bit);
5689
5690 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5691 if (bias != PIN_CONFIG_BIAS_DISABLE)
5692 enable |= bit;
5693
5694 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
5695 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5696 updown |= bit;
5697
5698 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
5699 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
5700}
5701
5702static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
5703 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
5704 .get_bias = r8a7796_pinmux_get_bias,
5705 .set_bias = r8a7796_pinmux_set_bias,
5706};
5707
5708const struct sh_pfc_soc_info r8a7796_pinmux_info = {
5709 .name = "r8a77960_pfc",
5710 .ops = &r8a7796_pinmux_ops,
5711 .unlock_reg = 0xe6060000, /* PMMR */
5712
5713 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5714
5715 .pins = pinmux_pins,
5716 .nr_pins = ARRAY_SIZE(pinmux_pins),
5717 .groups = pinmux_groups,
5718 .nr_groups = ARRAY_SIZE(pinmux_groups),
5719 .functions = pinmux_functions,
5720 .nr_functions = ARRAY_SIZE(pinmux_functions),
5721
5722 .cfg_regs = pinmux_config_regs,
5723 .drive_regs = pinmux_drive_regs,
5724
5725 .pinmux_data = pinmux_data,
5726 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5727};