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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Tom Warren795f9d72013-01-23 14:01:01 -07002/*
Thierry Redingce7eb162019-04-15 11:32:25 +02003 * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
Tom Warren795f9d72013-01-23 14:01:01 -07004 */
5
6/* Tegra SoC common clock control functions */
7
Simon Glass15023922017-06-12 06:21:39 -06008#include <div64.h>
9#include <dm.h>
Simon Glasscd4b59b2015-06-05 14:39:36 -060010#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glass495a5dc2019-11-14 12:57:30 -070012#include <time.h>
Tom Warren795f9d72013-01-23 14:01:01 -070013#include <asm/io.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/tegra.h>
Stephen Warren8d1fb312015-01-19 16:25:52 -070016#include <asm/arch-tegra/ap.h>
Tom Warren795f9d72013-01-23 14:01:01 -070017#include <asm/arch-tegra/clk_rst.h>
Simon Glasscd4b59b2015-06-05 14:39:36 -060018#include <asm/arch-tegra/pmc.h>
Tom Warren795f9d72013-01-23 14:01:01 -070019#include <asm/arch-tegra/timer.h>
Simon Glassdbd79542020-05-10 11:40:11 -060020#include <linux/delay.h>
Tom Warren795f9d72013-01-23 14:01:01 -070021
22/*
23 * This is our record of the current clock rate of each clock. We don't
24 * fill all of these in since we are only really interested in clocks which
25 * we use as parents.
26 */
27static unsigned pll_rate[CLOCK_ID_COUNT];
28
29/*
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +020030 * The oscillator frequency is fixed to one of seven set values. Based on this
Tom Warren795f9d72013-01-23 14:01:01 -070031 * the other clocks are set up appropriately.
32 */
33static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
34 13000000,
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +020035 16800000,
36 0,
37 0,
Tom Warren795f9d72013-01-23 14:01:01 -070038 19200000,
Tom Warren27bce712015-06-22 13:03:44 -070039 38400000,
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +020040 0,
41 0,
42 12000000,
Tom Warren27bce712015-06-22 13:03:44 -070043 48000000,
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +020044 0,
45 0,
46 26000000,
Tom Warren795f9d72013-01-23 14:01:01 -070047};
48
49/* return 1 if a peripheral ID is in range */
50#define clock_type_id_isvalid(id) ((id) >= 0 && \
51 (id) < CLOCK_TYPE_COUNT)
52
53char pllp_valid = 1; /* PLLP is set up correctly */
54
55/* return 1 if a periphc_internal_id is in range */
56#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
57 (id) < PERIPHC_COUNT)
58
59/* number of clock outputs of a PLL */
60static const u8 pll_num_clkouts[] = {
61 1, /* PLLC */
62 1, /* PLLM */
63 4, /* PLLP */
64 1, /* PLLA */
65 0, /* PLLU */
66 0, /* PLLD */
67};
68
69int clock_get_osc_bypass(void)
70{
71 struct clk_rst_ctlr *clkrst =
72 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
73 u32 reg;
74
75 reg = readl(&clkrst->crc_osc_ctrl);
76 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
77}
78
79/* Returns a pointer to the registers of the given pll */
80static struct clk_pll *get_pll(enum clock_id clkid)
81{
82 struct clk_rst_ctlr *clkrst =
83 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
84
85 assert(clock_id_is_pll(clkid));
Simon Glass6017b9a2015-04-14 21:03:32 -060086 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
Simon Glass31689872015-06-05 14:39:37 -060087 debug("%s: Invalid PLL %d\n", __func__, clkid);
Simon Glass6017b9a2015-04-14 21:03:32 -060088 return NULL;
89 }
Tom Warren795f9d72013-01-23 14:01:01 -070090 return &clkrst->crc_pll[clkid];
91}
92
Simon Glass6017b9a2015-04-14 21:03:32 -060093__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
94{
95 return NULL;
96}
97
Tom Warren795f9d72013-01-23 14:01:01 -070098int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
99 u32 *divp, u32 *cpcon, u32 *lfcon)
100{
101 struct clk_pll *pll = get_pll(clkid);
Tom Warrena8480ef2015-06-25 09:50:44 -0700102 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Tom Warren795f9d72013-01-23 14:01:01 -0700103 u32 data;
104
105 assert(clkid != CLOCK_ID_USB);
106
107 /* Safety check, adds to code size but is small */
108 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
109 return -1;
110 data = readl(&pll->pll_base);
Tom Warrena8480ef2015-06-25 09:50:44 -0700111 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
112 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
113 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
Tom Warren795f9d72013-01-23 14:01:01 -0700114 data = readl(&pll->pll_misc);
Tom Warrena8480ef2015-06-25 09:50:44 -0700115 /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
116 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
117 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
118
Tom Warren795f9d72013-01-23 14:01:01 -0700119 return 0;
120}
121
122unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
123 u32 divp, u32 cpcon, u32 lfcon)
124{
Simon Glass31689872015-06-05 14:39:37 -0600125 struct clk_pll *pll = NULL;
Tom Warrena8480ef2015-06-25 09:50:44 -0700126 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600127 struct clk_pll_simple *simple_pll = NULL;
Simon Glass6017b9a2015-04-14 21:03:32 -0600128 u32 misc_data, data;
Tom Warren795f9d72013-01-23 14:01:01 -0700129
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300130 if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
Simon Glass31689872015-06-05 14:39:37 -0600131 pll = get_pll(clkid);
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300132 else
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600133 simple_pll = clock_get_simple_pll(clkid);
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300134
135 if (!simple_pll && !pll) {
136 log_err("Unknown PLL id %d\n", clkid);
137 return 0;
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600138 }
Simon Glass31689872015-06-05 14:39:37 -0600139
Tom Warren795f9d72013-01-23 14:01:01 -0700140 /*
Tom Warrena8480ef2015-06-25 09:50:44 -0700141 * pllinfo has the m/n/p and kcp/kvco mask and shift
142 * values for all of the PLLs used in U-Boot, with any
143 * SoC differences accounted for.
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600144 *
145 * Preserve EN_LOCKDET, etc.
Tom Warren795f9d72013-01-23 14:01:01 -0700146 */
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600147 if (pll)
148 misc_data = readl(&pll->pll_misc);
149 else
150 misc_data = readl(&simple_pll->pll_misc);
151 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
152 misc_data |= cpcon << pllinfo->kcp_shift;
153 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
154 misc_data |= lfcon << pllinfo->kvco_shift;
Tom Warren795f9d72013-01-23 14:01:01 -0700155
Tom Warrena8480ef2015-06-25 09:50:44 -0700156 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
157 data |= divp << pllinfo->p_shift;
158 data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
Tom Warren795f9d72013-01-23 14:01:01 -0700159
Simon Glass6017b9a2015-04-14 21:03:32 -0600160 if (pll) {
161 writel(misc_data, &pll->pll_misc);
162 writel(data, &pll->pll_base);
163 } else {
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600164 writel(misc_data, &simple_pll->pll_misc);
165 writel(data, &simple_pll->pll_base);
Simon Glass6017b9a2015-04-14 21:03:32 -0600166 }
Tom Warren795f9d72013-01-23 14:01:01 -0700167
168 /* calculate the stable time */
169 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
170}
171
172void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
173 unsigned divisor)
174{
175 u32 *reg = get_periph_source_reg(periph_id);
176 u32 value;
177
178 value = readl(reg);
179
Stephen Warrendf5ed452014-01-24 10:16:19 -0700180 value &= ~OUT_CLK_SOURCE_31_30_MASK;
181 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
Tom Warren795f9d72013-01-23 14:01:01 -0700182
183 value &= ~OUT_CLK_DIVISOR_MASK;
184 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
185
186 writel(value, reg);
187}
188
Simon Glassd2d1c3f2015-04-14 21:03:33 -0600189int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
190 unsigned source)
Tom Warren795f9d72013-01-23 14:01:01 -0700191{
192 u32 *reg = get_periph_source_reg(periph_id);
193
Simon Glassd2d1c3f2015-04-14 21:03:33 -0600194 switch (mux_bits) {
195 case MASK_BITS_31_30:
196 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
197 source << OUT_CLK_SOURCE_31_30_SHIFT);
198 break;
199
200 case MASK_BITS_31_29:
201 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
202 source << OUT_CLK_SOURCE_31_29_SHIFT);
203 break;
204
205 case MASK_BITS_31_28:
206 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
207 source << OUT_CLK_SOURCE_31_28_SHIFT);
208 break;
209
210 default:
211 return -1;
212 }
213
214 return 0;
Tom Warren795f9d72013-01-23 14:01:01 -0700215}
216
Stephen Warren532543c2016-09-13 10:45:56 -0600217static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
218{
219 u32 *reg = get_periph_source_reg(periph_id);
220 u32 val = readl(reg);
221
222 switch (mux_bits) {
223 case MASK_BITS_31_30:
224 val >>= OUT_CLK_SOURCE_31_30_SHIFT;
225 val &= OUT_CLK_SOURCE_31_30_MASK;
226 return val;
227 case MASK_BITS_31_29:
228 val >>= OUT_CLK_SOURCE_31_29_SHIFT;
229 val &= OUT_CLK_SOURCE_31_29_MASK;
230 return val;
231 case MASK_BITS_31_28:
232 val >>= OUT_CLK_SOURCE_31_28_SHIFT;
233 val &= OUT_CLK_SOURCE_31_28_MASK;
234 return val;
235 default:
236 return -1;
237 }
238}
239
Simon Glassd2d1c3f2015-04-14 21:03:33 -0600240void clock_ll_set_source(enum periph_id periph_id, unsigned source)
241{
242 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
243}
244
Tom Warren795f9d72013-01-23 14:01:01 -0700245/**
246 * Given the parent's rate and the required rate for the children, this works
247 * out the peripheral clock divider to use, in 7.1 binary format.
248 *
249 * @param divider_bits number of divider bits (8 or 16)
250 * @param parent_rate clock rate of parent clock in Hz
251 * @param rate required clock rate for this clock
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100252 * Return: divider which should be used
Tom Warren795f9d72013-01-23 14:01:01 -0700253 */
254static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
255 unsigned long rate)
256{
257 u64 divider = parent_rate * 2;
258 unsigned max_divider = 1 << divider_bits;
259
260 divider += rate - 1;
261 do_div(divider, rate);
262
263 if ((s64)divider - 2 < 0)
264 return 0;
265
266 if ((s64)divider - 2 >= max_divider)
267 return -1;
268
269 return divider - 2;
270}
271
272int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
273{
274 struct clk_pll *pll = get_pll(clkid);
275 int data = 0, div = 0, offset = 0;
276
277 if (!clock_id_is_pll(clkid))
278 return -1;
279
280 if (pllout + 1 > pll_num_clkouts[clkid])
281 return -1;
282
283 div = clk_get_divider(8, pll_rate[clkid], rate);
284
285 if (div < 0)
286 return -1;
287
288 /* out2 and out4 are in the high part of the register */
289 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
290 offset = 16;
291
292 data = (div << PLL_OUT_RATIO_SHIFT) |
293 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
294 clrsetbits_le32(&pll->pll_out[pllout >> 1],
295 PLL_OUT_RATIO_MASK << offset, data << offset);
296
297 return 0;
298}
299
300/**
301 * Given the parent's rate and the divider in 7.1 format, this works out the
302 * resulting peripheral clock rate.
303 *
304 * @param parent_rate clock rate of parent clock in Hz
305 * @param divider which should be used in 7.1 format
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100306 * Return: effective clock rate of peripheral
Tom Warren795f9d72013-01-23 14:01:01 -0700307 */
308static unsigned long get_rate_from_divider(unsigned long parent_rate,
309 int divider)
310{
311 u64 rate;
312
313 rate = (u64)parent_rate * 2;
314 do_div(rate, divider + 2);
315 return rate;
316}
317
318unsigned long clock_get_periph_rate(enum periph_id periph_id,
319 enum clock_id parent)
320{
321 u32 *reg = get_periph_source_reg(periph_id);
Stephen Warrene331b202016-09-23 16:44:51 -0600322 unsigned parent_rate = pll_rate[parent];
323 int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT;
324
325 switch (periph_id) {
326 case PERIPH_ID_UART1:
327 case PERIPH_ID_UART2:
328 case PERIPH_ID_UART3:
329 case PERIPH_ID_UART4:
330 case PERIPH_ID_UART5:
331#ifdef CONFIG_TEGRA20
332 /* There's no divider for these clocks in this SoC. */
333 return parent_rate;
334#else
335 /*
336 * This undoes the +2 in get_rate_from_divider() which I
337 * believe is incorrect. Ideally we would fix
338 * get_rate_from_divider(), but... Removing the +2 from
339 * get_rate_from_divider() would probably require remove the -2
340 * from the tail of clk_get_divider() since I believe that's
341 * only there to invert get_rate_from_divider()'s +2. Observe
342 * how find_best_divider() uses those two functions together.
343 * However, doing so breaks other stuff, such as Seaboard's
344 * display, likely due to clock_set_pllout()'s call to
345 * clk_get_divider(). Attempting to fix that by making
346 * clock_set_pllout() subtract 2 from clk_get_divider()'s
347 * return value doesn't help. In summary this clock driver is
348 * quite broken but I'm afraid I have no idea how to fix it
349 * without completely replacing it.
Simon Glass86b89fd2017-05-31 17:57:22 -0600350 *
351 * Be careful to avoid a divide by zero error.
Stephen Warrene331b202016-09-23 16:44:51 -0600352 */
Simon Glass86b89fd2017-05-31 17:57:22 -0600353 if (div >= 1)
354 div -= 2;
Stephen Warrene331b202016-09-23 16:44:51 -0600355 break;
356#endif
357 default:
358 break;
359 }
Tom Warren795f9d72013-01-23 14:01:01 -0700360
Stephen Warrene331b202016-09-23 16:44:51 -0600361 return get_rate_from_divider(parent_rate, div);
Tom Warren795f9d72013-01-23 14:01:01 -0700362}
363
364/**
365 * Find the best available 7.1 format divisor given a parent clock rate and
366 * required child clock rate. This function assumes that a second-stage
367 * divisor is available which can divide by powers of 2 from 1 to 256.
368 *
369 * @param divider_bits number of divider bits (8 or 16)
370 * @param parent_rate clock rate of parent clock in Hz
371 * @param rate required clock rate for this clock
372 * @param extra_div value for the second-stage divisor (not set if this
373 * function returns -1.
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100374 * Return: divider which should be used, or -1 if nothing is valid
Tom Warren795f9d72013-01-23 14:01:01 -0700375 *
376 */
377static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
378 unsigned long rate, int *extra_div)
379{
380 int shift;
381 int best_divider = -1;
382 int best_error = rate;
383
384 /* try dividers from 1 to 256 and find closest match */
385 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
386 unsigned divided_parent = parent_rate >> shift;
387 int divider = clk_get_divider(divider_bits, divided_parent,
388 rate);
389 unsigned effective_rate = get_rate_from_divider(divided_parent,
390 divider);
391 int error = rate - effective_rate;
392
393 /* Given a valid divider, look for the lowest error */
394 if (divider != -1 && error < best_error) {
395 best_error = error;
396 *extra_div = 1 << shift;
397 best_divider = divider;
398 }
399 }
400
401 /* return what we found - *extra_div will already be set */
402 return best_divider;
403}
404
405/**
406 * Adjust peripheral PLL to use the given divider and source.
407 *
408 * @param periph_id peripheral to adjust
409 * @param source Source number (0-3 or 0-7)
410 * @param mux_bits Number of mux bits (2 or 4)
411 * @param divider Required divider in 7.1 or 15.1 format
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100412 * Return: 0 if ok, -1 on error (requesting a parent clock which is not valid
Tom Warren795f9d72013-01-23 14:01:01 -0700413 * for this peripheral)
414 */
415static int adjust_periph_pll(enum periph_id periph_id, int source,
416 int mux_bits, unsigned divider)
417{
418 u32 *reg = get_periph_source_reg(periph_id);
419
420 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
421 divider << OUT_CLK_DIVISOR_SHIFT);
422 udelay(1);
423
424 /* work out the source clock and set it */
425 if (source < 0)
426 return -1;
Tom Warren2fde44e2014-01-24 10:16:22 -0700427
Simon Glassd2d1c3f2015-04-14 21:03:33 -0600428 clock_ll_set_source_bits(periph_id, mux_bits, source);
Tom Warren2fde44e2014-01-24 10:16:22 -0700429
Tom Warren795f9d72013-01-23 14:01:01 -0700430 udelay(2);
431 return 0;
432}
433
Stephen Warren532543c2016-09-13 10:45:56 -0600434enum clock_id clock_get_periph_parent(enum periph_id periph_id)
435{
436 int err, mux_bits, divider_bits, type;
437 int source;
438
439 err = get_periph_clock_info(periph_id, &mux_bits, &divider_bits, &type);
440 if (err)
441 return CLOCK_ID_NONE;
442
443 source = clock_ll_get_source_bits(periph_id, mux_bits);
444
445 return get_periph_clock_id(periph_id, source);
446}
447
Tom Warren795f9d72013-01-23 14:01:01 -0700448unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
449 enum clock_id parent, unsigned rate, int *extra_div)
450{
451 unsigned effective_rate;
452 int mux_bits, divider_bits, source;
453 int divider;
Allen Martin810a4e42013-05-10 16:56:55 +0000454 int xdiv = 0;
Tom Warren795f9d72013-01-23 14:01:01 -0700455
456 /* work out the source clock and set it */
457 source = get_periph_clock_source(periph_id, parent, &mux_bits,
458 &divider_bits);
459
Allen Martin810a4e42013-05-10 16:56:55 +0000460 divider = find_best_divider(divider_bits, pll_rate[parent],
461 rate, &xdiv);
Tom Warren795f9d72013-01-23 14:01:01 -0700462 if (extra_div)
Allen Martin810a4e42013-05-10 16:56:55 +0000463 *extra_div = xdiv;
464
Tom Warren795f9d72013-01-23 14:01:01 -0700465 assert(divider >= 0);
466 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
467 return -1U;
468 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
469 get_periph_source_reg(periph_id),
470 readl(get_periph_source_reg(periph_id)));
471
472 /* Check what we ended up with. This shouldn't matter though */
473 effective_rate = clock_get_periph_rate(periph_id, parent);
474 if (extra_div)
475 effective_rate /= *extra_div;
476 if (rate != effective_rate)
477 debug("Requested clock rate %u not honored (got %u)\n",
478 rate, effective_rate);
479 return effective_rate;
480}
481
482unsigned clock_start_periph_pll(enum periph_id periph_id,
483 enum clock_id parent, unsigned rate)
484{
485 unsigned effective_rate;
486
487 reset_set_enable(periph_id, 1);
488 clock_enable(periph_id);
Simon Glass1a62f102019-04-01 13:38:38 -0700489 udelay(2);
Tom Warren795f9d72013-01-23 14:01:01 -0700490
491 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
492 NULL);
493
494 reset_set_enable(periph_id, 0);
495 return effective_rate;
496}
497
498void clock_enable(enum periph_id clkid)
499{
500 clock_set_enable(clkid, 1);
501}
502
503void clock_disable(enum periph_id clkid)
504{
505 clock_set_enable(clkid, 0);
506}
507
508void reset_periph(enum periph_id periph_id, int us_delay)
509{
510 /* Put peripheral into reset */
511 reset_set_enable(periph_id, 1);
512 udelay(us_delay);
513
514 /* Remove reset */
515 reset_set_enable(periph_id, 0);
516
517 udelay(us_delay);
518}
519
520void reset_cmplx_set_enable(int cpu, int which, int reset)
521{
522 struct clk_rst_ctlr *clkrst =
523 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
524 u32 mask;
525
526 /* Form the mask, which depends on the cpu chosen (2 or 4) */
527 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
528 mask = which << cpu;
529
530 /* either enable or disable those reset for that CPU */
531 if (reset)
532 writel(mask, &clkrst->crc_cpu_cmplx_set);
533 else
534 writel(mask, &clkrst->crc_cpu_cmplx_clr);
535}
536
Thierry Redingfa6e24d2015-08-20 11:42:19 +0200537unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
538{
539 return parent_rate;
540}
541
Tom Warren795f9d72013-01-23 14:01:01 -0700542unsigned clock_get_rate(enum clock_id clkid)
543{
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300544 struct clk_pll *pll = NULL;
545 struct clk_pll_simple *simple_pll = NULL;
Tom Warrena8480ef2015-06-25 09:50:44 -0700546 u32 base, divm;
547 u64 parent_rate, rate;
548 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Tom Warren795f9d72013-01-23 14:01:01 -0700549
550 parent_rate = osc_freq[clock_get_osc_freq()];
551 if (clkid == CLOCK_ID_OSC)
552 return parent_rate;
553
Thierry Redingfa6e24d2015-08-20 11:42:19 +0200554 if (clkid == CLOCK_ID_CLK_M)
555 return clk_m_get_rate(parent_rate);
556
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300557 if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
558 pll = get_pll(clkid);
559 else
560 simple_pll = clock_get_simple_pll(clkid);
561
562 if (!simple_pll && !pll) {
563 log_err("Unknown PLL id %d\n", clkid);
Simon Glass6017b9a2015-04-14 21:03:32 -0600564 return 0;
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300565 }
566
567 if (pll)
568 base = readl(&pll->pll_base);
569 else
570 base = readl(&simple_pll->pll_base);
Tom Warren795f9d72013-01-23 14:01:01 -0700571
Tom Warrena8480ef2015-06-25 09:50:44 -0700572 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
573 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
574 /*
575 * PLLU uses p_mask/p_shift for VCO on all but T210,
576 * T210 uses normal DIVP. Handled in pllinfo table.
577 */
Stephen Warrenb1c6a8a2015-08-19 17:03:59 -0600578#ifdef CONFIG_TEGRA210
579 /*
580 * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
581 * not applied. pllP_out2 does have divp applied. All other pllP_outN
582 * are divided down from pllP_out0. We only support pllP_out0 in
583 * U-Boot at the time of writing this comment.
584 */
585 if (clkid != CLOCK_ID_PERIPH)
586#endif
587 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
Tom Warren795f9d72013-01-23 14:01:01 -0700588 do_div(rate, divm);
589 return rate;
590}
591
592/**
593 * Set the output frequency you want for each PLL clock.
594 * PLL output frequencies are programmed by setting their N, M and P values.
595 * The governing equations are:
596 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
597 * where Fo is the output frequency from the PLL.
598 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
599 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
600 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
601 *
602 * @param n PLL feedback divider(DIVN)
603 * @param m PLL input divider(DIVN)
604 * @param p post divider(DIVP)
605 * @param cpcon base PLL charge pump(CPCON)
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100606 * Return: 0 if ok, -1 on error (the requested PLL is incorrect and cannot
Robert P. J. Day8d56db92016-07-15 13:44:45 -0400607 * be overridden), 1 if PLL is already correct
Tom Warren795f9d72013-01-23 14:01:01 -0700608 */
609int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
610{
Tom Warrena8480ef2015-06-25 09:50:44 -0700611 u32 base_reg, misc_reg;
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300612 struct clk_pll *pll = NULL;
613 struct clk_pll_simple *simple_pll = NULL;
Tom Warrena8480ef2015-06-25 09:50:44 -0700614 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Tom Warren795f9d72013-01-23 14:01:01 -0700615
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300616 if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
617 pll = get_pll(clkid);
618 else
619 simple_pll = clock_get_simple_pll(clkid);
620
621 if (!simple_pll && !pll) {
622 log_err("Unknown PLL id %d\n", clkid);
623 return 0;
624 }
Tom Warren795f9d72013-01-23 14:01:01 -0700625
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300626 if (pll)
627 base_reg = readl(&pll->pll_base);
628 else
629 base_reg = readl(&simple_pll->pll_base);
Tom Warren795f9d72013-01-23 14:01:01 -0700630
631 /* Set BYPASS, m, n and p to PLL_BASE */
Tom Warrena8480ef2015-06-25 09:50:44 -0700632 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
633 base_reg |= m << pllinfo->m_shift;
Tom Warren795f9d72013-01-23 14:01:01 -0700634
Tom Warrena8480ef2015-06-25 09:50:44 -0700635 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
636 base_reg |= n << pllinfo->n_shift;
Tom Warren795f9d72013-01-23 14:01:01 -0700637
Tom Warrena8480ef2015-06-25 09:50:44 -0700638 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
639 base_reg |= p << pllinfo->p_shift;
Tom Warren795f9d72013-01-23 14:01:01 -0700640
641 if (clkid == CLOCK_ID_PERIPH) {
642 /*
643 * If the PLL is already set up, check that it is correct
644 * and record this info for clock_verify() to check.
645 */
646 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
647 base_reg |= PLL_ENABLE_MASK;
648 if (base_reg != readl(&pll->pll_base))
649 pllp_valid = 0;
650 return pllp_valid ? 1 : -1;
651 }
652 base_reg |= PLL_BASE_OVRRIDE_MASK;
653 }
654
655 base_reg |= PLL_BYPASS_MASK;
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300656 if (pll)
657 writel(base_reg, &pll->pll_base);
658 else
659 writel(base_reg, &simple_pll->pll_base);
Tom Warren795f9d72013-01-23 14:01:01 -0700660
Tom Warrena8480ef2015-06-25 09:50:44 -0700661 /* Set cpcon (KCP) to PLL_MISC */
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300662 if (pll)
663 misc_reg = readl(&pll->pll_misc);
664 else
665 misc_reg = readl(&simple_pll->pll_misc);
666
Tom Warrena8480ef2015-06-25 09:50:44 -0700667 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
668 misc_reg |= cpcon << pllinfo->kcp_shift;
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300669 if (pll)
670 writel(misc_reg, &pll->pll_misc);
671 else
672 writel(misc_reg, &simple_pll->pll_misc);
Tom Warren795f9d72013-01-23 14:01:01 -0700673
674 /* Enable PLL */
675 base_reg |= PLL_ENABLE_MASK;
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300676 if (pll)
677 writel(base_reg, &pll->pll_base);
678 else
679 writel(base_reg, &simple_pll->pll_base);
Tom Warren795f9d72013-01-23 14:01:01 -0700680
681 /* Disable BYPASS */
682 base_reg &= ~PLL_BYPASS_MASK;
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300683 if (pll)
684 writel(base_reg, &pll->pll_base);
685 else
686 writel(base_reg, &simple_pll->pll_base);
Tom Warren795f9d72013-01-23 14:01:01 -0700687
688 return 0;
689}
690
691void clock_ll_start_uart(enum periph_id periph_id)
692{
693 /* Assert UART reset and enable clock */
694 reset_set_enable(periph_id, 1);
695 clock_enable(periph_id);
696 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
697
698 /* wait for 2us */
699 udelay(2);
700
701 /* De-assert reset to UART */
702 reset_set_enable(periph_id, 0);
703}
704
Masahiro Yamada366b24f2015-08-12 07:31:55 +0900705#if CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glassc3f26502017-07-25 08:30:00 -0600706int clock_decode_periph_id(struct udevice *dev)
Tom Warren795f9d72013-01-23 14:01:01 -0700707{
708 enum periph_id id;
709 u32 cell[2];
710 int err;
711
Simon Glassc3f26502017-07-25 08:30:00 -0600712 err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
Tom Warren795f9d72013-01-23 14:01:01 -0700713 if (err)
714 return -1;
715 id = clk_id_to_periph_id(cell[1]);
716 assert(clock_periph_id_isvalid(id));
717 return id;
718}
Svyatoslav Ryhelb6e50b82023-02-14 19:35:26 +0200719
720/*
721 * Get periph clock id and its parent from device tree.
722 *
723 * @param dev udevice associated with FDT node
724 * @param clk_id pointer to u32 array of 2 values
725 * first is periph clock, second is
726 * its PLL parent according to FDT.
727 */
728int clock_decode_pair(struct udevice *dev, int *clk_id)
729{
730 u32 cell[4];
731 int err;
732
733 err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
734 if (err)
735 return -EINVAL;
736
737 clk_id[0] = clk_id_to_periph_id(cell[1]);
738 clk_id[1] = clk_id_to_pll_id(cell[3]);
739
740 return 0;
741}
Masahiro Yamada366b24f2015-08-12 07:31:55 +0900742#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
Tom Warren795f9d72013-01-23 14:01:01 -0700743
744int clock_verify(void)
745{
746 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
747 u32 reg = readl(&pll->pll_base);
748
749 if (!pllp_valid) {
750 printf("Warning: PLLP %x is not correct\n", reg);
751 return -1;
752 }
753 debug("PLLP %x is correct\n", reg);
754 return 0;
755}
756
757void clock_init(void)
758{
Stephen Warren1453d102016-09-13 10:45:55 -0600759 int i;
760
Tom Warren27bce712015-06-22 13:03:44 -0700761 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
Tom Warren795f9d72013-01-23 14:01:01 -0700762 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
763 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
Tom Warren27bce712015-06-22 13:03:44 -0700764 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
Simon Glass93a19952015-04-14 21:03:34 -0600765 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
Tom Warren795f9d72013-01-23 14:01:01 -0700766 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
Tom Warren27bce712015-06-22 13:03:44 -0700767 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
768 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
Thierry Redingfa6e24d2015-08-20 11:42:19 +0200769 pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
Svyatoslav Ryhel6af975c2023-07-03 18:11:58 +0300770#ifndef CONFIG_TEGRA20
771 pll_rate[CLOCK_ID_DISPLAY2] = clock_get_rate(CLOCK_ID_DISPLAY2);
772#endif
Tom Warren27bce712015-06-22 13:03:44 -0700773
Tom Warren795f9d72013-01-23 14:01:01 -0700774 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
Thierry Redingfa6e24d2015-08-20 11:42:19 +0200775 debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
Tom Warren27bce712015-06-22 13:03:44 -0700776 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
Tom Warren795f9d72013-01-23 14:01:01 -0700777 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
778 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
Tom Warren27bce712015-06-22 13:03:44 -0700779 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
Simon Glass93a19952015-04-14 21:03:34 -0600780 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
Tom Warren795f9d72013-01-23 14:01:01 -0700781 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
Stephen Warren1453d102016-09-13 10:45:55 -0600782
783 for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
784 enum periph_id periph_id;
785 enum clock_id parent;
786 int source, mux_bits, divider_bits;
787
788 periph_id = periph_clk_init_table[i].periph_id;
789 parent = periph_clk_init_table[i].parent_clock_id;
790
791 source = get_periph_clock_source(periph_id, parent, &mux_bits,
792 &divider_bits);
793 clock_ll_set_source_bits(periph_id, mux_bits, source);
794 }
Tom Warren795f9d72013-01-23 14:01:01 -0700795}
Jimmy Zhang2a544db2014-01-24 10:37:36 -0700796
797static void set_avp_clock_source(u32 src)
798{
799 struct clk_rst_ctlr *clkrst =
800 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
801 u32 val;
802
803 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
804 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
805 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
806 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
807 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
808 writel(val, &clkrst->crc_sclk_brst_pol);
809 udelay(3);
810}
811
812/*
813 * This function is useful on Tegra30, and any later SoCs that have compatible
814 * PLLP configuration registers.
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700815 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
Jimmy Zhang2a544db2014-01-24 10:37:36 -0700816 */
817void tegra30_set_up_pllp(void)
818{
819 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
820 u32 reg;
821
822 /*
823 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
824 * run up to 275MHz. On power on, the default sytem clock source is set
825 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
826 * 408MHz which is beyond system clock's upper limit.
827 *
828 * The fix is to set the system clock to CLK_M before initializing PLLP,
829 * and then switch back to PLLP_OUT4, which has an appropriate divider
830 * configured, after PLLP has been configured
831 */
832 set_avp_clock_source(SCLK_SOURCE_CLKM);
833
834 /*
835 * PLLP output frequency set to 408Mhz
836 * PLLC output frequency set to 228Mhz
837 */
838 switch (clock_get_osc_freq()) {
839 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200840 case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
Jimmy Zhang2a544db2014-01-24 10:37:36 -0700841 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
842 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
843 break;
844
845 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
846 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
847 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
848 break;
849
850 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200851 case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
Jimmy Zhang2a544db2014-01-24 10:37:36 -0700852 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
853 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
854 break;
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200855
Jimmy Zhang2a544db2014-01-24 10:37:36 -0700856 case CLOCK_OSC_FREQ_19_2:
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200857 case CLOCK_OSC_FREQ_38_4:
Jimmy Zhang2a544db2014-01-24 10:37:36 -0700858 default:
859 /*
860 * These are not supported. It is too early to print a
861 * message and the UART likely won't work anyway due to the
862 * oscillator being wrong.
863 */
864 break;
865 }
866
867 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
868
869 /* OUT1, 2 */
870 /* Assert RSTN before enable */
871 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
872 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
873 /* Set divisor and reenable */
874 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
875 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
876 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
877 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
878 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
879
880 /* OUT3, 4 */
881 /* Assert RSTN before enable */
882 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
883 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
884 /* Set divisor and reenable */
885 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
886 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
887 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
888 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
889 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
890
891 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
892}
Simon Glasscd4b59b2015-06-05 14:39:36 -0600893
894int clock_external_output(int clk_id)
895{
Thierry Redingce7eb162019-04-15 11:32:25 +0200896 u32 val;
Simon Glasscd4b59b2015-06-05 14:39:36 -0600897
898 if (clk_id >= 1 && clk_id <= 3) {
Thierry Redingce7eb162019-04-15 11:32:25 +0200899 val = tegra_pmc_readl(offsetof(struct pmc_ctlr,
900 pmc_clk_out_cntrl));
901 val |= 1 << (2 + (clk_id - 1) * 8);
902 tegra_pmc_writel(val,
903 offsetof(struct pmc_ctlr,
904 pmc_clk_out_cntrl));
905
Simon Glasscd4b59b2015-06-05 14:39:36 -0600906 } else {
907 printf("%s: Unknown output clock id %d\n", __func__, clk_id);
908 return -EINVAL;
909 }
910
911 return 0;
912}
Simon Glass2b4029a2017-05-31 17:57:16 -0600913
914__weak bool clock_early_init_done(void)
915{
916 return true;
917}