| Green Wan | 7f33743 | 2021-05-27 06:52:07 -0700 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
| 2 | # |
| 3 | # Copyright (C) 2020-2021 SiFive, Inc |
| 4 | # Pragnesh Patel <pragnesh.patel@sifive.com> |
| 5 | |
| 6 | config SIFIVE_FU740 |
| 7 | bool |
| 8 | select ARCH_EARLY_INIT_R |
| 9 | select RAM |
| 10 | select SPL_RAM if SPL |
| 11 | imply CPU |
| 12 | imply CPU_RISCV |
| 13 | imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) |
| Bin Meng | b5f0372 | 2023-06-21 23:11:46 +0800 | [diff] [blame] | 14 | imply SPL_RISCV_ACLINT |
| Green Wan | 7f33743 | 2021-05-27 06:52:07 -0700 | [diff] [blame] | 15 | imply CMD_CPU |
| 16 | imply SPL_CPU |
| 17 | imply SPL_OPENSBI |
| 18 | imply SPL_LOAD_FIT |
| 19 | imply SMP |
| 20 | imply CLK_SIFIVE |
| 21 | imply CLK_SIFIVE_PRCI |
| Zong Li | ec34849 | 2021-09-01 15:01:42 +0800 | [diff] [blame] | 22 | imply SIFIVE_CACHE |
| 23 | imply SIFIVE_CCACHE |
| Green Wan | 7f33743 | 2021-05-27 06:52:07 -0700 | [diff] [blame] | 24 | imply SIFIVE_SERIAL |
| 25 | imply MACB |
| 26 | imply MII |
| 27 | imply SPI |
| 28 | imply SPI_SIFIVE |
| 29 | imply MMC |
| 30 | imply MMC_SPI |
| 31 | imply MMC_BROKEN_CD |
| 32 | imply CMD_MMC |
| 33 | imply DM_GPIO |
| 34 | imply SIFIVE_GPIO |
| 35 | imply CMD_GPIO |
| 36 | imply MISC |
| 37 | imply SIFIVE_OTP |
| 38 | imply DM_PWM |
| 39 | imply PWM_SIFIVE |
| Zong Li | 3376055 | 2021-06-30 23:23:46 +0800 | [diff] [blame] | 40 | imply DM_I2C |
| 41 | imply SYS_I2C_OCORES |
| Simon Glass | bccfc2e | 2021-07-10 21:14:36 -0600 | [diff] [blame] | 42 | imply SPL_I2C |
| Thomas Skibo | 9b9c4d5 | 2021-11-24 14:32:10 -0800 | [diff] [blame] | 43 | |
| 44 | if ENV_IS_IN_SPI_FLASH |
| 45 | |
| 46 | config ENV_OFFSET |
| 47 | default 0x505000 |
| 48 | |
| 49 | config ENV_SIZE |
| 50 | default 0x20000 |
| 51 | |
| 52 | config ENV_SECT_SIZE |
| 53 | default 0x10000 |
| 54 | |
| 55 | endif # ENV_IS_IN_SPI_FLASH |