riscv: cpu: fu740: Add support for cpu fu740
Add SiFive fu740 cpu to support RISC-V arch
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
new file mode 100644
index 0000000..3a5f6e4
--- /dev/null
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel@sifive.com>
+
+config SIFIVE_FU740
+ bool
+ select ARCH_EARLY_INIT_R
+ select RAM
+ select SPL_RAM if SPL
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply SPL_SIFIVE_CLINT
+ imply CMD_CPU
+ imply SPL_CPU
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
+ imply SMP
+ imply CLK_SIFIVE
+ imply CLK_SIFIVE_PRCI
+ imply SIFIVE_SERIAL
+ imply MACB
+ imply MII
+ imply SPI
+ imply SPI_SIFIVE
+ imply MMC
+ imply MMC_SPI
+ imply MMC_BROKEN_CD
+ imply CMD_MMC
+ imply DM_GPIO
+ imply SIFIVE_GPIO
+ imply CMD_GPIO
+ imply MISC
+ imply SIFIVE_OTP
+ imply DM_PWM
+ imply PWM_SIFIVE