blob: 9bdb6798b6708a38519c7b07bd353137cdd5a9ce [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek14b4c702009-09-07 09:08:02 +02002/*
3 * (C) Copyright 2007-2009 Michal Simek
4 * (C) Copyright 2003 Xilinx Inc.
Michal Simek4514b372008-03-28 12:41:56 +01005 *
Michal Simek4514b372008-03-28 12:41:56 +01006 * Michal SIMEK <monstr@monstr.eu>
Michal Simek14b4c702009-09-07 09:08:02 +02007 */
Michal Simek4514b372008-03-28 12:41:56 +01008
9#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Michal Simek4514b372008-03-28 12:41:56 +010011#include <net.h>
12#include <config.h>
Michal Simekf7cba782015-12-10 17:15:52 +010013#include <dm.h>
Michal Simek912145b2015-12-10 13:33:20 +010014#include <console.h>
Michal Simekb4a1d082010-10-11 11:41:47 +100015#include <malloc.h>
Michal Simek4514b372008-03-28 12:41:56 +010016#include <asm/io.h>
Michal Simek912145b2015-12-10 13:33:20 +010017#include <phy.h>
18#include <miiphy.h>
Michal Simekbb8b27b2012-06-28 21:37:57 +000019#include <fdtdec.h>
Simon Glassdbd79542020-05-10 11:40:11 -060020#include <linux/delay.h>
Masahiro Yamada64e4f7f2016-09-21 11:28:57 +090021#include <linux/errno.h>
Michal Simek36f7a412015-12-10 16:31:38 +010022#include <linux/kernel.h>
Zubair Lutfullah Kakakheld23bf842016-07-27 12:25:07 +010023#include <asm/io.h>
Michal Simekbb8b27b2012-06-28 21:37:57 +000024
Michal Simekf7cba782015-12-10 17:15:52 +010025DECLARE_GLOBAL_DATA_PTR;
Michal Simek4514b372008-03-28 12:41:56 +010026
Michal Simek4514b372008-03-28 12:41:56 +010027#define ENET_ADDR_LENGTH 6
Michal Simek36f7a412015-12-10 16:31:38 +010028#define ETH_FCS_LEN 4 /* Octets in the FCS */
Michal Simek4514b372008-03-28 12:41:56 +010029
30/* Xmit complete */
31#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
32/* Xmit interrupt enable bit */
33#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
Michal Simek4514b372008-03-28 12:41:56 +010034/* Program the MAC address */
35#define XEL_TSR_PROGRAM_MASK 0x00000002UL
36/* define for programming the MAC address into the EMAC Lite */
37#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
38
39/* Transmit packet length upper byte */
40#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
41/* Transmit packet length lower byte */
42#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
43
44/* Recv complete */
45#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
46/* Recv interrupt enable bit */
47#define XEL_RSR_RECV_IE_MASK 0x00000008UL
48
Michal Simek912145b2015-12-10 13:33:20 +010049/* MDIO Address Register Bit Masks */
50#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
51#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
52#define XEL_MDIOADDR_PHYADR_SHIFT 5
53#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
54
55/* MDIO Write Data Register Bit Masks */
56#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
57
58/* MDIO Read Data Register Bit Masks */
59#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
60
61/* MDIO Control Register Bit Masks */
62#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
63#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
64
Michal Simek905f0982015-12-10 14:18:15 +010065struct emaclite_regs {
66 u32 tx_ping; /* 0x0 - TX Ping buffer */
67 u32 reserved1[504];
68 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
69 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
70 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
71 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
72 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
73 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
74 u32 tx_ping_tsr; /* 0x7fc - Tx status */
75 u32 tx_pong; /* 0x800 - TX Pong buffer */
76 u32 reserved2[508];
77 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
78 u32 reserved3; /* 0xff8 */
79 u32 tx_pong_tsr; /* 0xffc - Tx status */
80 u32 rx_ping; /* 0x1000 - Receive Buffer */
81 u32 reserved4[510];
82 u32 rx_ping_rsr; /* 0x17fc - Rx status */
83 u32 rx_pong; /* 0x1800 - Receive Buffer */
84 u32 reserved5[510];
85 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
86};
87
Michal Simekf35b7cd2011-08-25 12:47:56 +020088struct xemaclite {
Michal Simek36f7a412015-12-10 16:31:38 +010089 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
Michal Simekdf40ead2011-09-12 21:10:01 +000090 u32 txpp; /* TX ping pong buffer */
91 u32 rxpp; /* RX ping pong buffer */
Michal Simek912145b2015-12-10 13:33:20 +010092 int phyaddr;
Michal Simek905f0982015-12-10 14:18:15 +010093 struct emaclite_regs *regs;
Michal Simek912145b2015-12-10 13:33:20 +010094 struct phy_device *phydev;
95 struct mii_dev *bus;
Michal Simekf35b7cd2011-08-25 12:47:56 +020096};
Michal Simek4514b372008-03-28 12:41:56 +010097
Michal Simek641ade02015-12-16 10:52:39 +010098static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
Michal Simek4514b372008-03-28 12:41:56 +010099
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000100static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
Michal Simek4514b372008-03-28 12:41:56 +0100101{
Michal Simekb4a1d082010-10-11 11:41:47 +1000102 u32 i;
Michal Simek4514b372008-03-28 12:41:56 +0100103 u32 alignbuffer;
104 u32 *to32ptr;
105 u32 *from32ptr;
106 u8 *to8ptr;
107 u8 *from8ptr;
108
109 from32ptr = (u32 *) srcptr;
110
111 /* Word aligned buffer, no correction needed. */
112 to32ptr = (u32 *) destptr;
113 while (bytecount > 3) {
114 *to32ptr++ = *from32ptr++;
115 bytecount -= 4;
116 }
117 to8ptr = (u8 *) to32ptr;
118
119 alignbuffer = *from32ptr++;
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000120 from8ptr = (u8 *) &alignbuffer;
Michal Simek4514b372008-03-28 12:41:56 +0100121
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000122 for (i = 0; i < bytecount; i++)
Michal Simek4514b372008-03-28 12:41:56 +0100123 *to8ptr++ = *from8ptr++;
Michal Simek4514b372008-03-28 12:41:56 +0100124}
125
Michal Simek90e89bf2015-12-10 16:01:50 +0100126static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
Michal Simek4514b372008-03-28 12:41:56 +0100127{
Michal Simekb4a1d082010-10-11 11:41:47 +1000128 u32 i;
Michal Simek4514b372008-03-28 12:41:56 +0100129 u32 alignbuffer;
130 u32 *to32ptr = (u32 *) destptr;
131 u32 *from32ptr;
132 u8 *to8ptr;
133 u8 *from8ptr;
134
135 from32ptr = (u32 *) srcptr;
136 while (bytecount > 3) {
137
138 *to32ptr++ = *from32ptr++;
139 bytecount -= 4;
140 }
141
142 alignbuffer = 0;
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000143 to8ptr = (u8 *) &alignbuffer;
Michal Simek4514b372008-03-28 12:41:56 +0100144 from8ptr = (u8 *) from32ptr;
145
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000146 for (i = 0; i < bytecount; i++)
Michal Simek4514b372008-03-28 12:41:56 +0100147 *to8ptr++ = *from8ptr++;
Michal Simek4514b372008-03-28 12:41:56 +0100148
149 *to32ptr++ = alignbuffer;
150}
151
Michal Simek912145b2015-12-10 13:33:20 +0100152static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
153 bool set, unsigned int timeout)
154{
155 u32 val;
156 unsigned long start = get_timer(0);
157
158 while (1) {
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100159 val = __raw_readl(reg);
Michal Simek912145b2015-12-10 13:33:20 +0100160
161 if (!set)
162 val = ~val;
163
164 if ((val & mask) == mask)
165 return 0;
166
167 if (get_timer(start) > timeout)
168 break;
169
170 if (ctrlc()) {
171 puts("Abort\n");
172 return -EINTR;
173 }
174
175 udelay(1);
176 }
177
178 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
179 func, reg, mask, set);
180
181 return -ETIMEDOUT;
182}
183
Michal Simek905f0982015-12-10 14:18:15 +0100184static int mdio_wait(struct emaclite_regs *regs)
Michal Simek912145b2015-12-10 13:33:20 +0100185{
Michal Simek905f0982015-12-10 14:18:15 +0100186 return wait_for_bit(__func__, &regs->mdioctrl,
Michal Simek912145b2015-12-10 13:33:20 +0100187 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
188}
189
Michal Simek905f0982015-12-10 14:18:15 +0100190static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
Michal Simek912145b2015-12-10 13:33:20 +0100191 u16 *data)
192{
Michal Simek905f0982015-12-10 14:18:15 +0100193 struct emaclite_regs *regs = emaclite->regs;
194
195 if (mdio_wait(regs))
Michal Simek912145b2015-12-10 13:33:20 +0100196 return 1;
197
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100198 u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
199 __raw_writel(XEL_MDIOADDR_OP_MASK
200 | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
201 | registernum), &regs->mdioaddr);
202 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
Michal Simek912145b2015-12-10 13:33:20 +0100203
Michal Simek905f0982015-12-10 14:18:15 +0100204 if (mdio_wait(regs))
Michal Simek912145b2015-12-10 13:33:20 +0100205 return 1;
206
207 /* Read data */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100208 *data = __raw_readl(&regs->mdiord);
Michal Simek912145b2015-12-10 13:33:20 +0100209 return 0;
210}
211
Michal Simek905f0982015-12-10 14:18:15 +0100212static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
Michal Simek912145b2015-12-10 13:33:20 +0100213 u16 data)
214{
Michal Simek905f0982015-12-10 14:18:15 +0100215 struct emaclite_regs *regs = emaclite->regs;
216
217 if (mdio_wait(regs))
Michal Simek912145b2015-12-10 13:33:20 +0100218 return 1;
219
220 /*
221 * Write the PHY address, register number and clear the OP bit in the
222 * MDIO Address register and then write the value into the MDIO Write
223 * Data register. Finally, set the Status bit in the MDIO Control
224 * register to start a MDIO write transaction.
225 */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100226 u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
227 __raw_writel(~XEL_MDIOADDR_OP_MASK
228 & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
229 | registernum), &regs->mdioaddr);
230 __raw_writel(data, &regs->mdiowr);
231 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
Michal Simek912145b2015-12-10 13:33:20 +0100232
Michal Simek905f0982015-12-10 14:18:15 +0100233 if (mdio_wait(regs))
Michal Simek912145b2015-12-10 13:33:20 +0100234 return 1;
235
236 return 0;
237}
Michal Simek912145b2015-12-10 13:33:20 +0100238
Michal Simekfeebc8a2015-12-16 10:40:05 +0100239static void emaclite_stop(struct udevice *dev)
Michal Simek4514b372008-03-28 12:41:56 +0100240{
Michal Simekfeebc8a2015-12-16 10:40:05 +0100241 debug("eth_stop\n");
Michal Simek4514b372008-03-28 12:41:56 +0100242}
Michal Simek912145b2015-12-10 13:33:20 +0100243
244/* Use MII register 1 (MII status register) to detect PHY */
245#define PHY_DETECT_REG 1
246
247/* Mask used to verify certain PHY features (or register contents)
248 * in the register above:
249 * 0x1000: 10Mbps full duplex support
250 * 0x0800: 10Mbps half duplex support
251 * 0x0008: Auto-negotiation support
252 */
253#define PHY_DETECT_MASK 0x1808
254
Michal Simekf7cba782015-12-10 17:15:52 +0100255static int setup_phy(struct udevice *dev)
Michal Simek912145b2015-12-10 13:33:20 +0100256{
Michal Simekdbc0cfc2016-05-18 12:37:22 +0200257 int i, ret;
Michal Simek912145b2015-12-10 13:33:20 +0100258 u16 phyreg;
Michal Simekf7cba782015-12-10 17:15:52 +0100259 struct xemaclite *emaclite = dev_get_priv(dev);
Michal Simek912145b2015-12-10 13:33:20 +0100260 struct phy_device *phydev;
261
262 u32 supported = SUPPORTED_10baseT_Half |
263 SUPPORTED_10baseT_Full |
264 SUPPORTED_100baseT_Half |
265 SUPPORTED_100baseT_Full;
266
267 if (emaclite->phyaddr != -1) {
Michal Simek905f0982015-12-10 14:18:15 +0100268 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
Michal Simek912145b2015-12-10 13:33:20 +0100269 if ((phyreg != 0xFFFF) &&
270 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
271 /* Found a valid PHY address */
272 debug("Default phy address %d is valid\n",
273 emaclite->phyaddr);
274 } else {
275 debug("PHY address is not setup correctly %d\n",
276 emaclite->phyaddr);
277 emaclite->phyaddr = -1;
278 }
279 }
280
281 if (emaclite->phyaddr == -1) {
282 /* detect the PHY address */
283 for (i = 31; i >= 0; i--) {
Michal Simek905f0982015-12-10 14:18:15 +0100284 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
Michal Simek912145b2015-12-10 13:33:20 +0100285 if ((phyreg != 0xFFFF) &&
286 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
287 /* Found a valid PHY address */
288 emaclite->phyaddr = i;
289 debug("emaclite: Found valid phy address, %d\n",
290 i);
291 break;
292 }
293 }
294 }
295
296 /* interface - look at tsec */
297 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
298 PHY_INTERFACE_MODE_MII);
299 /*
300 * Phy can support 1000baseT but device NOT that's why phydev->supported
301 * must be setup for 1000baseT. phydev->advertising setups what speeds
302 * will be used for autonegotiation where 1000baseT must be disabled.
303 */
304 phydev->supported = supported | SUPPORTED_1000baseT_Half |
305 SUPPORTED_1000baseT_Full;
306 phydev->advertising = supported;
307 emaclite->phydev = phydev;
308 phy_config(phydev);
Michal Simekdbc0cfc2016-05-18 12:37:22 +0200309 ret = phy_startup(phydev);
310 if (ret)
311 return ret;
Michal Simek912145b2015-12-10 13:33:20 +0100312
313 if (!phydev->link) {
314 printf("%s: No link.\n", phydev->dev->name);
315 return 0;
316 }
317
318 /* Do not setup anything */
319 return 1;
320}
Michal Simek4514b372008-03-28 12:41:56 +0100321
Michal Simekfeebc8a2015-12-16 10:40:05 +0100322static int emaclite_start(struct udevice *dev)
Michal Simek4514b372008-03-28 12:41:56 +0100323{
Michal Simekf7cba782015-12-10 17:15:52 +0100324 struct xemaclite *emaclite = dev_get_priv(dev);
325 struct eth_pdata *pdata = dev_get_platdata(dev);
Michal Simek905f0982015-12-10 14:18:15 +0100326 struct emaclite_regs *regs = emaclite->regs;
327
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000328 debug("EmacLite Initialization Started\n");
Michal Simek4514b372008-03-28 12:41:56 +0100329
330/*
331 * TX - TX_PING & TX_PONG initialization
332 */
333 /* Restart PING TX */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100334 __raw_writel(0, &regs->tx_ping_tsr);
Michal Simek4514b372008-03-28 12:41:56 +0100335 /* Copy MAC address */
Michal Simekf7cba782015-12-10 17:15:52 +0100336 xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
Michal Simek34240c42015-12-10 15:22:21 +0100337 ENET_ADDR_LENGTH);
Michal Simek4514b372008-03-28 12:41:56 +0100338 /* Set the length */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100339 __raw_writel(ENET_ADDR_LENGTH, &regs->tx_ping_tplr);
Michal Simek4514b372008-03-28 12:41:56 +0100340 /* Update the MAC address in the EMAC Lite */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100341 __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_ping_tsr);
Michal Simek4514b372008-03-28 12:41:56 +0100342 /* Wait for EMAC Lite to finish with the MAC address update */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100343 while ((__raw_readl(&regs->tx_ping_tsr) &
Michal Simekac357ac2011-08-25 12:36:39 +0200344 XEL_TSR_PROG_MAC_ADDR) != 0)
345 ;
Michal Simek4514b372008-03-28 12:41:56 +0100346
Michal Simekdf40ead2011-09-12 21:10:01 +0000347 if (emaclite->txpp) {
348 /* The same operation with PONG TX */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100349 __raw_writel(0, &regs->tx_pong_tsr);
Michal Simekf7cba782015-12-10 17:15:52 +0100350 xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
Michal Simek34240c42015-12-10 15:22:21 +0100351 ENET_ADDR_LENGTH);
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100352 __raw_writel(ENET_ADDR_LENGTH, &regs->tx_pong_tplr);
353 __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_pong_tsr);
354 while ((__raw_readl(&regs->tx_pong_tsr) &
Michal Simek34240c42015-12-10 15:22:21 +0100355 XEL_TSR_PROG_MAC_ADDR) != 0)
Michal Simekdf40ead2011-09-12 21:10:01 +0000356 ;
357 }
Michal Simek4514b372008-03-28 12:41:56 +0100358
359/*
360 * RX - RX_PING & RX_PONG initialization
361 */
362 /* Write out the value to flush the RX buffer */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100363 __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_ping_rsr);
Michal Simekdf40ead2011-09-12 21:10:01 +0000364
365 if (emaclite->rxpp)
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100366 __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_pong_rsr);
Michal Simek4514b372008-03-28 12:41:56 +0100367
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100368 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, &regs->mdioctrl);
369 if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
Michal Simek912145b2015-12-10 13:33:20 +0100370 if (!setup_phy(dev))
371 return -1;
Michal Simekf7cba782015-12-10 17:15:52 +0100372
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000373 debug("EmacLite Initialization complete\n");
Michal Simek4514b372008-03-28 12:41:56 +0100374 return 0;
375}
376
Michal Simek1edc6572015-12-10 15:42:01 +0100377static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
Michal Simek4514b372008-03-28 12:41:56 +0100378{
Michal Simek1edc6572015-12-10 15:42:01 +0100379 u32 tmp;
380 struct emaclite_regs *regs = emaclite->regs;
Michal Simekf35b7cd2011-08-25 12:47:56 +0200381
Michal Simek4514b372008-03-28 12:41:56 +0100382 /*
383 * Read the other buffer register
384 * and determine if the other buffer is available
385 */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100386 tmp = ~__raw_readl(&regs->tx_ping_tsr);
Michal Simek1edc6572015-12-10 15:42:01 +0100387 if (emaclite->txpp)
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100388 tmp |= ~__raw_readl(&regs->tx_pong_tsr);
Michal Simek4514b372008-03-28 12:41:56 +0100389
Michal Simek1edc6572015-12-10 15:42:01 +0100390 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
Michal Simek4514b372008-03-28 12:41:56 +0100391}
392
Michal Simekf7cba782015-12-10 17:15:52 +0100393static int emaclite_send(struct udevice *dev, void *ptr, int len)
Michal Simekb4a1d082010-10-11 11:41:47 +1000394{
395 u32 reg;
Michal Simekf7cba782015-12-10 17:15:52 +0100396 struct xemaclite *emaclite = dev_get_priv(dev);
Michal Simek9b9423b2015-12-10 15:32:11 +0100397 struct emaclite_regs *regs = emaclite->regs;
Michal Simek4514b372008-03-28 12:41:56 +0100398
Michal Simekb4a1d082010-10-11 11:41:47 +1000399 u32 maxtry = 1000;
Michal Simek4514b372008-03-28 12:41:56 +0100400
Michal Simek3aa96f82011-09-12 21:10:04 +0000401 if (len > PKTSIZE)
402 len = PKTSIZE;
Michal Simek4514b372008-03-28 12:41:56 +0100403
Michal Simek1edc6572015-12-10 15:42:01 +0100404 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000405 udelay(10);
Michal Simek4514b372008-03-28 12:41:56 +0100406 maxtry--;
407 }
408
409 if (!maxtry) {
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000410 printf("Error: Timeout waiting for ethernet TX buffer\n");
Michal Simek4514b372008-03-28 12:41:56 +0100411 /* Restart PING TX */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100412 __raw_writel(0, &regs->tx_ping_tsr);
Michal Simekdf40ead2011-09-12 21:10:01 +0000413 if (emaclite->txpp) {
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100414 __raw_writel(0, &regs->tx_pong_tsr);
Michal Simekdf40ead2011-09-12 21:10:01 +0000415 }
Michal Simek29869212011-03-08 04:25:53 +0000416 return -1;
Michal Simek4514b372008-03-28 12:41:56 +0100417 }
418
Michal Simek4514b372008-03-28 12:41:56 +0100419 /* Determine if the expected buffer address is empty */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100420 reg = __raw_readl(&regs->tx_ping_tsr);
Michal Simekd92cef42015-12-10 16:06:07 +0100421 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
Michal Simek90e89bf2015-12-10 16:01:50 +0100422 debug("Send packet from tx_ping buffer\n");
Michal Simek4514b372008-03-28 12:41:56 +0100423 /* Write the frame to the buffer */
Michal Simek90e89bf2015-12-10 16:01:50 +0100424 xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100425 __raw_writel(len
426 & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
427 &regs->tx_ping_tplr);
428 reg = __raw_readl(&regs->tx_ping_tsr);
Michal Simek4514b372008-03-28 12:41:56 +0100429 reg |= XEL_TSR_XMIT_BUSY_MASK;
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100430 __raw_writel(reg, &regs->tx_ping_tsr);
Michal Simek29869212011-03-08 04:25:53 +0000431 return 0;
Michal Simek4514b372008-03-28 12:41:56 +0100432 }
Michal Simekdf40ead2011-09-12 21:10:01 +0000433
434 if (emaclite->txpp) {
Michal Simekdf40ead2011-09-12 21:10:01 +0000435 /* Determine if the expected buffer address is empty */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100436 reg = __raw_readl(&regs->tx_pong_tsr);
Michal Simekd92cef42015-12-10 16:06:07 +0100437 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
Michal Simek90e89bf2015-12-10 16:01:50 +0100438 debug("Send packet from tx_pong buffer\n");
Michal Simekdf40ead2011-09-12 21:10:01 +0000439 /* Write the frame to the buffer */
Michal Simek90e89bf2015-12-10 16:01:50 +0100440 xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100441 __raw_writel(len &
Michal Simek90e89bf2015-12-10 16:01:50 +0100442 (XEL_TPLR_LENGTH_MASK_HI |
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100443 XEL_TPLR_LENGTH_MASK_LO),
444 &regs->tx_pong_tplr);
445 reg = __raw_readl(&regs->tx_pong_tsr);
Michal Simekdf40ead2011-09-12 21:10:01 +0000446 reg |= XEL_TSR_XMIT_BUSY_MASK;
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100447 __raw_writel(reg, &regs->tx_pong_tsr);
Michal Simekdf40ead2011-09-12 21:10:01 +0000448 return 0;
Michal Simek4514b372008-03-28 12:41:56 +0100449 }
Michal Simek4514b372008-03-28 12:41:56 +0100450 }
Michal Simekdf40ead2011-09-12 21:10:01 +0000451
Michal Simek5d1cf6c2011-09-12 21:10:05 +0000452 puts("Error while sending frame\n");
Michal Simek29869212011-03-08 04:25:53 +0000453 return -1;
Michal Simek4514b372008-03-28 12:41:56 +0100454}
455
Michal Simekf7cba782015-12-10 17:15:52 +0100456static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
Michal Simek4514b372008-03-28 12:41:56 +0100457{
Michal Simek36f7a412015-12-10 16:31:38 +0100458 u32 length, first_read, reg, attempt = 0;
459 void *addr, *ack;
Michal Simekf35b7cd2011-08-25 12:47:56 +0200460 struct xemaclite *emaclite = dev->priv;
Michal Simek36f7a412015-12-10 16:31:38 +0100461 struct emaclite_regs *regs = emaclite->regs;
462 struct ethernet_hdr *eth;
463 struct ip_udp_hdr *ip;
Michal Simek4514b372008-03-28 12:41:56 +0100464
Michal Simek36f7a412015-12-10 16:31:38 +0100465try_again:
466 if (!emaclite->use_rx_pong_buffer_next) {
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100467 reg = __raw_readl(&regs->rx_ping_rsr);
Michal Simek36f7a412015-12-10 16:31:38 +0100468 debug("Testing data at rx_ping\n");
469 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
470 debug("Data found in rx_ping buffer\n");
471 addr = &regs->rx_ping;
472 ack = &regs->rx_ping_rsr;
473 } else {
474 debug("Data not found in rx_ping buffer\n");
475 /* Pong buffer is not available - return immediately */
476 if (!emaclite->rxpp)
477 return -1;
Michal Simekdf40ead2011-09-12 21:10:01 +0000478
Michal Simek36f7a412015-12-10 16:31:38 +0100479 /* Try pong buffer if this is first attempt */
480 if (attempt++)
481 return -1;
482 emaclite->use_rx_pong_buffer_next =
483 !emaclite->use_rx_pong_buffer_next;
484 goto try_again;
485 }
486 } else {
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100487 reg = __raw_readl(&regs->rx_pong_rsr);
Michal Simek36f7a412015-12-10 16:31:38 +0100488 debug("Testing data at rx_pong\n");
489 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
490 debug("Data found in rx_pong buffer\n");
491 addr = &regs->rx_pong;
492 ack = &regs->rx_pong_rsr;
Michal Simekdf40ead2011-09-12 21:10:01 +0000493 } else {
Michal Simek36f7a412015-12-10 16:31:38 +0100494 debug("Data not found in rx_pong buffer\n");
495 /* Try ping buffer if this is first attempt */
496 if (attempt++)
497 return -1;
498 emaclite->use_rx_pong_buffer_next =
499 !emaclite->use_rx_pong_buffer_next;
500 goto try_again;
Michal Simek4514b372008-03-28 12:41:56 +0100501 }
Michal Simek4514b372008-03-28 12:41:56 +0100502 }
Michal Simek36f7a412015-12-10 16:31:38 +0100503
504 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
505 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
506 xemaclite_alignedread(addr, etherrxbuff, first_read);
507
508 /* Detect real packet size */
509 eth = (struct ethernet_hdr *)etherrxbuff;
510 switch (ntohs(eth->et_protlen)) {
511 case PROT_ARP:
512 length = first_read;
513 debug("ARP Packet %x\n", length);
514 break;
515 case PROT_IP:
516 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
517 length = ntohs(ip->ip_len);
518 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
519 debug("IP Packet %x\n", length);
520 break;
521 default:
522 debug("Other Packet\n");
523 length = PKTSIZE;
524 break;
Michal Simek4514b372008-03-28 12:41:56 +0100525 }
526
Michal Simek36f7a412015-12-10 16:31:38 +0100527 /* Read the rest of the packet which is longer then first read */
528 if (length != first_read)
529 xemaclite_alignedread(addr + first_read,
530 etherrxbuff + first_read,
531 length - first_read);
Michal Simek4514b372008-03-28 12:41:56 +0100532
533 /* Acknowledge the frame */
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100534 reg = __raw_readl(ack);
Michal Simek4514b372008-03-28 12:41:56 +0100535 reg &= ~XEL_RSR_RECV_DONE_MASK;
Zubair Lutfullah Kakakhel91664592016-07-27 12:25:08 +0100536 __raw_writel(reg, ack);
Michal Simek4514b372008-03-28 12:41:56 +0100537
Michal Simek36f7a412015-12-10 16:31:38 +0100538 debug("Packet receive from 0x%p, length %dB\n", addr, length);
Michal Simek641ade02015-12-16 10:52:39 +0100539 *packetp = etherrxbuff;
540 return length;
Michal Simek912145b2015-12-10 13:33:20 +0100541}
542
Michal Simekf7cba782015-12-10 17:15:52 +0100543static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
544 int devad, int reg)
Michal Simek912145b2015-12-10 13:33:20 +0100545{
546 u32 ret;
Michal Simekf7cba782015-12-10 17:15:52 +0100547 u16 val = 0;
Michal Simek912145b2015-12-10 13:33:20 +0100548
Michal Simekf7cba782015-12-10 17:15:52 +0100549 ret = phyread(bus->priv, addr, reg, &val);
550 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
551 return val;
Michal Simek4514b372008-03-28 12:41:56 +0100552}
Michal Simekb4a1d082010-10-11 11:41:47 +1000553
Michal Simekf7cba782015-12-10 17:15:52 +0100554static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
555 int reg, u16 value)
Michal Simek912145b2015-12-10 13:33:20 +0100556{
Michal Simekf7cba782015-12-10 17:15:52 +0100557 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
558 return phywrite(bus->priv, addr, reg, value);
Michal Simek912145b2015-12-10 13:33:20 +0100559}
Michal Simek912145b2015-12-10 13:33:20 +0100560
Michal Simekf7cba782015-12-10 17:15:52 +0100561static int emaclite_probe(struct udevice *dev)
Michal Simekb4a1d082010-10-11 11:41:47 +1000562{
Michal Simekf7cba782015-12-10 17:15:52 +0100563 struct xemaclite *emaclite = dev_get_priv(dev);
564 int ret;
Michal Simekb4a1d082010-10-11 11:41:47 +1000565
Michal Simekf7cba782015-12-10 17:15:52 +0100566 emaclite->bus = mdio_alloc();
567 emaclite->bus->read = emaclite_miiphy_read;
568 emaclite->bus->write = emaclite_miiphy_write;
569 emaclite->bus->priv = emaclite;
Michal Simekf35b7cd2011-08-25 12:47:56 +0200570
Michal Simeke4dab432016-12-08 10:25:44 +0100571 ret = mdio_register_seq(emaclite->bus, dev->seq);
Michal Simekf7cba782015-12-10 17:15:52 +0100572 if (ret)
573 return ret;
574
575 return 0;
576}
Michal Simekf35b7cd2011-08-25 12:47:56 +0200577
Michal Simekf7cba782015-12-10 17:15:52 +0100578static int emaclite_remove(struct udevice *dev)
579{
580 struct xemaclite *emaclite = dev_get_priv(dev);
581
582 free(emaclite->phydev);
583 mdio_unregister(emaclite->bus);
584 mdio_free(emaclite->bus);
Michal Simekb4a1d082010-10-11 11:41:47 +1000585
Michal Simekf7cba782015-12-10 17:15:52 +0100586 return 0;
587}
Michal Simekdf40ead2011-09-12 21:10:01 +0000588
Michal Simekf7cba782015-12-10 17:15:52 +0100589static const struct eth_ops emaclite_ops = {
Michal Simekfeebc8a2015-12-16 10:40:05 +0100590 .start = emaclite_start,
Michal Simekf7cba782015-12-10 17:15:52 +0100591 .send = emaclite_send,
592 .recv = emaclite_recv,
Michal Simekfeebc8a2015-12-16 10:40:05 +0100593 .stop = emaclite_stop,
Michal Simekf7cba782015-12-10 17:15:52 +0100594};
595
596static int emaclite_ofdata_to_platdata(struct udevice *dev)
597{
598 struct eth_pdata *pdata = dev_get_platdata(dev);
599 struct xemaclite *emaclite = dev_get_priv(dev);
600 int offset = 0;
Michal Simekb4a1d082010-10-11 11:41:47 +1000601
Simon Glassba1dea42017-05-17 17:18:05 -0600602 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Zubair Lutfullah Kakakheld23bf842016-07-27 12:25:07 +0100603 emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
604 0x10000);
Michal Simekb4a1d082010-10-11 11:41:47 +1000605
Michal Simek912145b2015-12-10 13:33:20 +0100606 emaclite->phyaddr = -1;
Michal Simek912145b2015-12-10 13:33:20 +0100607
Simon Glassdd79d6e2017-01-17 16:52:55 -0700608 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
Michal Simekf7cba782015-12-10 17:15:52 +0100609 "phy-handle");
610 if (offset > 0)
611 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
612 "reg", -1);
Michal Simekb4a1d082010-10-11 11:41:47 +1000613
Simon Glassdd79d6e2017-01-17 16:52:55 -0700614 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Michal Simekf7cba782015-12-10 17:15:52 +0100615 "xlnx,tx-ping-pong", 0);
Simon Glassdd79d6e2017-01-17 16:52:55 -0700616 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Michal Simekf7cba782015-12-10 17:15:52 +0100617 "xlnx,rx-ping-pong", 0);
Michal Simek912145b2015-12-10 13:33:20 +0100618
Michal Simekf7cba782015-12-10 17:15:52 +0100619 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
620 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
Michal Simek912145b2015-12-10 13:33:20 +0100621
Michal Simekf7cba782015-12-10 17:15:52 +0100622 return 0;
Michal Simekb4a1d082010-10-11 11:41:47 +1000623}
Michal Simekf7cba782015-12-10 17:15:52 +0100624
625static const struct udevice_id emaclite_ids[] = {
626 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
627 { }
628};
629
630U_BOOT_DRIVER(emaclite) = {
631 .name = "emaclite",
632 .id = UCLASS_ETH,
633 .of_match = emaclite_ids,
634 .ofdata_to_platdata = emaclite_ofdata_to_platdata,
635 .probe = emaclite_probe,
636 .remove = emaclite_remove,
637 .ops = &emaclite_ops,
638 .priv_auto_alloc_size = sizeof(struct xemaclite),
639 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
640};