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Michal Simek14b4c702009-09-07 09:08:02 +02001/*
2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
Michal Simek4514b372008-03-28 12:41:56 +01004 *
Michal Simek4514b372008-03-28 12:41:56 +01005 * Michal SIMEK <monstr@monstr.eu>
6 *
Michal Simek14b4c702009-09-07 09:08:02 +02007 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
Michal Simek4514b372008-03-28 12:41:56 +010019 *
Michal Simek14b4c702009-09-07 09:08:02 +020020 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
Michal Simek4514b372008-03-28 12:41:56 +010025
26#include <common.h>
27#include <net.h>
28#include <config.h>
Michal Simekb4a1d082010-10-11 11:41:47 +100029#include <malloc.h>
Michal Simek4514b372008-03-28 12:41:56 +010030#include <asm/io.h>
31
32#undef DEBUG
33
Michal Simek4514b372008-03-28 12:41:56 +010034#define ENET_ADDR_LENGTH 6
35
36/* EmacLite constants */
37#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
38#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
39#define XEL_TSR_OFFSET 0x07FC /* Tx status */
40#define XEL_RSR_OFFSET 0x17FC /* Rx status */
41#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
42
43/* Xmit complete */
44#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
45/* Xmit interrupt enable bit */
46#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
47/* Buffer is active, SW bit only */
48#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
49/* Program the MAC address */
50#define XEL_TSR_PROGRAM_MASK 0x00000002UL
51/* define for programming the MAC address into the EMAC Lite */
52#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
53
54/* Transmit packet length upper byte */
55#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
56/* Transmit packet length lower byte */
57#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
58
59/* Recv complete */
60#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
61/* Recv interrupt enable bit */
62#define XEL_RSR_RECV_IE_MASK 0x00000008UL
63
Michal Simekf35b7cd2011-08-25 12:47:56 +020064struct xemaclite {
Michal Simekb4a1d082010-10-11 11:41:47 +100065 u32 nexttxbuffertouse; /* Next TX buffer to write to */
66 u32 nextrxbuffertouse; /* Next RX buffer to read from */
Michal Simekdf40ead2011-09-12 21:10:01 +000067 u32 txpp; /* TX ping pong buffer */
68 u32 rxpp; /* RX ping pong buffer */
Michal Simekf35b7cd2011-08-25 12:47:56 +020069};
Michal Simek4514b372008-03-28 12:41:56 +010070
Clive Stubbings0d501912008-10-27 15:05:00 +000071static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
Michal Simek4514b372008-03-28 12:41:56 +010072
Michal Simekb4a1d082010-10-11 11:41:47 +100073static void xemaclite_alignedread (u32 *srcptr, void *destptr, u32 bytecount)
Michal Simek4514b372008-03-28 12:41:56 +010074{
Michal Simekb4a1d082010-10-11 11:41:47 +100075 u32 i;
Michal Simek4514b372008-03-28 12:41:56 +010076 u32 alignbuffer;
77 u32 *to32ptr;
78 u32 *from32ptr;
79 u8 *to8ptr;
80 u8 *from8ptr;
81
82 from32ptr = (u32 *) srcptr;
83
84 /* Word aligned buffer, no correction needed. */
85 to32ptr = (u32 *) destptr;
86 while (bytecount > 3) {
87 *to32ptr++ = *from32ptr++;
88 bytecount -= 4;
89 }
90 to8ptr = (u8 *) to32ptr;
91
92 alignbuffer = *from32ptr++;
93 from8ptr = (u8 *) & alignbuffer;
94
95 for (i = 0; i < bytecount; i++) {
96 *to8ptr++ = *from8ptr++;
97 }
98}
99
Michal Simekb4a1d082010-10-11 11:41:47 +1000100static void xemaclite_alignedwrite (void *srcptr, u32 destptr, u32 bytecount)
Michal Simek4514b372008-03-28 12:41:56 +0100101{
Michal Simekb4a1d082010-10-11 11:41:47 +1000102 u32 i;
Michal Simek4514b372008-03-28 12:41:56 +0100103 u32 alignbuffer;
104 u32 *to32ptr = (u32 *) destptr;
105 u32 *from32ptr;
106 u8 *to8ptr;
107 u8 *from8ptr;
108
109 from32ptr = (u32 *) srcptr;
110 while (bytecount > 3) {
111
112 *to32ptr++ = *from32ptr++;
113 bytecount -= 4;
114 }
115
116 alignbuffer = 0;
117 to8ptr = (u8 *) & alignbuffer;
118 from8ptr = (u8 *) from32ptr;
119
120 for (i = 0; i < bytecount; i++) {
121 *to8ptr++ = *from8ptr++;
122 }
123
124 *to32ptr++ = alignbuffer;
125}
126
Michal Simekb4a1d082010-10-11 11:41:47 +1000127static void emaclite_halt(struct eth_device *dev)
Michal Simek4514b372008-03-28 12:41:56 +0100128{
129 debug ("eth_halt\n");
130}
131
Michal Simekb4a1d082010-10-11 11:41:47 +1000132static int emaclite_init(struct eth_device *dev, bd_t *bis)
Michal Simek4514b372008-03-28 12:41:56 +0100133{
Michal Simekdf40ead2011-09-12 21:10:01 +0000134 struct xemaclite *emaclite = dev->priv;
Michal Simek4514b372008-03-28 12:41:56 +0100135 debug ("EmacLite Initialization Started\n");
Michal Simek4514b372008-03-28 12:41:56 +0100136
137/*
138 * TX - TX_PING & TX_PONG initialization
139 */
140 /* Restart PING TX */
Michal Simekac357ac2011-08-25 12:36:39 +0200141 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
Michal Simek4514b372008-03-28 12:41:56 +0100142 /* Copy MAC address */
Michal Simekb4a1d082010-10-11 11:41:47 +1000143 xemaclite_alignedwrite (dev->enetaddr,
Michal Simekac357ac2011-08-25 12:36:39 +0200144 dev->iobase, ENET_ADDR_LENGTH);
Michal Simek4514b372008-03-28 12:41:56 +0100145 /* Set the length */
Michal Simekac357ac2011-08-25 12:36:39 +0200146 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
Michal Simek4514b372008-03-28 12:41:56 +0100147 /* Update the MAC address in the EMAC Lite */
Michal Simekac357ac2011-08-25 12:36:39 +0200148 out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
Michal Simek4514b372008-03-28 12:41:56 +0100149 /* Wait for EMAC Lite to finish with the MAC address update */
Michal Simekac357ac2011-08-25 12:36:39 +0200150 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
151 XEL_TSR_PROG_MAC_ADDR) != 0)
152 ;
Michal Simek4514b372008-03-28 12:41:56 +0100153
Michal Simekdf40ead2011-09-12 21:10:01 +0000154 if (emaclite->txpp) {
155 /* The same operation with PONG TX */
156 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
157 xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
158 XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
159 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
160 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
161 XEL_TSR_PROG_MAC_ADDR);
162 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
163 XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
164 ;
165 }
Michal Simek4514b372008-03-28 12:41:56 +0100166
167/*
168 * RX - RX_PING & RX_PONG initialization
169 */
170 /* Write out the value to flush the RX buffer */
Michal Simekac357ac2011-08-25 12:36:39 +0200171 out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
Michal Simekdf40ead2011-09-12 21:10:01 +0000172
173 if (emaclite->rxpp)
174 out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
175 XEL_RSR_RECV_IE_MASK);
Michal Simek4514b372008-03-28 12:41:56 +0100176
177 debug ("EmacLite Initialization complete\n");
178 return 0;
179}
180
Michal Simekf35b7cd2011-08-25 12:47:56 +0200181static int xemaclite_txbufferavailable(struct eth_device *dev)
Michal Simek4514b372008-03-28 12:41:56 +0100182{
183 u32 reg;
184 u32 txpingbusy;
185 u32 txpongbusy;
Michal Simekf35b7cd2011-08-25 12:47:56 +0200186 struct xemaclite *emaclite = dev->priv;
187
Michal Simek4514b372008-03-28 12:41:56 +0100188 /*
189 * Read the other buffer register
190 * and determine if the other buffer is available
191 */
Michal Simekf35b7cd2011-08-25 12:47:56 +0200192 reg = in_be32 (dev->iobase +
193 emaclite->nexttxbuffertouse + 0);
Michal Simek4514b372008-03-28 12:41:56 +0100194 txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
195 XEL_TSR_XMIT_BUSY_MASK);
196
Michal Simekf35b7cd2011-08-25 12:47:56 +0200197 reg = in_be32 (dev->iobase +
198 (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
Michal Simek4514b372008-03-28 12:41:56 +0100199 txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
200 XEL_TSR_XMIT_BUSY_MASK);
201
202 return (!(txpingbusy && txpongbusy));
203}
204
Michal Simekb4a1d082010-10-11 11:41:47 +1000205static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
206{
207 u32 reg;
208 u32 baseaddress;
Michal Simekf35b7cd2011-08-25 12:47:56 +0200209 struct xemaclite *emaclite = dev->priv;
Michal Simek4514b372008-03-28 12:41:56 +0100210
Michal Simekb4a1d082010-10-11 11:41:47 +1000211 u32 maxtry = 1000;
Michal Simek4514b372008-03-28 12:41:56 +0100212
Michal Simek3aa96f82011-09-12 21:10:04 +0000213 if (len > PKTSIZE)
214 len = PKTSIZE;
Michal Simek4514b372008-03-28 12:41:56 +0100215
Michal Simekf35b7cd2011-08-25 12:47:56 +0200216 while (!xemaclite_txbufferavailable(dev) && maxtry) {
Michal Simek4514b372008-03-28 12:41:56 +0100217 udelay (10);
218 maxtry--;
219 }
220
221 if (!maxtry) {
222 printf ("Error: Timeout waiting for ethernet TX buffer\n");
223 /* Restart PING TX */
Michal Simekac357ac2011-08-25 12:36:39 +0200224 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
Michal Simekdf40ead2011-09-12 21:10:01 +0000225 if (emaclite->txpp) {
226 out_be32 (dev->iobase + XEL_TSR_OFFSET +
227 XEL_BUFFER_OFFSET, 0);
228 }
Michal Simek29869212011-03-08 04:25:53 +0000229 return -1;
Michal Simek4514b372008-03-28 12:41:56 +0100230 }
231
232 /* Determine the expected TX buffer address */
Michal Simekf35b7cd2011-08-25 12:47:56 +0200233 baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
Michal Simek4514b372008-03-28 12:41:56 +0100234
235 /* Determine if the expected buffer address is empty */
236 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
237 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
238 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
239 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
240
Michal Simekdf40ead2011-09-12 21:10:01 +0000241 if (emaclite->txpp)
242 emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
243
Michal Simek4514b372008-03-28 12:41:56 +0100244 debug ("Send packet from 0x%x\n", baseaddress);
245 /* Write the frame to the buffer */
246 xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
247 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
248 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
249 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
250 reg |= XEL_TSR_XMIT_BUSY_MASK;
251 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
252 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
253 }
254 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
Michal Simek29869212011-03-08 04:25:53 +0000255 return 0;
Michal Simek4514b372008-03-28 12:41:56 +0100256 }
Michal Simekdf40ead2011-09-12 21:10:01 +0000257
258 if (emaclite->txpp) {
259 /* Switch to second buffer */
260 baseaddress ^= XEL_BUFFER_OFFSET;
261 /* Determine if the expected buffer address is empty */
Michal Simek4514b372008-03-28 12:41:56 +0100262 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
Michal Simekdf40ead2011-09-12 21:10:01 +0000263 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
264 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
265 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
266 debug("Send packet from 0x%x\n", baseaddress);
267 /* Write the frame to the buffer */
268 xemaclite_alignedwrite((void *) ptr, baseaddress, len);
269 out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
270 (XEL_TPLR_LENGTH_MASK_HI |
271 XEL_TPLR_LENGTH_MASK_LO)));
272 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
273 reg |= XEL_TSR_XMIT_BUSY_MASK;
274 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
275 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
276 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
277 return 0;
Michal Simek4514b372008-03-28 12:41:56 +0100278 }
Michal Simek4514b372008-03-28 12:41:56 +0100279 }
Michal Simekdf40ead2011-09-12 21:10:01 +0000280
Michal Simek4514b372008-03-28 12:41:56 +0100281 puts ("Error while sending frame\n");
Michal Simek29869212011-03-08 04:25:53 +0000282 return -1;
Michal Simek4514b372008-03-28 12:41:56 +0100283}
284
Michal Simekb4a1d082010-10-11 11:41:47 +1000285static int emaclite_recv(struct eth_device *dev)
Michal Simek4514b372008-03-28 12:41:56 +0100286{
Michal Simekb4a1d082010-10-11 11:41:47 +1000287 u32 length;
288 u32 reg;
289 u32 baseaddress;
Michal Simekf35b7cd2011-08-25 12:47:56 +0200290 struct xemaclite *emaclite = dev->priv;
Michal Simek4514b372008-03-28 12:41:56 +0100291
Michal Simekf35b7cd2011-08-25 12:47:56 +0200292 baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
Michal Simek4514b372008-03-28 12:41:56 +0100293 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
294 debug ("Testing data at address 0x%x\n", baseaddress);
295 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
Michal Simekdf40ead2011-09-12 21:10:01 +0000296 if (emaclite->rxpp)
297 emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
Michal Simek4514b372008-03-28 12:41:56 +0100298 } else {
Michal Simekdf40ead2011-09-12 21:10:01 +0000299
300 if (!emaclite->rxpp) {
Michal Simek4514b372008-03-28 12:41:56 +0100301 debug ("No data was available - address 0x%x\n",
Michal Simekdf40ead2011-09-12 21:10:01 +0000302 baseaddress);
Michal Simek4514b372008-03-28 12:41:56 +0100303 return 0;
Michal Simekdf40ead2011-09-12 21:10:01 +0000304 } else {
305 baseaddress ^= XEL_BUFFER_OFFSET;
306 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
307 if ((reg & XEL_RSR_RECV_DONE_MASK) !=
308 XEL_RSR_RECV_DONE_MASK) {
309 debug("No data was available - address 0x%x\n",
310 baseaddress);
311 return 0;
312 }
Michal Simek4514b372008-03-28 12:41:56 +0100313 }
Michal Simek4514b372008-03-28 12:41:56 +0100314 }
315 /* Get the length of the frame that arrived */
Michal Simek1b9ecc92010-10-11 11:41:46 +1000316 switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
Michal Simek4514b372008-03-28 12:41:56 +0100317 0xFFFF0000 ) >> 16) {
318 case 0x806:
319 length = 42 + 20; /* FIXME size of ARP */
320 debug ("ARP Packet\n");
321 break;
322 case 0x800:
323 length = 14 + 14 +
Michal Simek1b9ecc92010-10-11 11:41:46 +1000324 (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10))) &
Michal Simek4514b372008-03-28 12:41:56 +0100325 0xFFFF0000) >> 16); /* FIXME size of IP packet */
326 debug ("IP Packet\n");
327 break;
328 default:
Michal Simek3aa96f82011-09-12 21:10:04 +0000329 debug("Other Packet\n");
330 length = PKTSIZE;
Michal Simek4514b372008-03-28 12:41:56 +0100331 break;
332 }
333
334 xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
335 etherrxbuff, length);
336
337 /* Acknowledge the frame */
338 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
339 reg &= ~XEL_RSR_RECV_DONE_MASK;
340 out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
341
342 debug ("Packet receive from 0x%x, length %dB\n", baseaddress, length);
343 NetReceive ((uchar *) etherrxbuff, length);
Michal Simek29869212011-03-08 04:25:53 +0000344 return length;
Michal Simek4514b372008-03-28 12:41:56 +0100345
346}
Michal Simekb4a1d082010-10-11 11:41:47 +1000347
348int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
349{
350 struct eth_device *dev;
Michal Simekf35b7cd2011-08-25 12:47:56 +0200351 struct xemaclite *emaclite;
Michal Simekb4a1d082010-10-11 11:41:47 +1000352
Michal Simek8f2bf362011-08-25 12:28:47 +0200353 dev = calloc(1, sizeof(*dev));
Michal Simekb4a1d082010-10-11 11:41:47 +1000354 if (dev == NULL)
Michal Simek29869212011-03-08 04:25:53 +0000355 return -1;
Michal Simekf35b7cd2011-08-25 12:47:56 +0200356
357 emaclite = calloc(1, sizeof(struct xemaclite));
358 if (emaclite == NULL) {
359 free(dev);
360 return -1;
361 }
362
363 dev->priv = emaclite;
Michal Simekb4a1d082010-10-11 11:41:47 +1000364
Michal Simekdf40ead2011-09-12 21:10:01 +0000365#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
366 emaclite->txpp = 1;
367#endif
368#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
369 emaclite->rxpp = 1;
370#endif
371
Michal Simek0c7fa442011-08-25 12:25:14 +0200372 sprintf(dev->name, "Xelite.%x", base_addr);
Michal Simekb4a1d082010-10-11 11:41:47 +1000373
374 dev->iobase = base_addr;
Michal Simekb4a1d082010-10-11 11:41:47 +1000375 dev->init = emaclite_init;
376 dev->halt = emaclite_halt;
377 dev->send = emaclite_send;
378 dev->recv = emaclite_recv;
379
380 eth_register(dev);
381
Michal Simek29869212011-03-08 04:25:53 +0000382 return 1;
Michal Simekb4a1d082010-10-11 11:41:47 +1000383}