blob: 1c8767dbea29d94dc925a81f7f0d6b9eb329923d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4e112c12003-06-03 23:54:09 +00002/**************************************************************************
Andre Schwarz68c2a302008-03-06 16:45:44 +01003Intel Pro 1000 for ppcboot/das-u-boot
wdenk4e112c12003-06-03 23:54:09 +00004Drivers are port from Intel's Linux driver e1000-4.3.15
5and from Etherboot pro 1000 driver by mrakes at vivato dot net
6tested on both gig copper and gig fiber boards
7***************************************************************************/
8/*******************************************************************************
9
wdenk4e112c12003-06-03 23:54:09 +000010 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
wdenk57b2d802003-06-27 21:31:46 +000011
wdenk4e112c12003-06-03 23:54:09 +000012 Contact Information:
13 Linux NICS <linux.nics@intel.com>
14 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15
16*******************************************************************************/
17/*
18 * Copyright (C) Archway Digital Solutions.
19 *
20 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
21 * 2/9/2002
22 *
23 * Copyright (C) Linux Networx.
24 * Massive upgrade to work with the new intel gigabit NICs.
25 * <ebiederman at lnxi dot com>
Roy Zang181119b2011-01-21 11:29:38 +080026 *
27 * Copyright 2011 Freescale Semiconductor, Inc.
wdenk4e112c12003-06-03 23:54:09 +000028 */
29
Simon Glassed38aef2020-05-10 11:40:03 -060030#include <command.h>
Simon Glass63334482019-11-14 12:57:39 -070031#include <cpu_func.h>
Simon Glass9f86b382015-08-19 09:33:40 -060032#include <dm.h>
Simon Glassc53abc32015-08-19 09:33:39 -060033#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060034#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070035#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060036#include <memalign.h>
Simon Glass274e0b02020-05-10 11:39:56 -060037#include <net.h>
Simon Glassc53abc32015-08-19 09:33:39 -060038#include <pci.h>
Simon Glassdbd79542020-05-10 11:40:11 -060039#include <linux/delay.h>
wdenk4e112c12003-06-03 23:54:09 +000040#include "e1000.h"
Simon Glass274e0b02020-05-10 11:39:56 -060041#include <asm/cache.h>
wdenk4e112c12003-06-03 23:54:09 +000042
wdenk4e112c12003-06-03 23:54:09 +000043#define TOUT_LOOP 100000
44
Roy Zang966172e2009-08-22 03:49:52 +080045#define E1000_DEFAULT_PCI_PBA 0x00000030
46#define E1000_DEFAULT_PCIE_PBA 0x000a0026
wdenk4e112c12003-06-03 23:54:09 +000047
48/* NIC specific static variables go here */
49
Marek Vasut742c5c22014-08-08 07:41:38 -070050/* Intel i210 needs the DMA descriptor rings aligned to 128b */
51#define E1000_BUFFER_ALIGN 128
wdenk4e112c12003-06-03 23:54:09 +000052
Simon Glass9f86b382015-08-19 09:33:40 -060053/*
54 * TODO(sjg@chromium.org): Even with driver model we share these buffers.
55 * Concurrent receiving on multiple active Ethernet devices will not work.
56 * Normally U-Boot does not support this anyway. To fix it in this driver,
57 * move these buffers and the tx/rx pointers to struct e1000_hw.
58 */
Marek Vasut742c5c22014-08-08 07:41:38 -070059DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
60DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
61DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
wdenk4e112c12003-06-03 23:54:09 +000062
63static int tx_tail;
64static int rx_tail, rx_last;
Simon Glass9f86b382015-08-19 09:33:40 -060065static int num_cards; /* Number of E1000 devices seen so far */
wdenk4e112c12003-06-03 23:54:09 +000066
Kyle Moffett7b698d52011-10-18 11:05:26 +000067static struct pci_device_id e1000_supported[] = {
Simon Glassc53abc32015-08-19 09:33:39 -060068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
69 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
70 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
71 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
72 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
73 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
74 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
75 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
76 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
77 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
78 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
79 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
80 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
Roy Zang28f7a052009-07-31 13:34:02 +080085 /* E1000 PCIe card */
Simon Glassc53abc32015-08-19 09:33:39 -060086 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
88 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
98 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
106 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
107 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
Marjolaine Amate0cef7802024-06-24 19:15:32 +0000108 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_K) },
109 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LMVP) },
110 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LM) },
111 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_V) },
112 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_IT) },
113 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED) },
Simon Glassc53abc32015-08-19 09:33:39 -0600114 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
115 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
116 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
117 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
118 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
119 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
120 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
121 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
Marjolaine Amatee4913352024-03-04 16:23:38 +0100122 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED) },
123 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_IT) },
ZhiJie.zhang87e00132025-04-21 17:08:26 +0800124 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_V) },
Marek Vasut74a13c22014-08-08 07:41:39 -0700125
Stefan Althoeferbc6d2fc2008-12-20 19:40:41 +0100126 {}
wdenk4e112c12003-06-03 23:54:09 +0000127};
128
129/* Function forward declarations */
Simon Glassc53abc32015-08-19 09:33:39 -0600130static int e1000_setup_link(struct e1000_hw *hw);
131static int e1000_setup_fiber_link(struct e1000_hw *hw);
132static int e1000_setup_copper_link(struct e1000_hw *hw);
wdenk4e112c12003-06-03 23:54:09 +0000133static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
134static void e1000_config_collision_dist(struct e1000_hw *hw);
135static int e1000_config_mac_to_phy(struct e1000_hw *hw);
136static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
Simon Glassc53abc32015-08-19 09:33:39 -0600137static int e1000_check_for_link(struct e1000_hw *hw);
wdenk4e112c12003-06-03 23:54:09 +0000138static int e1000_wait_autoneg(struct e1000_hw *hw);
Roy Zang28f7a052009-07-31 13:34:02 +0800139static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
wdenk4e112c12003-06-03 23:54:09 +0000140 uint16_t * duplex);
141static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
142 uint16_t * phy_data);
143static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
144 uint16_t phy_data);
Roy Zang28f7a052009-07-31 13:34:02 +0800145static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
wdenk4e112c12003-06-03 23:54:09 +0000146static int e1000_phy_reset(struct e1000_hw *hw);
147static int e1000_detect_gig_phy(struct e1000_hw *hw);
Roy Zang28f7a052009-07-31 13:34:02 +0800148static void e1000_set_media_type(struct e1000_hw *hw);
wdenk4e112c12003-06-03 23:54:09 +0000149
Roy Zang28f7a052009-07-31 13:34:02 +0800150static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
Tim Harvey5cb59ec2015-05-19 10:01:18 -0700151static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
Roy Zang28f7a052009-07-31 13:34:02 +0800152static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
wdenk4e112c12003-06-03 23:54:09 +0000153
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +0200154#ifndef CONFIG_E1000_NO_NVM
155static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
Hannu Lounentoc56999e2018-01-10 20:31:24 +0100156static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
Roy Zang9b7c4302009-08-11 03:48:05 +0800157static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
158 uint16_t words,
159 uint16_t *data);
wdenk4e112c12003-06-03 23:54:09 +0000160/******************************************************************************
161 * Raises the EEPROM's clock input.
162 *
163 * hw - Struct containing variables accessed by shared code
164 * eecd - EECD's current value
165 *****************************************************************************/
Kyle Moffett142cbf82011-10-18 11:05:28 +0000166void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
wdenk4e112c12003-06-03 23:54:09 +0000167{
168 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
169 * wait 50 microseconds.
170 */
171 *eecd = *eecd | E1000_EECD_SK;
172 E1000_WRITE_REG(hw, EECD, *eecd);
173 E1000_WRITE_FLUSH(hw);
174 udelay(50);
175}
176
177/******************************************************************************
178 * Lowers the EEPROM's clock input.
179 *
wdenk57b2d802003-06-27 21:31:46 +0000180 * hw - Struct containing variables accessed by shared code
wdenk4e112c12003-06-03 23:54:09 +0000181 * eecd - EECD's current value
182 *****************************************************************************/
Kyle Moffett142cbf82011-10-18 11:05:28 +0000183void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
wdenk4e112c12003-06-03 23:54:09 +0000184{
wdenk57b2d802003-06-27 21:31:46 +0000185 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
186 * wait 50 microseconds.
wdenk4e112c12003-06-03 23:54:09 +0000187 */
188 *eecd = *eecd & ~E1000_EECD_SK;
189 E1000_WRITE_REG(hw, EECD, *eecd);
190 E1000_WRITE_FLUSH(hw);
191 udelay(50);
192}
193
194/******************************************************************************
195 * Shift data bits out to the EEPROM.
196 *
197 * hw - Struct containing variables accessed by shared code
198 * data - data to send to the EEPROM
199 * count - number of bits to shift out
200 *****************************************************************************/
201static void
202e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
203{
204 uint32_t eecd;
205 uint32_t mask;
206
207 /* We need to shift "count" bits out to the EEPROM. So, value in the
208 * "data" parameter will be shifted out to the EEPROM one bit at a time.
wdenk57b2d802003-06-27 21:31:46 +0000209 * In order to do this, "data" must be broken down into bits.
wdenk4e112c12003-06-03 23:54:09 +0000210 */
211 mask = 0x01 << (count - 1);
212 eecd = E1000_READ_REG(hw, EECD);
213 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
214 do {
215 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
216 * and then raising and then lowering the clock (the SK bit controls
217 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
218 * by setting "DI" to "0" and then raising and then lowering the clock.
219 */
220 eecd &= ~E1000_EECD_DI;
221
222 if (data & mask)
223 eecd |= E1000_EECD_DI;
224
225 E1000_WRITE_REG(hw, EECD, eecd);
226 E1000_WRITE_FLUSH(hw);
227
228 udelay(50);
229
230 e1000_raise_ee_clk(hw, &eecd);
231 e1000_lower_ee_clk(hw, &eecd);
232
233 mask = mask >> 1;
234
235 } while (mask);
236
237 /* We leave the "DI" bit set to "0" when we leave this routine. */
238 eecd &= ~E1000_EECD_DI;
239 E1000_WRITE_REG(hw, EECD, eecd);
240}
241
242/******************************************************************************
243 * Shift data bits in from the EEPROM
244 *
245 * hw - Struct containing variables accessed by shared code
246 *****************************************************************************/
247static uint16_t
Roy Zang28f7a052009-07-31 13:34:02 +0800248e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
wdenk4e112c12003-06-03 23:54:09 +0000249{
250 uint32_t eecd;
251 uint32_t i;
252 uint16_t data;
253
Roy Zang28f7a052009-07-31 13:34:02 +0800254 /* In order to read a register from the EEPROM, we need to shift 'count'
255 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
256 * input to the EEPROM (setting the SK bit), and then reading the
257 * value of the "DO" bit. During this "shifting in" process the
258 * "DI" bit should always be clear.
wdenk4e112c12003-06-03 23:54:09 +0000259 */
260
261 eecd = E1000_READ_REG(hw, EECD);
262
263 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
264 data = 0;
265
Roy Zang28f7a052009-07-31 13:34:02 +0800266 for (i = 0; i < count; i++) {
wdenk4e112c12003-06-03 23:54:09 +0000267 data = data << 1;
268 e1000_raise_ee_clk(hw, &eecd);
269
270 eecd = E1000_READ_REG(hw, EECD);
271
272 eecd &= ~(E1000_EECD_DI);
273 if (eecd & E1000_EECD_DO)
274 data |= 1;
275
276 e1000_lower_ee_clk(hw, &eecd);
277 }
278
279 return data;
280}
281
282/******************************************************************************
Roy Zang28f7a052009-07-31 13:34:02 +0800283 * Returns EEPROM to a "standby" state
wdenk4e112c12003-06-03 23:54:09 +0000284 *
285 * hw - Struct containing variables accessed by shared code
wdenk4e112c12003-06-03 23:54:09 +0000286 *****************************************************************************/
Kyle Moffett142cbf82011-10-18 11:05:28 +0000287void e1000_standby_eeprom(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +0000288{
Roy Zang28f7a052009-07-31 13:34:02 +0800289 struct e1000_eeprom_info *eeprom = &hw->eeprom;
wdenk4e112c12003-06-03 23:54:09 +0000290 uint32_t eecd;
291
292 eecd = E1000_READ_REG(hw, EECD);
293
Roy Zang28f7a052009-07-31 13:34:02 +0800294 if (eeprom->type == e1000_eeprom_microwire) {
295 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
296 E1000_WRITE_REG(hw, EECD, eecd);
297 E1000_WRITE_FLUSH(hw);
298 udelay(eeprom->delay_usec);
wdenk4e112c12003-06-03 23:54:09 +0000299
Roy Zang28f7a052009-07-31 13:34:02 +0800300 /* Clock high */
301 eecd |= E1000_EECD_SK;
302 E1000_WRITE_REG(hw, EECD, eecd);
303 E1000_WRITE_FLUSH(hw);
304 udelay(eeprom->delay_usec);
305
306 /* Select EEPROM */
307 eecd |= E1000_EECD_CS;
308 E1000_WRITE_REG(hw, EECD, eecd);
309 E1000_WRITE_FLUSH(hw);
310 udelay(eeprom->delay_usec);
311
312 /* Clock low */
313 eecd &= ~E1000_EECD_SK;
314 E1000_WRITE_REG(hw, EECD, eecd);
315 E1000_WRITE_FLUSH(hw);
316 udelay(eeprom->delay_usec);
317 } else if (eeprom->type == e1000_eeprom_spi) {
318 /* Toggle CS to flush commands */
319 eecd |= E1000_EECD_CS;
320 E1000_WRITE_REG(hw, EECD, eecd);
321 E1000_WRITE_FLUSH(hw);
322 udelay(eeprom->delay_usec);
323 eecd &= ~E1000_EECD_CS;
324 E1000_WRITE_REG(hw, EECD, eecd);
325 E1000_WRITE_FLUSH(hw);
326 udelay(eeprom->delay_usec);
327 }
328}
329
330/***************************************************************************
331* Description: Determines if the onboard NVM is FLASH or EEPROM.
332*
333* hw - Struct containing variables accessed by shared code
334****************************************************************************/
York Sun4a598092013-04-01 11:29:11 -0700335static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
Roy Zang28f7a052009-07-31 13:34:02 +0800336{
337 uint32_t eecd = 0;
338
339 DEBUGFUNC();
340
341 if (hw->mac_type == e1000_ich8lan)
York Sun4a598092013-04-01 11:29:11 -0700342 return false;
Roy Zang28f7a052009-07-31 13:34:02 +0800343
Roy Zang181119b2011-01-21 11:29:38 +0800344 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
Roy Zang28f7a052009-07-31 13:34:02 +0800345 eecd = E1000_READ_REG(hw, EECD);
346
347 /* Isolate bits 15 & 16 */
348 eecd = ((eecd >> 15) & 0x03);
349
350 /* If both bits are set, device is Flash type */
351 if (eecd == 0x03)
York Sun4a598092013-04-01 11:29:11 -0700352 return false;
Roy Zang28f7a052009-07-31 13:34:02 +0800353 }
York Sun4a598092013-04-01 11:29:11 -0700354 return true;
wdenk4e112c12003-06-03 23:54:09 +0000355}
356
357/******************************************************************************
Roy Zang28f7a052009-07-31 13:34:02 +0800358 * Prepares EEPROM for access
wdenk57b2d802003-06-27 21:31:46 +0000359 *
wdenk4e112c12003-06-03 23:54:09 +0000360 * hw - Struct containing variables accessed by shared code
Roy Zang28f7a052009-07-31 13:34:02 +0800361 *
362 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
363 * function should be called before issuing a command to the EEPROM.
wdenk4e112c12003-06-03 23:54:09 +0000364 *****************************************************************************/
Kyle Moffett142cbf82011-10-18 11:05:28 +0000365int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +0000366{
Roy Zang28f7a052009-07-31 13:34:02 +0800367 struct e1000_eeprom_info *eeprom = &hw->eeprom;
368 uint32_t eecd, i = 0;
369
Timur Tabiedc45b52009-08-17 15:55:38 -0500370 DEBUGFUNC();
wdenk4e112c12003-06-03 23:54:09 +0000371
Roy Zang28f7a052009-07-31 13:34:02 +0800372 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
373 return -E1000_ERR_SWFW_SYNC;
wdenk4e112c12003-06-03 23:54:09 +0000374 eecd = E1000_READ_REG(hw, EECD);
375
Marek Vasut74a13c22014-08-08 07:41:39 -0700376 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
Roy Zang28f7a052009-07-31 13:34:02 +0800377 /* Request EEPROM Access */
378 if (hw->mac_type > e1000_82544) {
379 eecd |= E1000_EECD_REQ;
380 E1000_WRITE_REG(hw, EECD, eecd);
381 eecd = E1000_READ_REG(hw, EECD);
382 while ((!(eecd & E1000_EECD_GNT)) &&
383 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
384 i++;
385 udelay(5);
386 eecd = E1000_READ_REG(hw, EECD);
387 }
388 if (!(eecd & E1000_EECD_GNT)) {
389 eecd &= ~E1000_EECD_REQ;
390 E1000_WRITE_REG(hw, EECD, eecd);
391 DEBUGOUT("Could not acquire EEPROM grant\n");
392 return -E1000_ERR_EEPROM;
393 }
394 }
395 }
wdenk4e112c12003-06-03 23:54:09 +0000396
Roy Zang28f7a052009-07-31 13:34:02 +0800397 /* Setup EEPROM for Read/Write */
wdenk4e112c12003-06-03 23:54:09 +0000398
Roy Zang28f7a052009-07-31 13:34:02 +0800399 if (eeprom->type == e1000_eeprom_microwire) {
400 /* Clear SK and DI */
401 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
402 E1000_WRITE_REG(hw, EECD, eecd);
wdenk4e112c12003-06-03 23:54:09 +0000403
Roy Zang28f7a052009-07-31 13:34:02 +0800404 /* Set CS */
405 eecd |= E1000_EECD_CS;
406 E1000_WRITE_REG(hw, EECD, eecd);
407 } else if (eeprom->type == e1000_eeprom_spi) {
408 /* Clear SK and CS */
409 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
410 E1000_WRITE_REG(hw, EECD, eecd);
411 udelay(1);
412 }
413
414 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +0000415}
416
417/******************************************************************************
Roy Zang28f7a052009-07-31 13:34:02 +0800418 * Sets up eeprom variables in the hw struct. Must be called after mac_type
419 * is configured. Additionally, if this is ICH8, the flash controller GbE
420 * registers must be mapped, or this will crash.
wdenk4e112c12003-06-03 23:54:09 +0000421 *
422 * hw - Struct containing variables accessed by shared code
wdenk4e112c12003-06-03 23:54:09 +0000423 *****************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +0800424static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +0000425{
Roy Zang28f7a052009-07-31 13:34:02 +0800426 struct e1000_eeprom_info *eeprom = &hw->eeprom;
Marek Vasut74a13c22014-08-08 07:41:39 -0700427 uint32_t eecd;
Roy Zang28f7a052009-07-31 13:34:02 +0800428 int32_t ret_val = E1000_SUCCESS;
429 uint16_t eeprom_size;
wdenk4e112c12003-06-03 23:54:09 +0000430
Marek Vasut74a13c22014-08-08 07:41:39 -0700431 if (hw->mac_type == e1000_igb)
432 eecd = E1000_READ_REG(hw, I210_EECD);
433 else
434 eecd = E1000_READ_REG(hw, EECD);
435
Timur Tabiedc45b52009-08-17 15:55:38 -0500436 DEBUGFUNC();
Roy Zang28f7a052009-07-31 13:34:02 +0800437
438 switch (hw->mac_type) {
439 case e1000_82542_rev2_0:
440 case e1000_82542_rev2_1:
441 case e1000_82543:
442 case e1000_82544:
443 eeprom->type = e1000_eeprom_microwire;
444 eeprom->word_size = 64;
445 eeprom->opcode_bits = 3;
446 eeprom->address_bits = 6;
447 eeprom->delay_usec = 50;
York Sun4a598092013-04-01 11:29:11 -0700448 eeprom->use_eerd = false;
449 eeprom->use_eewr = false;
Roy Zang28f7a052009-07-31 13:34:02 +0800450 break;
451 case e1000_82540:
452 case e1000_82545:
453 case e1000_82545_rev_3:
454 case e1000_82546:
455 case e1000_82546_rev_3:
456 eeprom->type = e1000_eeprom_microwire;
457 eeprom->opcode_bits = 3;
458 eeprom->delay_usec = 50;
459 if (eecd & E1000_EECD_SIZE) {
460 eeprom->word_size = 256;
461 eeprom->address_bits = 8;
462 } else {
463 eeprom->word_size = 64;
464 eeprom->address_bits = 6;
465 }
York Sun4a598092013-04-01 11:29:11 -0700466 eeprom->use_eerd = false;
467 eeprom->use_eewr = false;
Roy Zang28f7a052009-07-31 13:34:02 +0800468 break;
469 case e1000_82541:
470 case e1000_82541_rev_2:
471 case e1000_82547:
472 case e1000_82547_rev_2:
473 if (eecd & E1000_EECD_TYPE) {
474 eeprom->type = e1000_eeprom_spi;
475 eeprom->opcode_bits = 8;
476 eeprom->delay_usec = 1;
477 if (eecd & E1000_EECD_ADDR_BITS) {
478 eeprom->page_size = 32;
479 eeprom->address_bits = 16;
480 } else {
481 eeprom->page_size = 8;
482 eeprom->address_bits = 8;
483 }
484 } else {
485 eeprom->type = e1000_eeprom_microwire;
486 eeprom->opcode_bits = 3;
487 eeprom->delay_usec = 50;
488 if (eecd & E1000_EECD_ADDR_BITS) {
489 eeprom->word_size = 256;
490 eeprom->address_bits = 8;
491 } else {
492 eeprom->word_size = 64;
493 eeprom->address_bits = 6;
494 }
495 }
York Sun4a598092013-04-01 11:29:11 -0700496 eeprom->use_eerd = false;
497 eeprom->use_eewr = false;
Roy Zang28f7a052009-07-31 13:34:02 +0800498 break;
499 case e1000_82571:
500 case e1000_82572:
501 eeprom->type = e1000_eeprom_spi;
502 eeprom->opcode_bits = 8;
503 eeprom->delay_usec = 1;
504 if (eecd & E1000_EECD_ADDR_BITS) {
505 eeprom->page_size = 32;
506 eeprom->address_bits = 16;
507 } else {
508 eeprom->page_size = 8;
509 eeprom->address_bits = 8;
510 }
York Sun4a598092013-04-01 11:29:11 -0700511 eeprom->use_eerd = false;
512 eeprom->use_eewr = false;
Roy Zang28f7a052009-07-31 13:34:02 +0800513 break;
514 case e1000_82573:
Roy Zang181119b2011-01-21 11:29:38 +0800515 case e1000_82574:
Roy Zang28f7a052009-07-31 13:34:02 +0800516 eeprom->type = e1000_eeprom_spi;
517 eeprom->opcode_bits = 8;
518 eeprom->delay_usec = 1;
519 if (eecd & E1000_EECD_ADDR_BITS) {
520 eeprom->page_size = 32;
521 eeprom->address_bits = 16;
522 } else {
523 eeprom->page_size = 8;
524 eeprom->address_bits = 8;
wdenk4e112c12003-06-03 23:54:09 +0000525 }
York Sun4a598092013-04-01 11:29:11 -0700526 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
Marek Vasut74a13c22014-08-08 07:41:39 -0700527 eeprom->use_eerd = true;
528 eeprom->use_eewr = true;
529
Roy Zang28f7a052009-07-31 13:34:02 +0800530 eeprom->type = e1000_eeprom_flash;
531 eeprom->word_size = 2048;
532
533 /* Ensure that the Autonomous FLASH update bit is cleared due to
534 * Flash update issue on parts which use a FLASH for NVM. */
535 eecd &= ~E1000_EECD_AUPDEN;
wdenk4e112c12003-06-03 23:54:09 +0000536 E1000_WRITE_REG(hw, EECD, eecd);
wdenk4e112c12003-06-03 23:54:09 +0000537 }
Roy Zang28f7a052009-07-31 13:34:02 +0800538 break;
539 case e1000_80003es2lan:
540 eeprom->type = e1000_eeprom_spi;
541 eeprom->opcode_bits = 8;
542 eeprom->delay_usec = 1;
543 if (eecd & E1000_EECD_ADDR_BITS) {
544 eeprom->page_size = 32;
545 eeprom->address_bits = 16;
546 } else {
547 eeprom->page_size = 8;
548 eeprom->address_bits = 8;
549 }
York Sun4a598092013-04-01 11:29:11 -0700550 eeprom->use_eerd = true;
551 eeprom->use_eewr = false;
Roy Zang28f7a052009-07-31 13:34:02 +0800552 break;
Marek Vasut74a13c22014-08-08 07:41:39 -0700553 case e1000_igb:
554 /* i210 has 4k of iNVM mapped as EEPROM */
555 eeprom->type = e1000_eeprom_invm;
556 eeprom->opcode_bits = 8;
557 eeprom->delay_usec = 1;
558 eeprom->page_size = 32;
559 eeprom->address_bits = 16;
560 eeprom->use_eerd = true;
561 eeprom->use_eewr = false;
562 break;
Roy Zang28f7a052009-07-31 13:34:02 +0800563 default:
564 break;
wdenk4e112c12003-06-03 23:54:09 +0000565 }
566
Marek Vasut74a13c22014-08-08 07:41:39 -0700567 if (eeprom->type == e1000_eeprom_spi ||
568 eeprom->type == e1000_eeprom_invm) {
Roy Zang28f7a052009-07-31 13:34:02 +0800569 /* eeprom_size will be an enum [0..8] that maps
570 * to eeprom sizes 128B to
571 * 32KB (incremented by powers of 2).
572 */
573 if (hw->mac_type <= e1000_82547_rev_2) {
574 /* Set to default value for initial eeprom read. */
575 eeprom->word_size = 64;
576 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
577 &eeprom_size);
578 if (ret_val)
579 return ret_val;
580 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
581 >> EEPROM_SIZE_SHIFT;
582 /* 256B eeprom size was not supported in earlier
583 * hardware, so we bump eeprom_size up one to
584 * ensure that "1" (which maps to 256B) is never
585 * the result used in the shifting logic below. */
586 if (eeprom_size)
587 eeprom_size++;
588 } else {
589 eeprom_size = (uint16_t)((eecd &
590 E1000_EECD_SIZE_EX_MASK) >>
591 E1000_EECD_SIZE_EX_SHIFT);
592 }
593
594 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
595 }
596 return ret_val;
wdenk4e112c12003-06-03 23:54:09 +0000597}
598
Roy Zang28f7a052009-07-31 13:34:02 +0800599/******************************************************************************
600 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
601 *
602 * hw - Struct containing variables accessed by shared code
603 *****************************************************************************/
604static int32_t
605e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
wdenk4e112c12003-06-03 23:54:09 +0000606{
Roy Zang28f7a052009-07-31 13:34:02 +0800607 uint32_t attempts = 100000;
608 uint32_t i, reg = 0;
609 int32_t done = E1000_ERR_EEPROM;
wdenk4e112c12003-06-03 23:54:09 +0000610
Roy Zang28f7a052009-07-31 13:34:02 +0800611 for (i = 0; i < attempts; i++) {
Marek Vasut74a13c22014-08-08 07:41:39 -0700612 if (eerd == E1000_EEPROM_POLL_READ) {
613 if (hw->mac_type == e1000_igb)
614 reg = E1000_READ_REG(hw, I210_EERD);
615 else
616 reg = E1000_READ_REG(hw, EERD);
617 } else {
618 if (hw->mac_type == e1000_igb)
619 reg = E1000_READ_REG(hw, I210_EEWR);
620 else
621 reg = E1000_READ_REG(hw, EEWR);
622 }
Roy Zang28f7a052009-07-31 13:34:02 +0800623
624 if (reg & E1000_EEPROM_RW_REG_DONE) {
625 done = E1000_SUCCESS;
626 break;
627 }
628 udelay(5);
629 }
630
631 return done;
wdenk4e112c12003-06-03 23:54:09 +0000632}
633
Roy Zang28f7a052009-07-31 13:34:02 +0800634/******************************************************************************
635 * Reads a 16 bit word from the EEPROM using the EERD register.
636 *
637 * hw - Struct containing variables accessed by shared code
638 * offset - offset of word in the EEPROM to read
639 * data - word read from the EEPROM
640 * words - number of words to read
641 *****************************************************************************/
642static int32_t
643e1000_read_eeprom_eerd(struct e1000_hw *hw,
644 uint16_t offset,
645 uint16_t words,
646 uint16_t *data)
wdenk4e112c12003-06-03 23:54:09 +0000647{
Roy Zang28f7a052009-07-31 13:34:02 +0800648 uint32_t i, eerd = 0;
649 int32_t error = 0;
wdenk4e112c12003-06-03 23:54:09 +0000650
Roy Zang28f7a052009-07-31 13:34:02 +0800651 for (i = 0; i < words; i++) {
652 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
653 E1000_EEPROM_RW_REG_START;
654
Marek Vasut74a13c22014-08-08 07:41:39 -0700655 if (hw->mac_type == e1000_igb)
656 E1000_WRITE_REG(hw, I210_EERD, eerd);
657 else
658 E1000_WRITE_REG(hw, EERD, eerd);
659
Roy Zang28f7a052009-07-31 13:34:02 +0800660 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
661
662 if (error)
663 break;
Marek Vasut74a13c22014-08-08 07:41:39 -0700664
665 if (hw->mac_type == e1000_igb) {
666 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
Roy Zang28f7a052009-07-31 13:34:02 +0800667 E1000_EEPROM_RW_REG_DATA);
Marek Vasut74a13c22014-08-08 07:41:39 -0700668 } else {
669 data[i] = (E1000_READ_REG(hw, EERD) >>
670 E1000_EEPROM_RW_REG_DATA);
671 }
Roy Zang28f7a052009-07-31 13:34:02 +0800672
wdenk4e112c12003-06-03 23:54:09 +0000673 }
Roy Zang28f7a052009-07-31 13:34:02 +0800674
675 return error;
wdenk4e112c12003-06-03 23:54:09 +0000676}
677
Kyle Moffett142cbf82011-10-18 11:05:28 +0000678void e1000_release_eeprom(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +0000679{
680 uint32_t eecd;
wdenk4e112c12003-06-03 23:54:09 +0000681
Roy Zang28f7a052009-07-31 13:34:02 +0800682 DEBUGFUNC();
683
684 eecd = E1000_READ_REG(hw, EECD);
685
686 if (hw->eeprom.type == e1000_eeprom_spi) {
687 eecd |= E1000_EECD_CS; /* Pull CS high */
688 eecd &= ~E1000_EECD_SK; /* Lower SCK */
689
wdenk4e112c12003-06-03 23:54:09 +0000690 E1000_WRITE_REG(hw, EECD, eecd);
Roy Zang28f7a052009-07-31 13:34:02 +0800691
692 udelay(hw->eeprom.delay_usec);
693 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
694 /* cleanup eeprom */
695
696 /* CS on Microwire is active-high */
697 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
698
699 E1000_WRITE_REG(hw, EECD, eecd);
700
701 /* Rising edge of clock */
702 eecd |= E1000_EECD_SK;
703 E1000_WRITE_REG(hw, EECD, eecd);
704 E1000_WRITE_FLUSH(hw);
705 udelay(hw->eeprom.delay_usec);
706
707 /* Falling edge of clock */
708 eecd &= ~E1000_EECD_SK;
709 E1000_WRITE_REG(hw, EECD, eecd);
710 E1000_WRITE_FLUSH(hw);
711 udelay(hw->eeprom.delay_usec);
wdenk4e112c12003-06-03 23:54:09 +0000712 }
wdenk4e112c12003-06-03 23:54:09 +0000713
714 /* Stop requesting EEPROM access */
715 if (hw->mac_type > e1000_82544) {
wdenk4e112c12003-06-03 23:54:09 +0000716 eecd &= ~E1000_EECD_REQ;
717 E1000_WRITE_REG(hw, EECD, eecd);
718 }
Tim Harvey5cb59ec2015-05-19 10:01:18 -0700719
720 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
wdenk4e112c12003-06-03 23:54:09 +0000721}
Tim Harvey5cb59ec2015-05-19 10:01:18 -0700722
wdenk4e112c12003-06-03 23:54:09 +0000723/******************************************************************************
Roy Zang28f7a052009-07-31 13:34:02 +0800724 * Reads a 16 bit word from the EEPROM.
wdenk57b2d802003-06-27 21:31:46 +0000725 *
wdenk4e112c12003-06-03 23:54:09 +0000726 * hw - Struct containing variables accessed by shared code
wdenk4e112c12003-06-03 23:54:09 +0000727 *****************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +0800728static int32_t
729e1000_spi_eeprom_ready(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +0000730{
Roy Zang28f7a052009-07-31 13:34:02 +0800731 uint16_t retry_count = 0;
732 uint8_t spi_stat_reg;
wdenk4e112c12003-06-03 23:54:09 +0000733
734 DEBUGFUNC();
735
Roy Zang28f7a052009-07-31 13:34:02 +0800736 /* Read "Status Register" repeatedly until the LSB is cleared. The
737 * EEPROM will signal that the command has been completed by clearing
738 * bit 0 of the internal status register. If it's not cleared within
739 * 5 milliseconds, then error out.
740 */
741 retry_count = 0;
742 do {
743 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
744 hw->eeprom.opcode_bits);
745 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
746 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
747 break;
wdenk57b2d802003-06-27 21:31:46 +0000748
Roy Zang28f7a052009-07-31 13:34:02 +0800749 udelay(5);
750 retry_count += 5;
751
752 e1000_standby_eeprom(hw);
753 } while (retry_count < EEPROM_MAX_RETRY_SPI);
754
755 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
756 * only 0-5mSec on 5V devices)
757 */
758 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
759 DEBUGOUT("SPI EEPROM Status error\n");
wdenk4e112c12003-06-03 23:54:09 +0000760 return -E1000_ERR_EEPROM;
761 }
Roy Zang28f7a052009-07-31 13:34:02 +0800762
763 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +0000764}
765
766/******************************************************************************
Roy Zang28f7a052009-07-31 13:34:02 +0800767 * Reads a 16 bit word from the EEPROM.
wdenk4e112c12003-06-03 23:54:09 +0000768 *
Roy Zang28f7a052009-07-31 13:34:02 +0800769 * hw - Struct containing variables accessed by shared code
770 * offset - offset of word in the EEPROM to read
771 * data - word read from the EEPROM
wdenk4e112c12003-06-03 23:54:09 +0000772 *****************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +0800773static int32_t
774e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
775 uint16_t words, uint16_t *data)
wdenk4e112c12003-06-03 23:54:09 +0000776{
Roy Zang28f7a052009-07-31 13:34:02 +0800777 struct e1000_eeprom_info *eeprom = &hw->eeprom;
778 uint32_t i = 0;
wdenk4e112c12003-06-03 23:54:09 +0000779
780 DEBUGFUNC();
781
Roy Zang28f7a052009-07-31 13:34:02 +0800782 /* If eeprom is not yet detected, do so now */
783 if (eeprom->word_size == 0)
784 e1000_init_eeprom_params(hw);
785
786 /* A check for invalid values: offset too large, too many words,
787 * and not enough words.
788 */
789 if ((offset >= eeprom->word_size) ||
790 (words > eeprom->word_size - offset) ||
791 (words == 0)) {
792 DEBUGOUT("\"words\" parameter out of bounds."
793 "Words = %d, size = %d\n", offset, eeprom->word_size);
794 return -E1000_ERR_EEPROM;
795 }
796
797 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
798 * directly. In this case, we need to acquire the EEPROM so that
799 * FW or other port software does not interrupt.
800 */
York Sun4a598092013-04-01 11:29:11 -0700801 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
802 hw->eeprom.use_eerd == false) {
Roy Zang28f7a052009-07-31 13:34:02 +0800803
804 /* Prepare the EEPROM for bit-bang reading */
805 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
806 return -E1000_ERR_EEPROM;
807 }
808
809 /* Eerd register EEPROM access requires no eeprom aquire/release */
York Sun4a598092013-04-01 11:29:11 -0700810 if (eeprom->use_eerd == true)
Roy Zang28f7a052009-07-31 13:34:02 +0800811 return e1000_read_eeprom_eerd(hw, offset, words, data);
812
Roy Zang28f7a052009-07-31 13:34:02 +0800813 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
814 * acquired the EEPROM at this point, so any returns should relase it */
815 if (eeprom->type == e1000_eeprom_spi) {
816 uint16_t word_in;
817 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
818
819 if (e1000_spi_eeprom_ready(hw)) {
820 e1000_release_eeprom(hw);
821 return -E1000_ERR_EEPROM;
822 }
823
824 e1000_standby_eeprom(hw);
825
826 /* Some SPI eeproms use the 8th address bit embedded in
827 * the opcode */
828 if ((eeprom->address_bits == 8) && (offset >= 128))
829 read_opcode |= EEPROM_A8_OPCODE_SPI;
830
831 /* Send the READ command (opcode + addr) */
832 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
833 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
834 eeprom->address_bits);
835
836 /* Read the data. The address of the eeprom internally
837 * increments with each byte (spi) being read, saving on the
838 * overhead of eeprom setup and tear-down. The address
839 * counter will roll over if reading beyond the size of
840 * the eeprom, thus allowing the entire memory to be read
841 * starting from any offset. */
842 for (i = 0; i < words; i++) {
843 word_in = e1000_shift_in_ee_bits(hw, 16);
844 data[i] = (word_in >> 8) | (word_in << 8);
845 }
846 } else if (eeprom->type == e1000_eeprom_microwire) {
847 for (i = 0; i < words; i++) {
848 /* Send the READ command (opcode + addr) */
849 e1000_shift_out_ee_bits(hw,
850 EEPROM_READ_OPCODE_MICROWIRE,
851 eeprom->opcode_bits);
852 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
853 eeprom->address_bits);
854
855 /* Read the data. For microwire, each word requires
856 * the overhead of eeprom setup and tear-down. */
857 data[i] = e1000_shift_in_ee_bits(hw, 16);
858 e1000_standby_eeprom(hw);
859 }
860 }
861
862 /* End this read operation */
863 e1000_release_eeprom(hw);
864
865 return E1000_SUCCESS;
866}
867
Hannu Lounentoc56999e2018-01-10 20:31:24 +0100868/******************************************************************************
869 * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
870 * @hw: pointer to the HW structure
871 * @offset: offset within the Shadow Ram to be written to
872 * @words: number of words to write
873 * @data: 16 bit word(s) to be written to the Shadow Ram
874 *
875 * Writes data to Shadow Ram at offset using EEWR register.
876 *
877 * If e1000_update_eeprom_checksum_i210 is not called after this function, the
878 * Shadow Ram will most likely contain an invalid checksum.
879 *****************************************************************************/
880static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
881 uint16_t words, uint16_t *data)
882{
883 struct e1000_eeprom_info *eeprom = &hw->eeprom;
884 uint32_t i, k, eewr = 0;
885 uint32_t attempts = 100000;
886 int32_t ret_val = 0;
887
888 /* A check for invalid values: offset too large, too many words,
889 * too many words for the offset, and not enough words.
890 */
891 if ((offset >= eeprom->word_size) ||
892 (words > (eeprom->word_size - offset)) || (words == 0)) {
893 DEBUGOUT("nvm parameter(s) out of bounds\n");
894 ret_val = -E1000_ERR_EEPROM;
895 goto out;
896 }
897
898 for (i = 0; i < words; i++) {
899 eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
900 | (data[i] << E1000_EEPROM_RW_REG_DATA) |
901 E1000_EEPROM_RW_REG_START;
902
903 E1000_WRITE_REG(hw, I210_EEWR, eewr);
904
905 for (k = 0; k < attempts; k++) {
906 if (E1000_EEPROM_RW_REG_DONE &
907 E1000_READ_REG(hw, I210_EEWR)) {
908 ret_val = 0;
909 break;
910 }
911 udelay(5);
912 }
913
914 if (ret_val) {
915 DEBUGOUT("Shadow RAM write EEWR timed out\n");
916 break;
917 }
918 }
919
920out:
921 return ret_val;
922}
923
924/******************************************************************************
925 * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
926 * @hw: pointer to the HW structure
927 *
928 *****************************************************************************/
929static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
930{
931 int32_t ret_val = -E1000_ERR_EEPROM;
932 uint32_t i, reg;
933
934 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
935 reg = E1000_READ_REG(hw, EECD);
936 if (reg & E1000_EECD_FLUDONE_I210) {
937 ret_val = 0;
938 break;
939 }
940 udelay(5);
941 }
942
943 return ret_val;
944}
945
946/******************************************************************************
947 * e1000_update_flash_i210 - Commit EEPROM to the flash
948 * @hw: pointer to the HW structure
949 *
950 *****************************************************************************/
951static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
952{
953 int32_t ret_val = 0;
954 uint32_t flup;
955
956 ret_val = e1000_pool_flash_update_done_i210(hw);
957 if (ret_val == -E1000_ERR_EEPROM) {
958 DEBUGOUT("Flash update time out\n");
959 goto out;
960 }
961
962 flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
963 E1000_WRITE_REG(hw, EECD, flup);
964
965 ret_val = e1000_pool_flash_update_done_i210(hw);
966 if (ret_val)
967 DEBUGOUT("Flash update time out\n");
968 else
969 DEBUGOUT("Flash update complete\n");
970
971out:
972 return ret_val;
973}
974
975/******************************************************************************
976 * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
977 * @hw: pointer to the HW structure
978 *
979 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
980 * up to the checksum. Then calculates the EEPROM checksum and writes the
981 * value to the EEPROM. Next commit EEPROM data onto the Flash.
982 *****************************************************************************/
983static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
984{
985 int32_t ret_val = 0;
986 uint16_t checksum = 0;
987 uint16_t i, nvm_data;
988
989 /* Read the first word from the EEPROM. If this times out or fails, do
990 * not continue or we could be in for a very long wait while every
991 * EEPROM read fails
992 */
993 ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
994 if (ret_val) {
995 DEBUGOUT("EEPROM read failed\n");
996 goto out;
997 }
998
999 if (!(e1000_get_hw_eeprom_semaphore(hw))) {
1000 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
1001 * because we do not want to take the synchronization
1002 * semaphores twice here.
1003 */
1004
1005 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
1006 ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
1007 if (ret_val) {
1008 e1000_put_hw_eeprom_semaphore(hw);
1009 DEBUGOUT("EEPROM Read Error while updating checksum.\n");
1010 goto out;
1011 }
1012 checksum += nvm_data;
1013 }
1014 checksum = (uint16_t)EEPROM_SUM - checksum;
1015 ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
1016 &checksum);
1017 if (ret_val) {
1018 e1000_put_hw_eeprom_semaphore(hw);
1019 DEBUGOUT("EEPROM Write Error while updating checksum.\n");
1020 goto out;
1021 }
1022
1023 e1000_put_hw_eeprom_semaphore(hw);
1024
1025 ret_val = e1000_update_flash_i210(hw);
1026 } else {
1027 ret_val = -E1000_ERR_SWFW_SYNC;
1028 }
1029
1030out:
1031 return ret_val;
1032}
Hannu Lounentoc56999e2018-01-10 20:31:24 +01001033
Roy Zang28f7a052009-07-31 13:34:02 +08001034/******************************************************************************
1035 * Verifies that the EEPROM has a valid checksum
1036 *
1037 * hw - Struct containing variables accessed by shared code
1038 *
1039 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
1040 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
1041 * valid.
1042 *****************************************************************************/
Kyle Moffett70946bc2011-10-18 11:05:27 +00001043static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
Roy Zang28f7a052009-07-31 13:34:02 +08001044{
Kyle Moffett70946bc2011-10-18 11:05:27 +00001045 uint16_t i, checksum, checksum_reg, *buf;
Roy Zang28f7a052009-07-31 13:34:02 +08001046
1047 DEBUGFUNC();
1048
Kyle Moffett70946bc2011-10-18 11:05:27 +00001049 /* Allocate a temporary buffer */
1050 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
1051 if (!buf) {
Simon Glassc53abc32015-08-19 09:33:39 -06001052 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
Kyle Moffett70946bc2011-10-18 11:05:27 +00001053 return -E1000_ERR_EEPROM;
Roy Zang28f7a052009-07-31 13:34:02 +08001054 }
1055
Kyle Moffett70946bc2011-10-18 11:05:27 +00001056 /* Read the EEPROM */
1057 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
Simon Glassc53abc32015-08-19 09:33:39 -06001058 E1000_ERR(hw, "Unable to read EEPROM!\n");
Roy Zang28f7a052009-07-31 13:34:02 +08001059 return -E1000_ERR_EEPROM;
1060 }
Kyle Moffett70946bc2011-10-18 11:05:27 +00001061
1062 /* Compute the checksum */
Wolfgang Denk15690332011-10-28 07:37:04 +02001063 checksum = 0;
Kyle Moffett70946bc2011-10-18 11:05:27 +00001064 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1065 checksum += buf[i];
1066 checksum = ((uint16_t)EEPROM_SUM) - checksum;
1067 checksum_reg = buf[i];
1068
1069 /* Verify it! */
1070 if (checksum == checksum_reg)
1071 return 0;
1072
1073 /* Hrm, verification failed, print an error */
Simon Glassc53abc32015-08-19 09:33:39 -06001074 E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
1075 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
1076 checksum_reg, checksum);
Kyle Moffett70946bc2011-10-18 11:05:27 +00001077
1078 return -E1000_ERR_EEPROM;
Roy Zang9b7c4302009-08-11 03:48:05 +08001079}
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001080#endif /* CONFIG_E1000_NO_NVM */
Roy Zang9b7c4302009-08-11 03:48:05 +08001081
1082/*****************************************************************************
1083 * Set PHY to class A mode
1084 * Assumes the following operations will follow to enable the new class mode.
1085 * 1. Do a PHY soft reset
1086 * 2. Restart auto-negotiation or force link.
1087 *
1088 * hw - Struct containing variables accessed by shared code
1089 ****************************************************************************/
1090static int32_t
1091e1000_set_phy_mode(struct e1000_hw *hw)
1092{
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001093#ifndef CONFIG_E1000_NO_NVM
Roy Zang9b7c4302009-08-11 03:48:05 +08001094 int32_t ret_val;
1095 uint16_t eeprom_data;
1096
1097 DEBUGFUNC();
1098
1099 if ((hw->mac_type == e1000_82545_rev_3) &&
1100 (hw->media_type == e1000_media_type_copper)) {
1101 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1102 1, &eeprom_data);
1103 if (ret_val)
1104 return ret_val;
1105
1106 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
1107 (eeprom_data & EEPROM_PHY_CLASS_A)) {
1108 ret_val = e1000_write_phy_reg(hw,
1109 M88E1000_PHY_PAGE_SELECT, 0x000B);
1110 if (ret_val)
1111 return ret_val;
1112 ret_val = e1000_write_phy_reg(hw,
1113 M88E1000_PHY_GEN_CONTROL, 0x8104);
1114 if (ret_val)
1115 return ret_val;
1116
York Sun4a598092013-04-01 11:29:11 -07001117 hw->phy_reset_disable = false;
Roy Zang9b7c4302009-08-11 03:48:05 +08001118 }
1119 }
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001120#endif
Roy Zang9b7c4302009-08-11 03:48:05 +08001121 return E1000_SUCCESS;
Roy Zang28f7a052009-07-31 13:34:02 +08001122}
Roy Zang28f7a052009-07-31 13:34:02 +08001123
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001124#ifndef CONFIG_E1000_NO_NVM
Roy Zang28f7a052009-07-31 13:34:02 +08001125/***************************************************************************
1126 *
1127 * Obtaining software semaphore bit (SMBI) before resetting PHY.
1128 *
1129 * hw: Struct containing variables accessed by shared code
1130 *
1131 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
1132 * E1000_SUCCESS at any other case.
1133 *
1134 ***************************************************************************/
1135static int32_t
1136e1000_get_software_semaphore(struct e1000_hw *hw)
1137{
1138 int32_t timeout = hw->eeprom.word_size + 1;
1139 uint32_t swsm;
1140
1141 DEBUGFUNC();
1142
Hannu Lounentoc56999e2018-01-10 20:31:24 +01001143 if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
Roy Zang28f7a052009-07-31 13:34:02 +08001144 return E1000_SUCCESS;
1145
1146 while (timeout) {
1147 swsm = E1000_READ_REG(hw, SWSM);
1148 /* If SMBI bit cleared, it is now set and we hold
1149 * the semaphore */
1150 if (!(swsm & E1000_SWSM_SMBI))
1151 break;
1152 mdelay(1);
1153 timeout--;
1154 }
1155
1156 if (!timeout) {
1157 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1158 return -E1000_ERR_RESET;
1159 }
1160
1161 return E1000_SUCCESS;
1162}
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001163#endif
Roy Zang28f7a052009-07-31 13:34:02 +08001164
1165/***************************************************************************
1166 * This function clears HW semaphore bits.
1167 *
1168 * hw: Struct containing variables accessed by shared code
1169 *
1170 * returns: - None.
1171 *
1172 ***************************************************************************/
1173static void
1174e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1175{
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001176#ifndef CONFIG_E1000_NO_NVM
Roy Zang28f7a052009-07-31 13:34:02 +08001177 uint32_t swsm;
1178
1179 DEBUGFUNC();
1180
1181 if (!hw->eeprom_semaphore_present)
1182 return;
1183
1184 swsm = E1000_READ_REG(hw, SWSM);
Bernhard Messerklinger801ae712018-02-15 08:55:49 +01001185 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
Roy Zang28f7a052009-07-31 13:34:02 +08001186 /* Release both semaphores. */
1187 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1188 } else
1189 swsm &= ~(E1000_SWSM_SWESMBI);
1190 E1000_WRITE_REG(hw, SWSM, swsm);
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001191#endif
Roy Zang28f7a052009-07-31 13:34:02 +08001192}
1193
1194/***************************************************************************
1195 *
1196 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1197 * adapter or Eeprom access.
1198 *
1199 * hw: Struct containing variables accessed by shared code
1200 *
1201 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1202 * E1000_SUCCESS at any other case.
1203 *
1204 ***************************************************************************/
1205static int32_t
1206e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1207{
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001208#ifndef CONFIG_E1000_NO_NVM
Roy Zang28f7a052009-07-31 13:34:02 +08001209 int32_t timeout;
1210 uint32_t swsm;
1211
1212 DEBUGFUNC();
1213
1214 if (!hw->eeprom_semaphore_present)
1215 return E1000_SUCCESS;
1216
Hannu Lounentoc56999e2018-01-10 20:31:24 +01001217 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
Roy Zang28f7a052009-07-31 13:34:02 +08001218 /* Get the SW semaphore. */
1219 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1220 return -E1000_ERR_EEPROM;
1221 }
1222
1223 /* Get the FW semaphore. */
1224 timeout = hw->eeprom.word_size + 1;
1225 while (timeout) {
1226 swsm = E1000_READ_REG(hw, SWSM);
1227 swsm |= E1000_SWSM_SWESMBI;
1228 E1000_WRITE_REG(hw, SWSM, swsm);
1229 /* if we managed to set the bit we got the semaphore. */
1230 swsm = E1000_READ_REG(hw, SWSM);
1231 if (swsm & E1000_SWSM_SWESMBI)
1232 break;
1233
1234 udelay(50);
1235 timeout--;
1236 }
1237
1238 if (!timeout) {
1239 /* Release semaphores */
1240 e1000_put_hw_eeprom_semaphore(hw);
1241 DEBUGOUT("Driver can't access the Eeprom - "
1242 "SWESMBI bit is set.\n");
1243 return -E1000_ERR_EEPROM;
1244 }
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001245#endif
Roy Zang28f7a052009-07-31 13:34:02 +08001246 return E1000_SUCCESS;
1247}
1248
Tim Harvey5cb59ec2015-05-19 10:01:18 -07001249/* Take ownership of the PHY */
Roy Zang28f7a052009-07-31 13:34:02 +08001250static int32_t
1251e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1252{
1253 uint32_t swfw_sync = 0;
1254 uint32_t swmask = mask;
1255 uint32_t fwmask = mask << 16;
1256 int32_t timeout = 200;
1257
1258 DEBUGFUNC();
1259 while (timeout) {
1260 if (e1000_get_hw_eeprom_semaphore(hw))
1261 return -E1000_ERR_SWFW_SYNC;
1262
Tim Harveydca35652015-05-19 10:01:19 -07001263 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
York Sun4303a832014-10-17 13:44:06 -07001264 if (!(swfw_sync & (fwmask | swmask)))
Roy Zang28f7a052009-07-31 13:34:02 +08001265 break;
1266
1267 /* firmware currently using resource (fwmask) */
1268 /* or other software thread currently using resource (swmask) */
1269 e1000_put_hw_eeprom_semaphore(hw);
1270 mdelay(5);
1271 timeout--;
1272 }
1273
1274 if (!timeout) {
1275 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1276 return -E1000_ERR_SWFW_SYNC;
1277 }
1278
1279 swfw_sync |= swmask;
1280 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1281
1282 e1000_put_hw_eeprom_semaphore(hw);
1283 return E1000_SUCCESS;
1284}
1285
Tim Harvey5cb59ec2015-05-19 10:01:18 -07001286static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1287{
1288 uint32_t swfw_sync = 0;
1289
1290 DEBUGFUNC();
1291 while (e1000_get_hw_eeprom_semaphore(hw))
1292 ; /* Empty */
1293
1294 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1295 swfw_sync &= ~mask;
1296 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1297
1298 e1000_put_hw_eeprom_semaphore(hw);
1299}
1300
York Sun4a598092013-04-01 11:29:11 -07001301static bool e1000_is_second_port(struct e1000_hw *hw)
Kyle Moffett7376f8d2010-09-13 05:52:22 +00001302{
1303 switch (hw->mac_type) {
1304 case e1000_80003es2lan:
1305 case e1000_82546:
1306 case e1000_82571:
1307 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
York Sun4a598092013-04-01 11:29:11 -07001308 return true;
Kyle Moffett7376f8d2010-09-13 05:52:22 +00001309 /* Fallthrough */
1310 default:
York Sun4a598092013-04-01 11:29:11 -07001311 return false;
Kyle Moffett7376f8d2010-09-13 05:52:22 +00001312 }
1313}
1314
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001315#ifndef CONFIG_E1000_NO_NVM
Roy Zang28f7a052009-07-31 13:34:02 +08001316/******************************************************************************
Hannu Lounentof36be3c2018-01-10 20:31:25 +01001317 * Reads the adapter's MAC address from the EEPROM
Roy Zang28f7a052009-07-31 13:34:02 +08001318 *
Hannu Lounentof36be3c2018-01-10 20:31:25 +01001319 * hw - Struct containing variables accessed by shared code
1320 * enetaddr - buffering where the MAC address will be stored
Roy Zang28f7a052009-07-31 13:34:02 +08001321 *****************************************************************************/
Hannu Lounentof36be3c2018-01-10 20:31:25 +01001322static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
1323 unsigned char enetaddr[6])
Roy Zang28f7a052009-07-31 13:34:02 +08001324{
Roy Zang28f7a052009-07-31 13:34:02 +08001325 uint16_t offset;
1326 uint16_t eeprom_data;
1327 int i;
1328
Roy Zang28f7a052009-07-31 13:34:02 +08001329 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
wdenk4e112c12003-06-03 23:54:09 +00001330 offset = i >> 1;
Hannu Lounentof36be3c2018-01-10 20:31:25 +01001331 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
wdenk4e112c12003-06-03 23:54:09 +00001332 DEBUGOUT("EEPROM Read Error\n");
1333 return -E1000_ERR_EEPROM;
1334 }
Simon Glassc53abc32015-08-19 09:33:39 -06001335 enetaddr[i] = eeprom_data & 0xff;
1336 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
wdenk4e112c12003-06-03 23:54:09 +00001337 }
Hannu Lounentof36be3c2018-01-10 20:31:25 +01001338
1339 return 0;
1340}
1341
1342/******************************************************************************
1343 * Reads the adapter's MAC address from the RAL/RAH registers
1344 *
1345 * hw - Struct containing variables accessed by shared code
1346 * enetaddr - buffering where the MAC address will be stored
1347 *****************************************************************************/
1348static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
1349 unsigned char enetaddr[6])
1350{
1351 uint16_t offset, tmp;
1352 uint32_t reg_data = 0;
1353 int i;
1354
1355 if (hw->mac_type != e1000_igb)
1356 return -E1000_ERR_MAC_TYPE;
1357
1358 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1359 offset = i >> 1;
1360
1361 if (offset == 0)
1362 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1363 else if (offset == 1)
1364 reg_data >>= 16;
1365 else if (offset == 2)
1366 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1367 tmp = reg_data & 0xffff;
1368
1369 enetaddr[i] = tmp & 0xff;
1370 enetaddr[i + 1] = (tmp >> 8) & 0xff;
1371 }
1372
1373 return 0;
1374}
1375
1376/******************************************************************************
1377 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1378 * second function of dual function devices
1379 *
1380 * hw - Struct containing variables accessed by shared code
1381 * enetaddr - buffering where the MAC address will be stored
1382 *****************************************************************************/
1383static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1384{
1385 int ret_val;
1386
1387 if (hw->mac_type == e1000_igb) {
1388 /* i210 preloads MAC address into RAL/RAH registers */
1389 ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
1390 } else {
1391 ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
1392 }
1393 if (ret_val)
1394 return ret_val;
Kyle Moffett7376f8d2010-09-13 05:52:22 +00001395
1396 /* Invert the last bit if this is the second device */
1397 if (e1000_is_second_port(hw))
Simon Glassc53abc32015-08-19 09:33:39 -06001398 enetaddr[5] ^= 1;
Kyle Moffett7376f8d2010-09-13 05:52:22 +00001399
wdenk4e112c12003-06-03 23:54:09 +00001400 return 0;
1401}
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02001402#endif
wdenk4e112c12003-06-03 23:54:09 +00001403
1404/******************************************************************************
1405 * Initializes receive address filters.
1406 *
wdenk57b2d802003-06-27 21:31:46 +00001407 * hw - Struct containing variables accessed by shared code
wdenk4e112c12003-06-03 23:54:09 +00001408 *
1409 * Places the MAC address in receive address register 0 and clears the rest
1410 * of the receive addresss registers. Clears the multicast table. Assumes
1411 * the receiver is in reset when the routine is called.
1412 *****************************************************************************/
1413static void
Simon Glassc53abc32015-08-19 09:33:39 -06001414e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
wdenk4e112c12003-06-03 23:54:09 +00001415{
wdenk4e112c12003-06-03 23:54:09 +00001416 uint32_t i;
1417 uint32_t addr_low;
1418 uint32_t addr_high;
1419
1420 DEBUGFUNC();
1421
1422 /* Setup the receive address. */
1423 DEBUGOUT("Programming MAC Address into RAR[0]\n");
Simon Glassc53abc32015-08-19 09:33:39 -06001424 addr_low = (enetaddr[0] |
1425 (enetaddr[1] << 8) |
1426 (enetaddr[2] << 16) | (enetaddr[3] << 24));
wdenk4e112c12003-06-03 23:54:09 +00001427
Simon Glassc53abc32015-08-19 09:33:39 -06001428 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
wdenk4e112c12003-06-03 23:54:09 +00001429
1430 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1431 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1432
1433 /* Zero out the other 15 receive addresses. */
1434 DEBUGOUT("Clearing RAR[1-15]\n");
1435 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1436 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1437 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1438 }
1439}
1440
1441/******************************************************************************
1442 * Clears the VLAN filer table
1443 *
1444 * hw - Struct containing variables accessed by shared code
1445 *****************************************************************************/
1446static void
1447e1000_clear_vfta(struct e1000_hw *hw)
1448{
1449 uint32_t offset;
1450
1451 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1452 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1453}
1454
1455/******************************************************************************
1456 * Set the mac type member in the hw struct.
wdenk57b2d802003-06-27 21:31:46 +00001457 *
wdenk4e112c12003-06-03 23:54:09 +00001458 * hw - Struct containing variables accessed by shared code
1459 *****************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +08001460int32_t
wdenk4e112c12003-06-03 23:54:09 +00001461e1000_set_mac_type(struct e1000_hw *hw)
1462{
1463 DEBUGFUNC();
1464
1465 switch (hw->device_id) {
1466 case E1000_DEV_ID_82542:
1467 switch (hw->revision_id) {
1468 case E1000_82542_2_0_REV_ID:
1469 hw->mac_type = e1000_82542_rev2_0;
1470 break;
1471 case E1000_82542_2_1_REV_ID:
1472 hw->mac_type = e1000_82542_rev2_1;
1473 break;
1474 default:
1475 /* Invalid 82542 revision ID */
1476 return -E1000_ERR_MAC_TYPE;
1477 }
1478 break;
1479 case E1000_DEV_ID_82543GC_FIBER:
1480 case E1000_DEV_ID_82543GC_COPPER:
1481 hw->mac_type = e1000_82543;
1482 break;
1483 case E1000_DEV_ID_82544EI_COPPER:
1484 case E1000_DEV_ID_82544EI_FIBER:
1485 case E1000_DEV_ID_82544GC_COPPER:
1486 case E1000_DEV_ID_82544GC_LOM:
1487 hw->mac_type = e1000_82544;
1488 break;
1489 case E1000_DEV_ID_82540EM:
1490 case E1000_DEV_ID_82540EM_LOM:
Roy Zang28f7a052009-07-31 13:34:02 +08001491 case E1000_DEV_ID_82540EP:
1492 case E1000_DEV_ID_82540EP_LOM:
1493 case E1000_DEV_ID_82540EP_LP:
wdenk4e112c12003-06-03 23:54:09 +00001494 hw->mac_type = e1000_82540;
1495 break;
1496 case E1000_DEV_ID_82545EM_COPPER:
1497 case E1000_DEV_ID_82545EM_FIBER:
1498 hw->mac_type = e1000_82545;
1499 break;
Roy Zang28f7a052009-07-31 13:34:02 +08001500 case E1000_DEV_ID_82545GM_COPPER:
1501 case E1000_DEV_ID_82545GM_FIBER:
1502 case E1000_DEV_ID_82545GM_SERDES:
1503 hw->mac_type = e1000_82545_rev_3;
1504 break;
wdenk4e112c12003-06-03 23:54:09 +00001505 case E1000_DEV_ID_82546EB_COPPER:
1506 case E1000_DEV_ID_82546EB_FIBER:
Roy Zang28f7a052009-07-31 13:34:02 +08001507 case E1000_DEV_ID_82546EB_QUAD_COPPER:
wdenk4e112c12003-06-03 23:54:09 +00001508 hw->mac_type = e1000_82546;
1509 break;
Roy Zang28f7a052009-07-31 13:34:02 +08001510 case E1000_DEV_ID_82546GB_COPPER:
1511 case E1000_DEV_ID_82546GB_FIBER:
1512 case E1000_DEV_ID_82546GB_SERDES:
1513 case E1000_DEV_ID_82546GB_PCIE:
1514 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1515 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1516 hw->mac_type = e1000_82546_rev_3;
1517 break;
1518 case E1000_DEV_ID_82541EI:
1519 case E1000_DEV_ID_82541EI_MOBILE:
1520 case E1000_DEV_ID_82541ER_LOM:
1521 hw->mac_type = e1000_82541;
1522 break;
Andre Schwarz68c2a302008-03-06 16:45:44 +01001523 case E1000_DEV_ID_82541ER:
Roy Zang28f7a052009-07-31 13:34:02 +08001524 case E1000_DEV_ID_82541GI:
Wolfgang Grandegger8562c382008-05-28 19:55:19 +02001525 case E1000_DEV_ID_82541GI_LF:
Roy Zang28f7a052009-07-31 13:34:02 +08001526 case E1000_DEV_ID_82541GI_MOBILE:
Wolfgang Denk35f734f2008-04-13 09:59:26 -07001527 hw->mac_type = e1000_82541_rev_2;
1528 break;
Roy Zang28f7a052009-07-31 13:34:02 +08001529 case E1000_DEV_ID_82547EI:
1530 case E1000_DEV_ID_82547EI_MOBILE:
1531 hw->mac_type = e1000_82547;
1532 break;
1533 case E1000_DEV_ID_82547GI:
1534 hw->mac_type = e1000_82547_rev_2;
1535 break;
1536 case E1000_DEV_ID_82571EB_COPPER:
1537 case E1000_DEV_ID_82571EB_FIBER:
1538 case E1000_DEV_ID_82571EB_SERDES:
1539 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1540 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1541 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1542 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1543 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1544 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1545 hw->mac_type = e1000_82571;
1546 break;
1547 case E1000_DEV_ID_82572EI_COPPER:
1548 case E1000_DEV_ID_82572EI_FIBER:
1549 case E1000_DEV_ID_82572EI_SERDES:
1550 case E1000_DEV_ID_82572EI:
1551 hw->mac_type = e1000_82572;
1552 break;
1553 case E1000_DEV_ID_82573E:
1554 case E1000_DEV_ID_82573E_IAMT:
1555 case E1000_DEV_ID_82573L:
1556 hw->mac_type = e1000_82573;
1557 break;
Roy Zang181119b2011-01-21 11:29:38 +08001558 case E1000_DEV_ID_82574L:
1559 hw->mac_type = e1000_82574;
1560 break;
Roy Zang28f7a052009-07-31 13:34:02 +08001561 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1562 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1563 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1564 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1565 hw->mac_type = e1000_80003es2lan;
1566 break;
1567 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1568 case E1000_DEV_ID_ICH8_IGP_AMT:
1569 case E1000_DEV_ID_ICH8_IGP_C:
1570 case E1000_DEV_ID_ICH8_IFE:
1571 case E1000_DEV_ID_ICH8_IFE_GT:
1572 case E1000_DEV_ID_ICH8_IFE_G:
1573 case E1000_DEV_ID_ICH8_IGP_M:
1574 hw->mac_type = e1000_ich8lan;
1575 break;
Marjolaine Amate0cef7802024-06-24 19:15:32 +00001576 case PCI_DEVICE_ID_INTEL_I226_K:
1577 case PCI_DEVICE_ID_INTEL_I226_LMVP:
1578 case PCI_DEVICE_ID_INTEL_I226_LM:
1579 case PCI_DEVICE_ID_INTEL_I226_V:
1580 case PCI_DEVICE_ID_INTEL_I226_IT:
1581 case PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED:
Marcel Ziswilerb9f66232014-09-08 00:03:50 +02001582 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1583 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
Marek Vasut74a13c22014-08-08 07:41:39 -07001584 case PCI_DEVICE_ID_INTEL_I210_COPPER:
Marcel Ziswilerb9f66232014-09-08 00:03:50 +02001585 case PCI_DEVICE_ID_INTEL_I211_COPPER:
Marek Vasut74a13c22014-08-08 07:41:39 -07001586 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1587 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1588 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1589 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
Marjolaine Amatee4913352024-03-04 16:23:38 +01001590 case PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED:
1591 case PCI_DEVICE_ID_INTEL_I225_IT:
ZhiJie.zhang87e00132025-04-21 17:08:26 +08001592 case PCI_DEVICE_ID_INTEL_I225_V:
Marek Vasut74a13c22014-08-08 07:41:39 -07001593 hw->mac_type = e1000_igb;
1594 break;
wdenk4e112c12003-06-03 23:54:09 +00001595 default:
1596 /* Should never have loaded on this device */
1597 return -E1000_ERR_MAC_TYPE;
1598 }
1599 return E1000_SUCCESS;
1600}
1601
1602/******************************************************************************
1603 * Reset the transmit and receive units; mask and clear all interrupts.
1604 *
1605 * hw - Struct containing variables accessed by shared code
1606 *****************************************************************************/
1607void
1608e1000_reset_hw(struct e1000_hw *hw)
1609{
1610 uint32_t ctrl;
1611 uint32_t ctrl_ext;
wdenk4e112c12003-06-03 23:54:09 +00001612 uint32_t manc;
Roy Zang966172e2009-08-22 03:49:52 +08001613 uint32_t pba = 0;
Marek Vasut74a13c22014-08-08 07:41:39 -07001614 uint32_t reg;
wdenk4e112c12003-06-03 23:54:09 +00001615
1616 DEBUGFUNC();
1617
Roy Zang966172e2009-08-22 03:49:52 +08001618 /* get the correct pba value for both PCI and PCIe*/
1619 if (hw->mac_type < e1000_82571)
1620 pba = E1000_DEFAULT_PCI_PBA;
1621 else
1622 pba = E1000_DEFAULT_PCIE_PBA;
1623
wdenk4e112c12003-06-03 23:54:09 +00001624 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1625 if (hw->mac_type == e1000_82542_rev2_0) {
1626 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
Bin Meng83cf24c2016-02-02 05:58:01 -08001627 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1628 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
wdenk4e112c12003-06-03 23:54:09 +00001629 }
1630
1631 /* Clear interrupt mask to stop board from generating interrupts */
1632 DEBUGOUT("Masking off all interrupts\n");
Marek Vasut74a13c22014-08-08 07:41:39 -07001633 if (hw->mac_type == e1000_igb)
1634 E1000_WRITE_REG(hw, I210_IAM, 0);
wdenk4e112c12003-06-03 23:54:09 +00001635 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1636
1637 /* Disable the Transmit and Receive units. Then delay to allow
1638 * any pending transactions to complete before we hit the MAC with
1639 * the global reset.
1640 */
1641 E1000_WRITE_REG(hw, RCTL, 0);
1642 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1643 E1000_WRITE_FLUSH(hw);
1644
Christian Gmeiner7c7b3c92020-10-06 16:08:35 +02001645 if (hw->mac_type == e1000_igb) {
1646 E1000_WRITE_REG(hw, RXPBS, I210_RXPBSIZE_DEFAULT);
1647 E1000_WRITE_REG(hw, TXPBS, I210_TXPBSIZE_DEFAULT);
1648 }
1649
wdenk4e112c12003-06-03 23:54:09 +00001650 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
York Sun4a598092013-04-01 11:29:11 -07001651 hw->tbi_compatibility_on = false;
wdenk4e112c12003-06-03 23:54:09 +00001652
1653 /* Delay to allow any outstanding PCI transactions to complete before
1654 * resetting the device
1655 */
1656 mdelay(10);
1657
1658 /* Issue a global reset to the MAC. This will reset the chip's
1659 * transmit, receive, DMA, and link units. It will not effect
1660 * the current PCI configuration. The global reset bit is self-
1661 * clearing, and should clear within a microsecond.
1662 */
1663 DEBUGOUT("Issuing a global reset to MAC\n");
1664 ctrl = E1000_READ_REG(hw, CTRL);
1665
Roy Zang28f7a052009-07-31 13:34:02 +08001666 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
wdenk4e112c12003-06-03 23:54:09 +00001667
1668 /* Force a reload from the EEPROM if necessary */
Marek Vasut74a13c22014-08-08 07:41:39 -07001669 if (hw->mac_type == e1000_igb) {
1670 mdelay(20);
1671 reg = E1000_READ_REG(hw, STATUS);
1672 if (reg & E1000_STATUS_PF_RST_DONE)
1673 DEBUGOUT("PF OK\n");
1674 reg = E1000_READ_REG(hw, I210_EECD);
1675 if (reg & E1000_EECD_AUTO_RD)
1676 DEBUGOUT("EEC OK\n");
1677 } else if (hw->mac_type < e1000_82540) {
wdenk4e112c12003-06-03 23:54:09 +00001678 /* Wait for reset to complete */
1679 udelay(10);
1680 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1681 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1682 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1683 E1000_WRITE_FLUSH(hw);
1684 /* Wait for EEPROM reload */
1685 mdelay(2);
1686 } else {
1687 /* Wait for EEPROM reload (it happens automatically) */
1688 mdelay(4);
1689 /* Dissable HW ARPs on ASF enabled adapters */
1690 manc = E1000_READ_REG(hw, MANC);
1691 manc &= ~(E1000_MANC_ARP_EN);
1692 E1000_WRITE_REG(hw, MANC, manc);
1693 }
1694
1695 /* Clear interrupt mask to stop board from generating interrupts */
1696 DEBUGOUT("Masking off all interrupts\n");
Marek Vasut74a13c22014-08-08 07:41:39 -07001697 if (hw->mac_type == e1000_igb)
1698 E1000_WRITE_REG(hw, I210_IAM, 0);
wdenk4e112c12003-06-03 23:54:09 +00001699 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1700
1701 /* Clear any pending interrupt events. */
Zang Roy-R61911e36d67c2011-11-06 22:22:36 +00001702 E1000_READ_REG(hw, ICR);
wdenk4e112c12003-06-03 23:54:09 +00001703
1704 /* If MWI was previously enabled, reenable it. */
1705 if (hw->mac_type == e1000_82542_rev2_0) {
Bin Meng83cf24c2016-02-02 05:58:01 -08001706 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
wdenk4e112c12003-06-03 23:54:09 +00001707 }
Marek Vasut74a13c22014-08-08 07:41:39 -07001708 if (hw->mac_type != e1000_igb)
1709 E1000_WRITE_REG(hw, PBA, pba);
Roy Zang28f7a052009-07-31 13:34:02 +08001710}
1711
1712/******************************************************************************
1713 *
1714 * Initialize a number of hardware-dependent bits
1715 *
1716 * hw: Struct containing variables accessed by shared code
1717 *
1718 * This function contains hardware limitation workarounds for PCI-E adapters
1719 *
1720 *****************************************************************************/
1721static void
1722e1000_initialize_hardware_bits(struct e1000_hw *hw)
1723{
1724 if ((hw->mac_type >= e1000_82571) &&
1725 (!hw->initialize_hw_bits_disable)) {
1726 /* Settings common to all PCI-express silicon */
1727 uint32_t reg_ctrl, reg_ctrl_ext;
1728 uint32_t reg_tarc0, reg_tarc1;
1729 uint32_t reg_tctl;
1730 uint32_t reg_txdctl, reg_txdctl1;
1731
1732 /* link autonegotiation/sync workarounds */
1733 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1734 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1735
1736 /* Enable not-done TX descriptor counting */
1737 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1738 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1739 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1740
1741 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1742 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1743 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1744
1745 switch (hw->mac_type) {
Andre Przywara4b307c12016-11-16 00:50:07 +00001746 case e1000_igb: /* IGB is cool */
1747 return;
Roy Zang28f7a052009-07-31 13:34:02 +08001748 case e1000_82571:
1749 case e1000_82572:
1750 /* Clear PHY TX compatible mode bits */
1751 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1752 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1753
1754 /* link autonegotiation/sync workarounds */
1755 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1756
1757 /* TX ring control fixes */
1758 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1759
1760 /* Multiple read bit is reversed polarity */
1761 reg_tctl = E1000_READ_REG(hw, TCTL);
1762 if (reg_tctl & E1000_TCTL_MULR)
1763 reg_tarc1 &= ~(1 << 28);
1764 else
1765 reg_tarc1 |= (1 << 28);
1766
1767 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1768 break;
1769 case e1000_82573:
Roy Zang181119b2011-01-21 11:29:38 +08001770 case e1000_82574:
Roy Zang28f7a052009-07-31 13:34:02 +08001771 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1772 reg_ctrl_ext &= ~(1 << 23);
1773 reg_ctrl_ext |= (1 << 22);
1774
1775 /* TX byte count fix */
1776 reg_ctrl = E1000_READ_REG(hw, CTRL);
1777 reg_ctrl &= ~(1 << 29);
1778
1779 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1780 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1781 break;
1782 case e1000_80003es2lan:
1783 /* improve small packet performace for fiber/serdes */
1784 if ((hw->media_type == e1000_media_type_fiber)
1785 || (hw->media_type ==
1786 e1000_media_type_internal_serdes)) {
1787 reg_tarc0 &= ~(1 << 20);
1788 }
1789
1790 /* Multiple read bit is reversed polarity */
1791 reg_tctl = E1000_READ_REG(hw, TCTL);
1792 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1793 if (reg_tctl & E1000_TCTL_MULR)
1794 reg_tarc1 &= ~(1 << 28);
1795 else
1796 reg_tarc1 |= (1 << 28);
1797
1798 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1799 break;
1800 case e1000_ich8lan:
1801 /* Reduce concurrent DMA requests to 3 from 4 */
1802 if ((hw->revision_id < 3) ||
1803 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1804 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1805 reg_tarc0 |= ((1 << 29)|(1 << 28));
1806
1807 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1808 reg_ctrl_ext |= (1 << 22);
1809 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1810
1811 /* workaround TX hang with TSO=on */
1812 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1813
1814 /* Multiple read bit is reversed polarity */
1815 reg_tctl = E1000_READ_REG(hw, TCTL);
1816 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1817 if (reg_tctl & E1000_TCTL_MULR)
1818 reg_tarc1 &= ~(1 << 28);
1819 else
1820 reg_tarc1 |= (1 << 28);
1821
1822 /* workaround TX hang with TSO=on */
1823 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1824
1825 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1826 break;
1827 default:
1828 break;
1829 }
1830
1831 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1832 }
wdenk4e112c12003-06-03 23:54:09 +00001833}
1834
1835/******************************************************************************
1836 * Performs basic configuration of the adapter.
1837 *
1838 * hw - Struct containing variables accessed by shared code
wdenk57b2d802003-06-27 21:31:46 +00001839 *
1840 * Assumes that the controller has previously been reset and is in a
wdenk4e112c12003-06-03 23:54:09 +00001841 * post-reset uninitialized state. Initializes the receive address registers,
1842 * multicast table, and VLAN filter table. Calls routines to setup link
1843 * configuration and flow control settings. Clears all on-chip counters. Leaves
1844 * the transmit and receive units disabled and uninitialized.
1845 *****************************************************************************/
1846static int
Simon Glassc53abc32015-08-19 09:33:39 -06001847e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
wdenk4e112c12003-06-03 23:54:09 +00001848{
Roy Zang28f7a052009-07-31 13:34:02 +08001849 uint32_t ctrl;
wdenk4e112c12003-06-03 23:54:09 +00001850 uint32_t i;
1851 int32_t ret_val;
1852 uint16_t pcix_cmd_word;
1853 uint16_t pcix_stat_hi_word;
1854 uint16_t cmd_mmrbc;
1855 uint16_t stat_mmrbc;
Roy Zang28f7a052009-07-31 13:34:02 +08001856 uint32_t mta_size;
1857 uint32_t reg_data;
1858 uint32_t ctrl_ext;
wdenk4e112c12003-06-03 23:54:09 +00001859 DEBUGFUNC();
Roy Zang28f7a052009-07-31 13:34:02 +08001860 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1861 if ((hw->mac_type == e1000_ich8lan) &&
1862 ((hw->revision_id < 3) ||
1863 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1864 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1865 reg_data = E1000_READ_REG(hw, STATUS);
1866 reg_data &= ~0x80000000;
1867 E1000_WRITE_REG(hw, STATUS, reg_data);
wdenk4e112c12003-06-03 23:54:09 +00001868 }
Roy Zang28f7a052009-07-31 13:34:02 +08001869 /* Do not need initialize Identification LED */
wdenk4e112c12003-06-03 23:54:09 +00001870
Roy Zang28f7a052009-07-31 13:34:02 +08001871 /* Set the media type and TBI compatibility */
1872 e1000_set_media_type(hw);
1873
1874 /* Must be called after e1000_set_media_type
1875 * because media_type is used */
1876 e1000_initialize_hardware_bits(hw);
wdenk4e112c12003-06-03 23:54:09 +00001877
1878 /* Disabling VLAN filtering. */
1879 DEBUGOUT("Initializing the IEEE VLAN\n");
Roy Zang28f7a052009-07-31 13:34:02 +08001880 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1881 if (hw->mac_type != e1000_ich8lan) {
1882 if (hw->mac_type < e1000_82545_rev_3)
1883 E1000_WRITE_REG(hw, VET, 0);
1884 e1000_clear_vfta(hw);
1885 }
wdenk4e112c12003-06-03 23:54:09 +00001886
1887 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1888 if (hw->mac_type == e1000_82542_rev2_0) {
1889 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
Bin Meng83cf24c2016-02-02 05:58:01 -08001890 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1891 hw->
1892 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
wdenk4e112c12003-06-03 23:54:09 +00001893 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1894 E1000_WRITE_FLUSH(hw);
1895 mdelay(5);
1896 }
1897
1898 /* Setup the receive address. This involves initializing all of the Receive
1899 * Address Registers (RARs 0 - 15).
1900 */
Simon Glassc53abc32015-08-19 09:33:39 -06001901 e1000_init_rx_addrs(hw, enetaddr);
wdenk4e112c12003-06-03 23:54:09 +00001902
1903 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1904 if (hw->mac_type == e1000_82542_rev2_0) {
1905 E1000_WRITE_REG(hw, RCTL, 0);
1906 E1000_WRITE_FLUSH(hw);
1907 mdelay(1);
Bin Meng83cf24c2016-02-02 05:58:01 -08001908 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
wdenk4e112c12003-06-03 23:54:09 +00001909 }
1910
1911 /* Zero out the Multicast HASH table */
1912 DEBUGOUT("Zeroing the MTA\n");
Roy Zang28f7a052009-07-31 13:34:02 +08001913 mta_size = E1000_MC_TBL_SIZE;
1914 if (hw->mac_type == e1000_ich8lan)
1915 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1916 for (i = 0; i < mta_size; i++) {
wdenk4e112c12003-06-03 23:54:09 +00001917 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
Roy Zang28f7a052009-07-31 13:34:02 +08001918 /* use write flush to prevent Memory Write Block (MWB) from
1919 * occuring when accessing our register space */
1920 E1000_WRITE_FLUSH(hw);
1921 }
Bin Meng1ba7e952015-11-16 01:19:16 -08001922
Roy Zang28f7a052009-07-31 13:34:02 +08001923 switch (hw->mac_type) {
1924 case e1000_82545_rev_3:
1925 case e1000_82546_rev_3:
Marek Vasut74a13c22014-08-08 07:41:39 -07001926 case e1000_igb:
Roy Zang28f7a052009-07-31 13:34:02 +08001927 break;
1928 default:
wdenk4e112c12003-06-03 23:54:09 +00001929 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
Roy Zang28f7a052009-07-31 13:34:02 +08001930 if (hw->bus_type == e1000_bus_type_pcix) {
Bin Meng83cf24c2016-02-02 05:58:01 -08001931 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1932 &pcix_cmd_word);
1933 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
1934 &pcix_stat_hi_word);
wdenk4e112c12003-06-03 23:54:09 +00001935 cmd_mmrbc =
1936 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1937 PCIX_COMMAND_MMRBC_SHIFT;
1938 stat_mmrbc =
1939 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1940 PCIX_STATUS_HI_MMRBC_SHIFT;
1941 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1942 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1943 if (cmd_mmrbc > stat_mmrbc) {
1944 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1945 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
Bin Meng83cf24c2016-02-02 05:58:01 -08001946 dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1947 pcix_cmd_word);
wdenk4e112c12003-06-03 23:54:09 +00001948 }
1949 }
Roy Zang28f7a052009-07-31 13:34:02 +08001950 break;
1951 }
wdenk4e112c12003-06-03 23:54:09 +00001952
Roy Zang28f7a052009-07-31 13:34:02 +08001953 /* More time needed for PHY to initialize */
1954 if (hw->mac_type == e1000_ich8lan)
1955 mdelay(15);
Marek Vasut74a13c22014-08-08 07:41:39 -07001956 if (hw->mac_type == e1000_igb)
1957 mdelay(15);
Roy Zang28f7a052009-07-31 13:34:02 +08001958
wdenk4e112c12003-06-03 23:54:09 +00001959 /* Call a subroutine to configure the link and setup flow control. */
Simon Glassc53abc32015-08-19 09:33:39 -06001960 ret_val = e1000_setup_link(hw);
wdenk4e112c12003-06-03 23:54:09 +00001961
1962 /* Set the transmit descriptor write-back policy */
1963 if (hw->mac_type > e1000_82544) {
1964 ctrl = E1000_READ_REG(hw, TXDCTL);
1965 ctrl =
1966 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1967 E1000_TXDCTL_FULL_TX_DESC_WB;
1968 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1969 }
Roy Zang28f7a052009-07-31 13:34:02 +08001970
Ruchika Guptaed1f72f2012-04-19 02:27:11 +00001971 /* Set the receive descriptor write back policy */
Ruchika Guptaed1f72f2012-04-19 02:27:11 +00001972 if (hw->mac_type >= e1000_82571) {
1973 ctrl = E1000_READ_REG(hw, RXDCTL);
1974 ctrl =
1975 (ctrl & ~E1000_RXDCTL_WTHRESH) |
1976 E1000_RXDCTL_FULL_RX_DESC_WB;
1977 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1978 }
1979
Roy Zang28f7a052009-07-31 13:34:02 +08001980 switch (hw->mac_type) {
1981 default:
1982 break;
1983 case e1000_80003es2lan:
1984 /* Enable retransmit on late collisions */
1985 reg_data = E1000_READ_REG(hw, TCTL);
1986 reg_data |= E1000_TCTL_RTLC;
1987 E1000_WRITE_REG(hw, TCTL, reg_data);
1988
1989 /* Configure Gigabit Carry Extend Padding */
1990 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1991 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1992 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1993 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1994
1995 /* Configure Transmit Inter-Packet Gap */
1996 reg_data = E1000_READ_REG(hw, TIPG);
1997 reg_data &= ~E1000_TIPG_IPGT_MASK;
1998 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1999 E1000_WRITE_REG(hw, TIPG, reg_data);
2000
2001 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
2002 reg_data &= ~0x00100000;
2003 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
2004 /* Fall through */
2005 case e1000_82571:
2006 case e1000_82572:
2007 case e1000_ich8lan:
2008 ctrl = E1000_READ_REG(hw, TXDCTL1);
2009 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
2010 | E1000_TXDCTL_FULL_TX_DESC_WB;
2011 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
2012 break;
Roy Zang181119b2011-01-21 11:29:38 +08002013 case e1000_82573:
2014 case e1000_82574:
2015 reg_data = E1000_READ_REG(hw, GCR);
2016 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
2017 E1000_WRITE_REG(hw, GCR, reg_data);
Marek Vasut74a13c22014-08-08 07:41:39 -07002018 case e1000_igb:
2019 break;
Roy Zang28f7a052009-07-31 13:34:02 +08002020 }
2021
Roy Zang28f7a052009-07-31 13:34:02 +08002022 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
2023 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
2024 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2025 /* Relaxed ordering must be disabled to avoid a parity
2026 * error crash in a PCI slot. */
2027 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2028 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2029 }
2030
2031 return ret_val;
2032}
wdenk4e112c12003-06-03 23:54:09 +00002033
2034/******************************************************************************
2035 * Configures flow control and link settings.
wdenk57b2d802003-06-27 21:31:46 +00002036 *
wdenk4e112c12003-06-03 23:54:09 +00002037 * hw - Struct containing variables accessed by shared code
wdenk57b2d802003-06-27 21:31:46 +00002038 *
wdenk4e112c12003-06-03 23:54:09 +00002039 * Determines which flow control settings to use. Calls the apropriate media-
2040 * specific link configuration function. Configures the flow control settings.
2041 * Assuming the adapter has a valid link partner, a valid link should be
wdenk57b2d802003-06-27 21:31:46 +00002042 * established. Assumes the hardware has previously been reset and the
wdenk4e112c12003-06-03 23:54:09 +00002043 * transmitter and receiver are not enabled.
2044 *****************************************************************************/
2045static int
Simon Glassc53abc32015-08-19 09:33:39 -06002046e1000_setup_link(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +00002047{
wdenk4e112c12003-06-03 23:54:09 +00002048 int32_t ret_val;
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02002049#ifndef CONFIG_E1000_NO_NVM
2050 uint32_t ctrl_ext;
wdenk4e112c12003-06-03 23:54:09 +00002051 uint16_t eeprom_data;
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02002052#endif
wdenk4e112c12003-06-03 23:54:09 +00002053
2054 DEBUGFUNC();
2055
Roy Zang28f7a052009-07-31 13:34:02 +08002056 /* In the case of the phy reset being blocked, we already have a link.
2057 * We do not have to set it up again. */
2058 if (e1000_check_phy_reset_block(hw))
2059 return E1000_SUCCESS;
2060
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02002061#ifndef CONFIG_E1000_NO_NVM
wdenk4e112c12003-06-03 23:54:09 +00002062 /* Read and store word 0x0F of the EEPROM. This word contains bits
2063 * that determine the hardware's default PAUSE (flow control) mode,
2064 * a bit that determines whether the HW defaults to enabling or
2065 * disabling auto-negotiation, and the direction of the
2066 * SW defined pins. If there is no SW over-ride of the flow
2067 * control setting, then the variable hw->fc will
2068 * be initialized based on a value in the EEPROM.
2069 */
Roy Zang28f7a052009-07-31 13:34:02 +08002070 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
2071 &eeprom_data) < 0) {
wdenk4e112c12003-06-03 23:54:09 +00002072 DEBUGOUT("EEPROM Read Error\n");
2073 return -E1000_ERR_EEPROM;
2074 }
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02002075#endif
wdenk4e112c12003-06-03 23:54:09 +00002076 if (hw->fc == e1000_fc_default) {
Roy Zang28f7a052009-07-31 13:34:02 +08002077 switch (hw->mac_type) {
2078 case e1000_ich8lan:
2079 case e1000_82573:
Roy Zang181119b2011-01-21 11:29:38 +08002080 case e1000_82574:
Marek Vasut74a13c22014-08-08 07:41:39 -07002081 case e1000_igb:
wdenk4e112c12003-06-03 23:54:09 +00002082 hw->fc = e1000_fc_full;
Roy Zang28f7a052009-07-31 13:34:02 +08002083 break;
2084 default:
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02002085#ifndef CONFIG_E1000_NO_NVM
Roy Zang28f7a052009-07-31 13:34:02 +08002086 ret_val = e1000_read_eeprom(hw,
2087 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
2088 if (ret_val) {
2089 DEBUGOUT("EEPROM Read Error\n");
2090 return -E1000_ERR_EEPROM;
2091 }
Roy Zang28f7a052009-07-31 13:34:02 +08002092 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
2093 hw->fc = e1000_fc_none;
2094 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
2095 EEPROM_WORD0F_ASM_DIR)
2096 hw->fc = e1000_fc_tx_pause;
2097 else
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02002098#endif
Roy Zang28f7a052009-07-31 13:34:02 +08002099 hw->fc = e1000_fc_full;
2100 break;
2101 }
wdenk4e112c12003-06-03 23:54:09 +00002102 }
2103
2104 /* We want to save off the original Flow Control configuration just
2105 * in case we get disconnected and then reconnected into a different
2106 * hub or switch with different Flow Control capabilities.
2107 */
2108 if (hw->mac_type == e1000_82542_rev2_0)
2109 hw->fc &= (~e1000_fc_tx_pause);
2110
2111 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
2112 hw->fc &= (~e1000_fc_rx_pause);
2113
2114 hw->original_fc = hw->fc;
2115
2116 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
2117
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02002118#ifndef CONFIG_E1000_NO_NVM
wdenk4e112c12003-06-03 23:54:09 +00002119 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
2120 * polarity value for the SW controlled pins, and setup the
2121 * Extended Device Control reg with that info.
2122 * This is needed because one of the SW controlled pins is used for
2123 * signal detection. So this should be done before e1000_setup_pcs_link()
2124 * or e1000_phy_setup() is called.
2125 */
2126 if (hw->mac_type == e1000_82543) {
2127 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
2128 SWDPIO__EXT_SHIFT);
2129 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2130 }
Rojhalat Ibrahimbbcd2b02013-10-07 18:30:39 +02002131#endif
wdenk4e112c12003-06-03 23:54:09 +00002132
2133 /* Call the necessary subroutine to configure the link. */
2134 ret_val = (hw->media_type == e1000_media_type_fiber) ?
Simon Glassc53abc32015-08-19 09:33:39 -06002135 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
wdenk4e112c12003-06-03 23:54:09 +00002136 if (ret_val < 0) {
2137 return ret_val;
2138 }
2139
2140 /* Initialize the flow control address, type, and PAUSE timer
2141 * registers to their default values. This is done even if flow
2142 * control is disabled, because it does not hurt anything to
2143 * initialize these registers.
2144 */
Roy Zang28f7a052009-07-31 13:34:02 +08002145 DEBUGOUT("Initializing the Flow Control address, type"
2146 "and timer regs\n");
2147
2148 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
2149 if (hw->mac_type != e1000_ich8lan) {
2150 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
2151 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
2152 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
2153 }
wdenk4e112c12003-06-03 23:54:09 +00002154
wdenk4e112c12003-06-03 23:54:09 +00002155 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
2156
2157 /* Set the flow control receive threshold registers. Normally,
2158 * these registers will be set to a default threshold that may be
2159 * adjusted later by the driver's runtime code. However, if the
2160 * ability to transmit pause frames in not enabled, then these
wdenk57b2d802003-06-27 21:31:46 +00002161 * registers will be set to 0.
wdenk4e112c12003-06-03 23:54:09 +00002162 */
2163 if (!(hw->fc & e1000_fc_tx_pause)) {
2164 E1000_WRITE_REG(hw, FCRTL, 0);
2165 E1000_WRITE_REG(hw, FCRTH, 0);
2166 } else {
2167 /* We need to set up the Receive Threshold high and low water marks
2168 * as well as (optionally) enabling the transmission of XON frames.
2169 */
2170 if (hw->fc_send_xon) {
2171 E1000_WRITE_REG(hw, FCRTL,
2172 (hw->fc_low_water | E1000_FCRTL_XONE));
2173 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2174 } else {
2175 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2176 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2177 }
2178 }
2179 return ret_val;
2180}
2181
2182/******************************************************************************
2183 * Sets up link for a fiber based adapter
2184 *
2185 * hw - Struct containing variables accessed by shared code
2186 *
2187 * Manipulates Physical Coding Sublayer functions in order to configure
2188 * link. Assumes the hardware has been previously reset and the transmitter
2189 * and receiver are not enabled.
2190 *****************************************************************************/
2191static int
Simon Glassc53abc32015-08-19 09:33:39 -06002192e1000_setup_fiber_link(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +00002193{
wdenk4e112c12003-06-03 23:54:09 +00002194 uint32_t ctrl;
2195 uint32_t status;
2196 uint32_t txcw = 0;
2197 uint32_t i;
2198 uint32_t signal;
2199 int32_t ret_val;
2200
2201 DEBUGFUNC();
wdenk57b2d802003-06-27 21:31:46 +00002202 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2203 * set when the optics detect a signal. On older adapters, it will be
wdenk4e112c12003-06-03 23:54:09 +00002204 * cleared when there is a signal
2205 */
2206 ctrl = E1000_READ_REG(hw, CTRL);
2207 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2208 signal = E1000_CTRL_SWDPIN1;
2209 else
2210 signal = 0;
2211
Simon Glassc53abc32015-08-19 09:33:39 -06002212 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
wdenk4e112c12003-06-03 23:54:09 +00002213 ctrl);
2214 /* Take the link out of reset */
2215 ctrl &= ~(E1000_CTRL_LRST);
2216
2217 e1000_config_collision_dist(hw);
2218
2219 /* Check for a software override of the flow control settings, and setup
2220 * the device accordingly. If auto-negotiation is enabled, then software
2221 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2222 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
wdenk57b2d802003-06-27 21:31:46 +00002223 * auto-negotiation is disabled, then software will have to manually
wdenk4e112c12003-06-03 23:54:09 +00002224 * configure the two flow control enable bits in the CTRL register.
2225 *
2226 * The possible values of the "fc" parameter are:
Wolfgang Denk35f734f2008-04-13 09:59:26 -07002227 * 0: Flow control is completely disabled
2228 * 1: Rx flow control is enabled (we can receive pause frames, but
2229 * not send pause frames).
2230 * 2: Tx flow control is enabled (we can send pause frames but we do
2231 * not support receiving pause frames).
2232 * 3: Both Rx and TX flow control (symmetric) are enabled.
wdenk4e112c12003-06-03 23:54:09 +00002233 */
2234 switch (hw->fc) {
2235 case e1000_fc_none:
2236 /* Flow control is completely disabled by a software over-ride. */
2237 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2238 break;
2239 case e1000_fc_rx_pause:
wdenk57b2d802003-06-27 21:31:46 +00002240 /* RX Flow control is enabled and TX Flow control is disabled by a
2241 * software over-ride. Since there really isn't a way to advertise
wdenk4e112c12003-06-03 23:54:09 +00002242 * that we are capable of RX Pause ONLY, we will advertise that we
2243 * support both symmetric and asymmetric RX PAUSE. Later, we will
2244 * disable the adapter's ability to send PAUSE frames.
2245 */
2246 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2247 break;
2248 case e1000_fc_tx_pause:
wdenk57b2d802003-06-27 21:31:46 +00002249 /* TX Flow control is enabled, and RX Flow control is disabled, by a
wdenk4e112c12003-06-03 23:54:09 +00002250 * software over-ride.
2251 */
2252 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2253 break;
2254 case e1000_fc_full:
2255 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2256 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2257 break;
2258 default:
2259 DEBUGOUT("Flow control param set incorrectly\n");
2260 return -E1000_ERR_CONFIG;
2261 break;
2262 }
2263
2264 /* Since auto-negotiation is enabled, take the link out of reset (the link
2265 * will be in reset, because we previously reset the chip). This will
2266 * restart auto-negotiation. If auto-neogtiation is successful then the
2267 * link-up status bit will be set and the flow control enable bits (RFCE
2268 * and TFCE) will be set according to their negotiated value.
2269 */
2270 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2271
2272 E1000_WRITE_REG(hw, TXCW, txcw);
2273 E1000_WRITE_REG(hw, CTRL, ctrl);
2274 E1000_WRITE_FLUSH(hw);
2275
2276 hw->txcw = txcw;
2277 mdelay(1);
2278
2279 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
wdenk57b2d802003-06-27 21:31:46 +00002280 * indication in the Device Status Register. Time-out if a link isn't
2281 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
wdenk4e112c12003-06-03 23:54:09 +00002282 * less than 500 milliseconds even if the other end is doing it in SW).
2283 */
2284 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2285 DEBUGOUT("Looking for Link\n");
2286 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2287 mdelay(10);
2288 status = E1000_READ_REG(hw, STATUS);
2289 if (status & E1000_STATUS_LU)
2290 break;
2291 }
2292 if (i == (LINK_UP_TIMEOUT / 10)) {
wdenk57b2d802003-06-27 21:31:46 +00002293 /* AutoNeg failed to achieve a link, so we'll call
wdenk4e112c12003-06-03 23:54:09 +00002294 * e1000_check_for_link. This routine will force the link up if we
2295 * detect a signal. This will allow us to communicate with
2296 * non-autonegotiating link partners.
2297 */
2298 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2299 hw->autoneg_failed = 1;
Simon Glassc53abc32015-08-19 09:33:39 -06002300 ret_val = e1000_check_for_link(hw);
wdenk4e112c12003-06-03 23:54:09 +00002301 if (ret_val < 0) {
2302 DEBUGOUT("Error while checking for link\n");
2303 return ret_val;
2304 }
2305 hw->autoneg_failed = 0;
2306 } else {
2307 hw->autoneg_failed = 0;
2308 DEBUGOUT("Valid Link Found\n");
2309 }
2310 } else {
2311 DEBUGOUT("No Signal Detected\n");
2312 return -E1000_ERR_NOLINK;
2313 }
2314 return 0;
2315}
2316
2317/******************************************************************************
Roy Zang28f7a052009-07-31 13:34:02 +08002318* Make sure we have a valid PHY and change PHY mode before link setup.
wdenk4e112c12003-06-03 23:54:09 +00002319*
2320* hw - Struct containing variables accessed by shared code
2321******************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +08002322static int32_t
2323e1000_copper_link_preconfig(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +00002324{
wdenk4e112c12003-06-03 23:54:09 +00002325 uint32_t ctrl;
2326 int32_t ret_val;
wdenk4e112c12003-06-03 23:54:09 +00002327 uint16_t phy_data;
2328
2329 DEBUGFUNC();
2330
2331 ctrl = E1000_READ_REG(hw, CTRL);
2332 /* With 82543, we need to force speed and duplex on the MAC equal to what
2333 * the PHY speed and duplex configuration is. In addition, we need to
2334 * perform a hardware reset on the PHY to take it out of reset.
2335 */
2336 if (hw->mac_type > e1000_82543) {
2337 ctrl |= E1000_CTRL_SLU;
2338 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2339 E1000_WRITE_REG(hw, CTRL, ctrl);
2340 } else {
Roy Zang28f7a052009-07-31 13:34:02 +08002341 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2342 | E1000_CTRL_SLU);
wdenk4e112c12003-06-03 23:54:09 +00002343 E1000_WRITE_REG(hw, CTRL, ctrl);
Roy Zang28f7a052009-07-31 13:34:02 +08002344 ret_val = e1000_phy_hw_reset(hw);
2345 if (ret_val)
2346 return ret_val;
wdenk4e112c12003-06-03 23:54:09 +00002347 }
2348
2349 /* Make sure we have a valid PHY */
2350 ret_val = e1000_detect_gig_phy(hw);
Roy Zang28f7a052009-07-31 13:34:02 +08002351 if (ret_val) {
wdenk4e112c12003-06-03 23:54:09 +00002352 DEBUGOUT("Error, did not detect valid phy.\n");
2353 return ret_val;
2354 }
Minghuan Lian674bcd52015-03-19 09:43:51 -07002355 DEBUGOUT("Phy ID = %x\n", hw->phy_id);
wdenk4e112c12003-06-03 23:54:09 +00002356
Roy Zang28f7a052009-07-31 13:34:02 +08002357 /* Set PHY to class A mode (if necessary) */
2358 ret_val = e1000_set_phy_mode(hw);
2359 if (ret_val)
2360 return ret_val;
Roy Zang28f7a052009-07-31 13:34:02 +08002361 if ((hw->mac_type == e1000_82545_rev_3) ||
2362 (hw->mac_type == e1000_82546_rev_3)) {
2363 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2364 &phy_data);
2365 phy_data |= 0x00000008;
2366 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2367 phy_data);
2368 }
2369
2370 if (hw->mac_type <= e1000_82543 ||
2371 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2372 hw->mac_type == e1000_82541_rev_2
2373 || hw->mac_type == e1000_82547_rev_2)
York Sun4a598092013-04-01 11:29:11 -07002374 hw->phy_reset_disable = false;
Roy Zang28f7a052009-07-31 13:34:02 +08002375
2376 return E1000_SUCCESS;
2377}
2378
2379/*****************************************************************************
2380 *
2381 * This function sets the lplu state according to the active flag. When
2382 * activating lplu this function also disables smart speed and vise versa.
2383 * lplu will not be activated unless the device autonegotiation advertisment
2384 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2385 * hw: Struct containing variables accessed by shared code
2386 * active - true to enable lplu false to disable lplu.
2387 *
2388 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2389 * E1000_SUCCESS at any other case.
2390 *
2391 ****************************************************************************/
2392
2393static int32_t
York Sun4a598092013-04-01 11:29:11 -07002394e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
Roy Zang28f7a052009-07-31 13:34:02 +08002395{
2396 uint32_t phy_ctrl = 0;
2397 int32_t ret_val;
2398 uint16_t phy_data;
2399 DEBUGFUNC();
2400
2401 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2402 && hw->phy_type != e1000_phy_igp_3)
2403 return E1000_SUCCESS;
2404
2405 /* During driver activity LPLU should not be used or it will attain link
2406 * from the lowest speeds starting from 10Mbps. The capability is used
2407 * for Dx transitions and states */
2408 if (hw->mac_type == e1000_82541_rev_2
2409 || hw->mac_type == e1000_82547_rev_2) {
2410 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2411 &phy_data);
2412 if (ret_val)
2413 return ret_val;
2414 } else if (hw->mac_type == e1000_ich8lan) {
2415 /* MAC writes into PHY register based on the state transition
2416 * and start auto-negotiation. SW driver can overwrite the
2417 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2418 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2419 } else {
2420 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2421 &phy_data);
2422 if (ret_val)
2423 return ret_val;
2424 }
2425
2426 if (!active) {
2427 if (hw->mac_type == e1000_82541_rev_2 ||
2428 hw->mac_type == e1000_82547_rev_2) {
2429 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2430 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2431 phy_data);
2432 if (ret_val)
2433 return ret_val;
2434 } else {
2435 if (hw->mac_type == e1000_ich8lan) {
2436 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2437 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2438 } else {
2439 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2440 ret_val = e1000_write_phy_reg(hw,
2441 IGP02E1000_PHY_POWER_MGMT, phy_data);
2442 if (ret_val)
2443 return ret_val;
2444 }
2445 }
2446
2447 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2448 * Dx states where the power conservation is most important. During
2449 * driver activity we should enable SmartSpeed, so performance is
2450 * maintained. */
2451 if (hw->smart_speed == e1000_smart_speed_on) {
2452 ret_val = e1000_read_phy_reg(hw,
2453 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2454 if (ret_val)
2455 return ret_val;
2456
2457 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2458 ret_val = e1000_write_phy_reg(hw,
2459 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2460 if (ret_val)
2461 return ret_val;
2462 } else if (hw->smart_speed == e1000_smart_speed_off) {
2463 ret_val = e1000_read_phy_reg(hw,
2464 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2465 if (ret_val)
2466 return ret_val;
2467
2468 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2469 ret_val = e1000_write_phy_reg(hw,
2470 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2471 if (ret_val)
2472 return ret_val;
2473 }
2474
2475 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2476 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2477 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2478
2479 if (hw->mac_type == e1000_82541_rev_2 ||
2480 hw->mac_type == e1000_82547_rev_2) {
2481 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2482 ret_val = e1000_write_phy_reg(hw,
2483 IGP01E1000_GMII_FIFO, phy_data);
2484 if (ret_val)
2485 return ret_val;
2486 } else {
2487 if (hw->mac_type == e1000_ich8lan) {
2488 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2489 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2490 } else {
2491 phy_data |= IGP02E1000_PM_D3_LPLU;
2492 ret_val = e1000_write_phy_reg(hw,
2493 IGP02E1000_PHY_POWER_MGMT, phy_data);
2494 if (ret_val)
2495 return ret_val;
2496 }
2497 }
2498
2499 /* When LPLU is enabled we should disable SmartSpeed */
2500 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2501 &phy_data);
2502 if (ret_val)
2503 return ret_val;
2504
2505 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2506 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2507 phy_data);
2508 if (ret_val)
2509 return ret_val;
2510 }
2511 return E1000_SUCCESS;
2512}
2513
2514/*****************************************************************************
2515 *
2516 * This function sets the lplu d0 state according to the active flag. When
2517 * activating lplu this function also disables smart speed and vise versa.
2518 * lplu will not be activated unless the device autonegotiation advertisment
2519 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2520 * hw: Struct containing variables accessed by shared code
2521 * active - true to enable lplu false to disable lplu.
2522 *
2523 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2524 * E1000_SUCCESS at any other case.
2525 *
2526 ****************************************************************************/
2527
2528static int32_t
York Sun4a598092013-04-01 11:29:11 -07002529e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
Roy Zang28f7a052009-07-31 13:34:02 +08002530{
2531 uint32_t phy_ctrl = 0;
2532 int32_t ret_val;
2533 uint16_t phy_data;
2534 DEBUGFUNC();
2535
2536 if (hw->mac_type <= e1000_82547_rev_2)
2537 return E1000_SUCCESS;
2538
2539 if (hw->mac_type == e1000_ich8lan) {
2540 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
Marek Vasut74a13c22014-08-08 07:41:39 -07002541 } else if (hw->mac_type == e1000_igb) {
2542 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
Roy Zang28f7a052009-07-31 13:34:02 +08002543 } else {
2544 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2545 &phy_data);
2546 if (ret_val)
2547 return ret_val;
2548 }
2549
2550 if (!active) {
2551 if (hw->mac_type == e1000_ich8lan) {
2552 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2553 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
Marek Vasut74a13c22014-08-08 07:41:39 -07002554 } else if (hw->mac_type == e1000_igb) {
2555 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2556 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
Roy Zang28f7a052009-07-31 13:34:02 +08002557 } else {
2558 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2559 ret_val = e1000_write_phy_reg(hw,
2560 IGP02E1000_PHY_POWER_MGMT, phy_data);
2561 if (ret_val)
2562 return ret_val;
2563 }
2564
Marek Vasut74a13c22014-08-08 07:41:39 -07002565 if (hw->mac_type == e1000_igb)
2566 return E1000_SUCCESS;
2567
Roy Zang28f7a052009-07-31 13:34:02 +08002568 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2569 * Dx states where the power conservation is most important. During
2570 * driver activity we should enable SmartSpeed, so performance is
2571 * maintained. */
2572 if (hw->smart_speed == e1000_smart_speed_on) {
2573 ret_val = e1000_read_phy_reg(hw,
2574 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2575 if (ret_val)
2576 return ret_val;
2577
2578 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2579 ret_val = e1000_write_phy_reg(hw,
2580 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2581 if (ret_val)
2582 return ret_val;
2583 } else if (hw->smart_speed == e1000_smart_speed_off) {
2584 ret_val = e1000_read_phy_reg(hw,
2585 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2586 if (ret_val)
2587 return ret_val;
2588
2589 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2590 ret_val = e1000_write_phy_reg(hw,
2591 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2592 if (ret_val)
2593 return ret_val;
2594 }
2595
Roy Zang28f7a052009-07-31 13:34:02 +08002596 } else {
2597
2598 if (hw->mac_type == e1000_ich8lan) {
2599 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2600 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
Marek Vasut74a13c22014-08-08 07:41:39 -07002601 } else if (hw->mac_type == e1000_igb) {
2602 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2603 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
Roy Zang28f7a052009-07-31 13:34:02 +08002604 } else {
2605 phy_data |= IGP02E1000_PM_D0_LPLU;
2606 ret_val = e1000_write_phy_reg(hw,
2607 IGP02E1000_PHY_POWER_MGMT, phy_data);
2608 if (ret_val)
2609 return ret_val;
2610 }
2611
Marek Vasut74a13c22014-08-08 07:41:39 -07002612 if (hw->mac_type == e1000_igb)
2613 return E1000_SUCCESS;
2614
Roy Zang28f7a052009-07-31 13:34:02 +08002615 /* When LPLU is enabled we should disable SmartSpeed */
2616 ret_val = e1000_read_phy_reg(hw,
2617 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2618 if (ret_val)
2619 return ret_val;
2620
2621 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2622 ret_val = e1000_write_phy_reg(hw,
2623 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2624 if (ret_val)
2625 return ret_val;
2626
2627 }
2628 return E1000_SUCCESS;
2629}
2630
2631/********************************************************************
2632* Copper link setup for e1000_phy_igp series.
2633*
2634* hw - Struct containing variables accessed by shared code
2635*********************************************************************/
2636static int32_t
2637e1000_copper_link_igp_setup(struct e1000_hw *hw)
2638{
2639 uint32_t led_ctrl;
2640 int32_t ret_val;
2641 uint16_t phy_data;
2642
Timur Tabiedc45b52009-08-17 15:55:38 -05002643 DEBUGFUNC();
Roy Zang28f7a052009-07-31 13:34:02 +08002644
2645 if (hw->phy_reset_disable)
2646 return E1000_SUCCESS;
2647
2648 ret_val = e1000_phy_reset(hw);
2649 if (ret_val) {
2650 DEBUGOUT("Error Resetting the PHY\n");
2651 return ret_val;
wdenk4e112c12003-06-03 23:54:09 +00002652 }
Roy Zang28f7a052009-07-31 13:34:02 +08002653
2654 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2655 mdelay(15);
2656 if (hw->mac_type != e1000_ich8lan) {
2657 /* Configure activity LED after PHY reset */
2658 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2659 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2660 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2661 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2662 }
2663
2664 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2665 if (hw->phy_type == e1000_phy_igp) {
2666 /* disable lplu d3 during driver init */
York Sun4a598092013-04-01 11:29:11 -07002667 ret_val = e1000_set_d3_lplu_state(hw, false);
Roy Zang28f7a052009-07-31 13:34:02 +08002668 if (ret_val) {
2669 DEBUGOUT("Error Disabling LPLU D3\n");
2670 return ret_val;
2671 }
2672 }
2673
2674 /* disable lplu d0 during driver init */
York Sun4a598092013-04-01 11:29:11 -07002675 ret_val = e1000_set_d0_lplu_state(hw, false);
Roy Zang28f7a052009-07-31 13:34:02 +08002676 if (ret_val) {
2677 DEBUGOUT("Error Disabling LPLU D0\n");
2678 return ret_val;
2679 }
2680 /* Configure mdi-mdix settings */
2681 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2682 if (ret_val)
2683 return ret_val;
2684
2685 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2686 hw->dsp_config_state = e1000_dsp_config_disabled;
2687 /* Force MDI for earlier revs of the IGP PHY */
2688 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2689 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2690 hw->mdix = 1;
2691
2692 } else {
2693 hw->dsp_config_state = e1000_dsp_config_enabled;
2694 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2695
2696 switch (hw->mdix) {
2697 case 1:
2698 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2699 break;
2700 case 2:
2701 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2702 break;
2703 case 0:
2704 default:
2705 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2706 break;
2707 }
2708 }
2709 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2710 if (ret_val)
2711 return ret_val;
2712
2713 /* set auto-master slave resolution settings */
2714 if (hw->autoneg) {
2715 e1000_ms_type phy_ms_setting = hw->master_slave;
2716
2717 if (hw->ffe_config_state == e1000_ffe_config_active)
2718 hw->ffe_config_state = e1000_ffe_config_enabled;
2719
2720 if (hw->dsp_config_state == e1000_dsp_config_activated)
2721 hw->dsp_config_state = e1000_dsp_config_enabled;
2722
2723 /* when autonegotiation advertisment is only 1000Mbps then we
2724 * should disable SmartSpeed and enable Auto MasterSlave
2725 * resolution as hardware default. */
2726 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2727 /* Disable SmartSpeed */
2728 ret_val = e1000_read_phy_reg(hw,
2729 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2730 if (ret_val)
2731 return ret_val;
2732 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2733 ret_val = e1000_write_phy_reg(hw,
2734 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2735 if (ret_val)
2736 return ret_val;
2737 /* Set auto Master/Slave resolution process */
2738 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2739 &phy_data);
2740 if (ret_val)
2741 return ret_val;
2742 phy_data &= ~CR_1000T_MS_ENABLE;
2743 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2744 phy_data);
2745 if (ret_val)
2746 return ret_val;
2747 }
2748
2749 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2750 if (ret_val)
2751 return ret_val;
2752
2753 /* load defaults for future use */
2754 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2755 ((phy_data & CR_1000T_MS_VALUE) ?
2756 e1000_ms_force_master :
2757 e1000_ms_force_slave) :
2758 e1000_ms_auto;
2759
2760 switch (phy_ms_setting) {
2761 case e1000_ms_force_master:
2762 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2763 break;
2764 case e1000_ms_force_slave:
2765 phy_data |= CR_1000T_MS_ENABLE;
2766 phy_data &= ~(CR_1000T_MS_VALUE);
2767 break;
2768 case e1000_ms_auto:
2769 phy_data &= ~CR_1000T_MS_ENABLE;
2770 default:
2771 break;
2772 }
2773 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2774 if (ret_val)
2775 return ret_val;
2776 }
2777
2778 return E1000_SUCCESS;
2779}
2780
2781/*****************************************************************************
2782 * This function checks the mode of the firmware.
2783 *
York Sun4a598092013-04-01 11:29:11 -07002784 * returns - true when the mode is IAMT or false.
Roy Zang28f7a052009-07-31 13:34:02 +08002785 ****************************************************************************/
York Sun4a598092013-04-01 11:29:11 -07002786bool
Roy Zang28f7a052009-07-31 13:34:02 +08002787e1000_check_mng_mode(struct e1000_hw *hw)
2788{
2789 uint32_t fwsm;
2790 DEBUGFUNC();
2791
2792 fwsm = E1000_READ_REG(hw, FWSM);
2793
2794 if (hw->mac_type == e1000_ich8lan) {
2795 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2796 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
York Sun4a598092013-04-01 11:29:11 -07002797 return true;
Roy Zang28f7a052009-07-31 13:34:02 +08002798 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2799 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
York Sun4a598092013-04-01 11:29:11 -07002800 return true;
Roy Zang28f7a052009-07-31 13:34:02 +08002801
York Sun4a598092013-04-01 11:29:11 -07002802 return false;
Roy Zang28f7a052009-07-31 13:34:02 +08002803}
2804
2805static int32_t
2806e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2807{
Kyle Moffett7376f8d2010-09-13 05:52:22 +00002808 uint16_t swfw = E1000_SWFW_PHY0_SM;
Roy Zang28f7a052009-07-31 13:34:02 +08002809 uint32_t reg_val;
Roy Zang28f7a052009-07-31 13:34:02 +08002810 DEBUGFUNC();
2811
Kyle Moffett7376f8d2010-09-13 05:52:22 +00002812 if (e1000_is_second_port(hw))
Roy Zang28f7a052009-07-31 13:34:02 +08002813 swfw = E1000_SWFW_PHY1_SM;
Kyle Moffett7376f8d2010-09-13 05:52:22 +00002814
Roy Zang28f7a052009-07-31 13:34:02 +08002815 if (e1000_swfw_sync_acquire(hw, swfw))
2816 return -E1000_ERR_SWFW_SYNC;
2817
2818 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2819 & E1000_KUMCTRLSTA_OFFSET) | data;
2820 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2821 udelay(2);
2822
2823 return E1000_SUCCESS;
2824}
2825
2826static int32_t
2827e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2828{
Kyle Moffett7376f8d2010-09-13 05:52:22 +00002829 uint16_t swfw = E1000_SWFW_PHY0_SM;
Roy Zang28f7a052009-07-31 13:34:02 +08002830 uint32_t reg_val;
Roy Zang28f7a052009-07-31 13:34:02 +08002831 DEBUGFUNC();
2832
Kyle Moffett7376f8d2010-09-13 05:52:22 +00002833 if (e1000_is_second_port(hw))
Roy Zang28f7a052009-07-31 13:34:02 +08002834 swfw = E1000_SWFW_PHY1_SM;
Kyle Moffett7376f8d2010-09-13 05:52:22 +00002835
Marek Vasut74a13c22014-08-08 07:41:39 -07002836 if (e1000_swfw_sync_acquire(hw, swfw)) {
2837 debug("%s[%i]\n", __func__, __LINE__);
Roy Zang28f7a052009-07-31 13:34:02 +08002838 return -E1000_ERR_SWFW_SYNC;
Marek Vasut74a13c22014-08-08 07:41:39 -07002839 }
Roy Zang28f7a052009-07-31 13:34:02 +08002840
2841 /* Write register address */
2842 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2843 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2844 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2845 udelay(2);
2846
2847 /* Read the data returned */
2848 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2849 *data = (uint16_t)reg_val;
2850
2851 return E1000_SUCCESS;
2852}
2853
2854/********************************************************************
2855* Copper link setup for e1000_phy_gg82563 series.
2856*
2857* hw - Struct containing variables accessed by shared code
2858*********************************************************************/
2859static int32_t
2860e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2861{
2862 int32_t ret_val;
2863 uint16_t phy_data;
2864 uint32_t reg_data;
2865
2866 DEBUGFUNC();
2867
2868 if (!hw->phy_reset_disable) {
2869 /* Enable CRS on TX for half-duplex operation. */
2870 ret_val = e1000_read_phy_reg(hw,
2871 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2872 if (ret_val)
2873 return ret_val;
2874
2875 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2876 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2877 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2878
2879 ret_val = e1000_write_phy_reg(hw,
2880 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2881 if (ret_val)
2882 return ret_val;
2883
2884 /* Options:
2885 * MDI/MDI-X = 0 (default)
2886 * 0 - Auto for all speeds
2887 * 1 - MDI mode
2888 * 2 - MDI-X mode
2889 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2890 */
2891 ret_val = e1000_read_phy_reg(hw,
2892 GG82563_PHY_SPEC_CTRL, &phy_data);
2893 if (ret_val)
2894 return ret_val;
2895
2896 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2897
2898 switch (hw->mdix) {
2899 case 1:
2900 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2901 break;
2902 case 2:
2903 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2904 break;
2905 case 0:
2906 default:
2907 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2908 break;
2909 }
2910
2911 /* Options:
2912 * disable_polarity_correction = 0 (default)
2913 * Automatic Correction for Reversed Cable Polarity
2914 * 0 - Disabled
2915 * 1 - Enabled
2916 */
2917 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2918 ret_val = e1000_write_phy_reg(hw,
2919 GG82563_PHY_SPEC_CTRL, phy_data);
2920
2921 if (ret_val)
2922 return ret_val;
2923
2924 /* SW Reset the PHY so all changes take effect */
2925 ret_val = e1000_phy_reset(hw);
2926 if (ret_val) {
2927 DEBUGOUT("Error Resetting the PHY\n");
2928 return ret_val;
2929 }
2930 } /* phy_reset_disable */
2931
2932 if (hw->mac_type == e1000_80003es2lan) {
2933 /* Bypass RX and TX FIFO's */
2934 ret_val = e1000_write_kmrn_reg(hw,
2935 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2936 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2937 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2938 if (ret_val)
2939 return ret_val;
2940
2941 ret_val = e1000_read_phy_reg(hw,
2942 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2943 if (ret_val)
2944 return ret_val;
2945
2946 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2947 ret_val = e1000_write_phy_reg(hw,
2948 GG82563_PHY_SPEC_CTRL_2, phy_data);
2949
2950 if (ret_val)
2951 return ret_val;
2952
2953 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2954 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2955 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2956
2957 ret_val = e1000_read_phy_reg(hw,
2958 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2959 if (ret_val)
2960 return ret_val;
2961
2962 /* Do not init these registers when the HW is in IAMT mode, since the
2963 * firmware will have already initialized them. We only initialize
2964 * them if the HW is not in IAMT mode.
2965 */
York Sun4a598092013-04-01 11:29:11 -07002966 if (e1000_check_mng_mode(hw) == false) {
Roy Zang28f7a052009-07-31 13:34:02 +08002967 /* Enable Electrical Idle on the PHY */
2968 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2969 ret_val = e1000_write_phy_reg(hw,
2970 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2971 if (ret_val)
2972 return ret_val;
2973
2974 ret_val = e1000_read_phy_reg(hw,
2975 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2976 if (ret_val)
2977 return ret_val;
2978
2979 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2980 ret_val = e1000_write_phy_reg(hw,
2981 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2982
2983 if (ret_val)
2984 return ret_val;
2985 }
2986
2987 /* Workaround: Disable padding in Kumeran interface in the MAC
2988 * and in the PHY to avoid CRC errors.
2989 */
2990 ret_val = e1000_read_phy_reg(hw,
2991 GG82563_PHY_INBAND_CTRL, &phy_data);
2992 if (ret_val)
2993 return ret_val;
2994 phy_data |= GG82563_ICR_DIS_PADDING;
2995 ret_val = e1000_write_phy_reg(hw,
2996 GG82563_PHY_INBAND_CTRL, phy_data);
2997 if (ret_val)
2998 return ret_val;
2999 }
3000 return E1000_SUCCESS;
3001}
3002
3003/********************************************************************
3004* Copper link setup for e1000_phy_m88 series.
3005*
3006* hw - Struct containing variables accessed by shared code
3007*********************************************************************/
3008static int32_t
3009e1000_copper_link_mgp_setup(struct e1000_hw *hw)
3010{
3011 int32_t ret_val;
3012 uint16_t phy_data;
3013
3014 DEBUGFUNC();
3015
3016 if (hw->phy_reset_disable)
3017 return E1000_SUCCESS;
3018
3019 /* Enable CRS on TX. This must be set for half-duplex operation. */
3020 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3021 if (ret_val)
3022 return ret_val;
3023
wdenk4e112c12003-06-03 23:54:09 +00003024 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3025
wdenk4e112c12003-06-03 23:54:09 +00003026 /* Options:
3027 * MDI/MDI-X = 0 (default)
3028 * 0 - Auto for all speeds
3029 * 1 - MDI mode
3030 * 2 - MDI-X mode
3031 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
3032 */
3033 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
Roy Zang28f7a052009-07-31 13:34:02 +08003034
wdenk4e112c12003-06-03 23:54:09 +00003035 switch (hw->mdix) {
3036 case 1:
3037 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
3038 break;
3039 case 2:
3040 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
3041 break;
3042 case 3:
3043 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
3044 break;
3045 case 0:
3046 default:
3047 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
3048 break;
3049 }
wdenk4e112c12003-06-03 23:54:09 +00003050
wdenk4e112c12003-06-03 23:54:09 +00003051 /* Options:
3052 * disable_polarity_correction = 0 (default)
Roy Zang28f7a052009-07-31 13:34:02 +08003053 * Automatic Correction for Reversed Cable Polarity
wdenk4e112c12003-06-03 23:54:09 +00003054 * 0 - Disabled
3055 * 1 - Enabled
3056 */
3057 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
Roy Zang28f7a052009-07-31 13:34:02 +08003058 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
3059 if (ret_val)
3060 return ret_val;
wdenk4e112c12003-06-03 23:54:09 +00003061
Roy Zang28f7a052009-07-31 13:34:02 +08003062 if (hw->phy_revision < M88E1011_I_REV_4) {
3063 /* Force TX_CLK in the Extended PHY Specific Control Register
3064 * to 25MHz clock.
3065 */
3066 ret_val = e1000_read_phy_reg(hw,
3067 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
3068 if (ret_val)
3069 return ret_val;
3070
3071 phy_data |= M88E1000_EPSCR_TX_CLK_25;
3072
3073 if ((hw->phy_revision == E1000_REVISION_2) &&
3074 (hw->phy_id == M88E1111_I_PHY_ID)) {
3075 /* Vidalia Phy, set the downshift counter to 5x */
3076 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
3077 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
3078 ret_val = e1000_write_phy_reg(hw,
3079 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3080 if (ret_val)
3081 return ret_val;
3082 } else {
3083 /* Configure Master and Slave downshift values */
3084 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
3085 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
3086 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
3087 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
3088 ret_val = e1000_write_phy_reg(hw,
3089 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3090 if (ret_val)
3091 return ret_val;
3092 }
wdenk4e112c12003-06-03 23:54:09 +00003093 }
3094
3095 /* SW Reset the PHY so all changes take effect */
3096 ret_val = e1000_phy_reset(hw);
Roy Zang28f7a052009-07-31 13:34:02 +08003097 if (ret_val) {
wdenk4e112c12003-06-03 23:54:09 +00003098 DEBUGOUT("Error Resetting the PHY\n");
3099 return ret_val;
3100 }
3101
Roy Zang28f7a052009-07-31 13:34:02 +08003102 return E1000_SUCCESS;
3103}
wdenk4e112c12003-06-03 23:54:09 +00003104
Roy Zang28f7a052009-07-31 13:34:02 +08003105/********************************************************************
3106* Setup auto-negotiation and flow control advertisements,
3107* and then perform auto-negotiation.
3108*
3109* hw - Struct containing variables accessed by shared code
3110*********************************************************************/
3111static int32_t
3112e1000_copper_link_autoneg(struct e1000_hw *hw)
3113{
3114 int32_t ret_val;
3115 uint16_t phy_data;
3116
3117 DEBUGFUNC();
3118
wdenk4e112c12003-06-03 23:54:09 +00003119 /* Perform some bounds checking on the hw->autoneg_advertised
3120 * parameter. If this variable is zero, then set it to the default.
3121 */
3122 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
3123
3124 /* If autoneg_advertised is zero, we assume it was not defaulted
3125 * by the calling code so we set to advertise full capability.
3126 */
3127 if (hw->autoneg_advertised == 0)
3128 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
3129
Roy Zang28f7a052009-07-31 13:34:02 +08003130 /* IFE phy only supports 10/100 */
3131 if (hw->phy_type == e1000_phy_ife)
3132 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
3133
wdenk4e112c12003-06-03 23:54:09 +00003134 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3135 ret_val = e1000_phy_setup_autoneg(hw);
Roy Zang28f7a052009-07-31 13:34:02 +08003136 if (ret_val) {
wdenk4e112c12003-06-03 23:54:09 +00003137 DEBUGOUT("Error Setting up Auto-Negotiation\n");
3138 return ret_val;
3139 }
3140 DEBUGOUT("Restarting Auto-Neg\n");
3141
3142 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
3143 * the Auto Neg Restart bit in the PHY control register.
3144 */
Roy Zang28f7a052009-07-31 13:34:02 +08003145 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3146 if (ret_val)
3147 return ret_val;
3148
wdenk4e112c12003-06-03 23:54:09 +00003149 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
Roy Zang28f7a052009-07-31 13:34:02 +08003150 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3151 if (ret_val)
3152 return ret_val;
3153
wdenk4e112c12003-06-03 23:54:09 +00003154 /* Does the user want to wait for Auto-Neg to complete here, or
3155 * check at a later time (for example, callback routine).
3156 */
Roy Zang28f7a052009-07-31 13:34:02 +08003157 /* If we do not wait for autonegtation to complete I
3158 * do not see a valid link status.
3159 * wait_autoneg_complete = 1 .
3160 */
wdenk4e112c12003-06-03 23:54:09 +00003161 if (hw->wait_autoneg_complete) {
3162 ret_val = e1000_wait_autoneg(hw);
Roy Zang28f7a052009-07-31 13:34:02 +08003163 if (ret_val) {
3164 DEBUGOUT("Error while waiting for autoneg"
3165 "to complete\n");
wdenk4e112c12003-06-03 23:54:09 +00003166 return ret_val;
3167 }
3168 }
Roy Zang28f7a052009-07-31 13:34:02 +08003169
York Sun4a598092013-04-01 11:29:11 -07003170 hw->get_link_status = true;
Roy Zang28f7a052009-07-31 13:34:02 +08003171
3172 return E1000_SUCCESS;
3173}
3174
3175/******************************************************************************
3176* Config the MAC and the PHY after link is up.
3177* 1) Set up the MAC to the current PHY speed/duplex
3178* if we are on 82543. If we
3179* are on newer silicon, we only need to configure
3180* collision distance in the Transmit Control Register.
3181* 2) Set up flow control on the MAC to that established with
3182* the link partner.
3183* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3184*
3185* hw - Struct containing variables accessed by shared code
3186******************************************************************************/
3187static int32_t
3188e1000_copper_link_postconfig(struct e1000_hw *hw)
3189{
3190 int32_t ret_val;
3191 DEBUGFUNC();
3192
3193 if (hw->mac_type >= e1000_82544) {
3194 e1000_config_collision_dist(hw);
3195 } else {
3196 ret_val = e1000_config_mac_to_phy(hw);
3197 if (ret_val) {
3198 DEBUGOUT("Error configuring MAC to PHY settings\n");
3199 return ret_val;
3200 }
3201 }
3202 ret_val = e1000_config_fc_after_link_up(hw);
3203 if (ret_val) {
3204 DEBUGOUT("Error Configuring Flow Control\n");
wdenk4e112c12003-06-03 23:54:09 +00003205 return ret_val;
3206 }
Roy Zang28f7a052009-07-31 13:34:02 +08003207 return E1000_SUCCESS;
3208}
3209
3210/******************************************************************************
3211* Detects which PHY is present and setup the speed and duplex
3212*
3213* hw - Struct containing variables accessed by shared code
3214******************************************************************************/
3215static int
Simon Glassc53abc32015-08-19 09:33:39 -06003216e1000_setup_copper_link(struct e1000_hw *hw)
Roy Zang28f7a052009-07-31 13:34:02 +08003217{
Roy Zang28f7a052009-07-31 13:34:02 +08003218 int32_t ret_val;
3219 uint16_t i;
3220 uint16_t phy_data;
3221 uint16_t reg_data;
3222
3223 DEBUGFUNC();
3224
3225 switch (hw->mac_type) {
3226 case e1000_80003es2lan:
3227 case e1000_ich8lan:
3228 /* Set the mac to wait the maximum time between each
3229 * iteration and increase the max iterations when
3230 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3231 ret_val = e1000_write_kmrn_reg(hw,
3232 GG82563_REG(0x34, 4), 0xFFFF);
3233 if (ret_val)
3234 return ret_val;
3235 ret_val = e1000_read_kmrn_reg(hw,
3236 GG82563_REG(0x34, 9), &reg_data);
3237 if (ret_val)
3238 return ret_val;
3239 reg_data |= 0x3F;
3240 ret_val = e1000_write_kmrn_reg(hw,
3241 GG82563_REG(0x34, 9), reg_data);
3242 if (ret_val)
3243 return ret_val;
3244 default:
3245 break;
3246 }
3247
3248 /* Check if it is a valid PHY and set PHY mode if necessary. */
3249 ret_val = e1000_copper_link_preconfig(hw);
3250 if (ret_val)
3251 return ret_val;
3252 switch (hw->mac_type) {
3253 case e1000_80003es2lan:
3254 /* Kumeran registers are written-only */
3255 reg_data =
3256 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3257 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3258 ret_val = e1000_write_kmrn_reg(hw,
3259 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3260 if (ret_val)
3261 return ret_val;
3262 break;
3263 default:
3264 break;
3265 }
3266
3267 if (hw->phy_type == e1000_phy_igp ||
3268 hw->phy_type == e1000_phy_igp_3 ||
3269 hw->phy_type == e1000_phy_igp_2) {
3270 ret_val = e1000_copper_link_igp_setup(hw);
3271 if (ret_val)
3272 return ret_val;
Marek Vasut74a13c22014-08-08 07:41:39 -07003273 } else if (hw->phy_type == e1000_phy_m88 ||
Marjolaine Amatee4913352024-03-04 16:23:38 +01003274 hw->phy_type == e1000_phy_igb ||
3275 hw->phy_type == e1000_phy_igc) {
Roy Zang28f7a052009-07-31 13:34:02 +08003276 ret_val = e1000_copper_link_mgp_setup(hw);
3277 if (ret_val)
3278 return ret_val;
3279 } else if (hw->phy_type == e1000_phy_gg82563) {
3280 ret_val = e1000_copper_link_ggp_setup(hw);
3281 if (ret_val)
3282 return ret_val;
3283 }
3284
3285 /* always auto */
3286 /* Setup autoneg and flow control advertisement
3287 * and perform autonegotiation */
3288 ret_val = e1000_copper_link_autoneg(hw);
3289 if (ret_val)
3290 return ret_val;
wdenk4e112c12003-06-03 23:54:09 +00003291
3292 /* Check link status. Wait up to 100 microseconds for link to become
3293 * valid.
3294 */
3295 for (i = 0; i < 10; i++) {
Roy Zang28f7a052009-07-31 13:34:02 +08003296 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3297 if (ret_val)
3298 return ret_val;
3299 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3300 if (ret_val)
3301 return ret_val;
3302
wdenk4e112c12003-06-03 23:54:09 +00003303 if (phy_data & MII_SR_LINK_STATUS) {
Roy Zang28f7a052009-07-31 13:34:02 +08003304 /* Config the MAC and PHY after link is up */
3305 ret_val = e1000_copper_link_postconfig(hw);
3306 if (ret_val)
wdenk4e112c12003-06-03 23:54:09 +00003307 return ret_val;
Roy Zang28f7a052009-07-31 13:34:02 +08003308
wdenk4e112c12003-06-03 23:54:09 +00003309 DEBUGOUT("Valid link established!!!\n");
Roy Zang28f7a052009-07-31 13:34:02 +08003310 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +00003311 }
3312 udelay(10);
3313 }
3314
3315 DEBUGOUT("Unable to establish link!!!\n");
Roy Zang28f7a052009-07-31 13:34:02 +08003316 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +00003317}
3318
3319/******************************************************************************
3320* Configures PHY autoneg and flow control advertisement settings
3321*
3322* hw - Struct containing variables accessed by shared code
3323******************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +08003324int32_t
wdenk4e112c12003-06-03 23:54:09 +00003325e1000_phy_setup_autoneg(struct e1000_hw *hw)
3326{
Roy Zang28f7a052009-07-31 13:34:02 +08003327 int32_t ret_val;
wdenk4e112c12003-06-03 23:54:09 +00003328 uint16_t mii_autoneg_adv_reg;
3329 uint16_t mii_1000t_ctrl_reg;
3330
3331 DEBUGFUNC();
3332
3333 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
Roy Zang28f7a052009-07-31 13:34:02 +08003334 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3335 if (ret_val)
3336 return ret_val;
wdenk4e112c12003-06-03 23:54:09 +00003337
Roy Zang28f7a052009-07-31 13:34:02 +08003338 if (hw->phy_type != e1000_phy_ife) {
3339 /* Read the MII 1000Base-T Control Register (Address 9). */
3340 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3341 &mii_1000t_ctrl_reg);
3342 if (ret_val)
3343 return ret_val;
3344 } else
3345 mii_1000t_ctrl_reg = 0;
wdenk4e112c12003-06-03 23:54:09 +00003346
3347 /* Need to parse both autoneg_advertised and fc and set up
3348 * the appropriate PHY registers. First we will parse for
3349 * autoneg_advertised software override. Since we can advertise
3350 * a plethora of combinations, we need to check each bit
3351 * individually.
3352 */
3353
3354 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3355 * Advertisement Register (Address 4) and the 1000 mb speed bits in
Roy Zang28f7a052009-07-31 13:34:02 +08003356 * the 1000Base-T Control Register (Address 9).
wdenk4e112c12003-06-03 23:54:09 +00003357 */
3358 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3359 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3360
3361 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3362
3363 /* Do we want to advertise 10 Mb Half Duplex? */
3364 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3365 DEBUGOUT("Advertise 10mb Half duplex\n");
3366 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3367 }
3368
3369 /* Do we want to advertise 10 Mb Full Duplex? */
3370 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3371 DEBUGOUT("Advertise 10mb Full duplex\n");
3372 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3373 }
3374
3375 /* Do we want to advertise 100 Mb Half Duplex? */
3376 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3377 DEBUGOUT("Advertise 100mb Half duplex\n");
3378 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3379 }
3380
3381 /* Do we want to advertise 100 Mb Full Duplex? */
3382 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3383 DEBUGOUT("Advertise 100mb Full duplex\n");
3384 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3385 }
3386
3387 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3388 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3389 DEBUGOUT
3390 ("Advertise 1000mb Half duplex requested, request denied!\n");
3391 }
3392
3393 /* Do we want to advertise 1000 Mb Full Duplex? */
3394 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3395 DEBUGOUT("Advertise 1000mb Full duplex\n");
3396 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3397 }
3398
3399 /* Check for a software override of the flow control settings, and
3400 * setup the PHY advertisement registers accordingly. If
3401 * auto-negotiation is enabled, then software will have to set the
3402 * "PAUSE" bits to the correct value in the Auto-Negotiation
3403 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3404 *
3405 * The possible values of the "fc" parameter are:
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003406 * 0: Flow control is completely disabled
3407 * 1: Rx flow control is enabled (we can receive pause frames
3408 * but not send pause frames).
3409 * 2: Tx flow control is enabled (we can send pause frames
3410 * but we do not support receiving pause frames).
3411 * 3: Both Rx and TX flow control (symmetric) are enabled.
wdenk4e112c12003-06-03 23:54:09 +00003412 * other: No software override. The flow control configuration
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003413 * in the EEPROM is used.
wdenk4e112c12003-06-03 23:54:09 +00003414 */
3415 switch (hw->fc) {
3416 case e1000_fc_none: /* 0 */
3417 /* Flow control (RX & TX) is completely disabled by a
3418 * software over-ride.
3419 */
3420 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3421 break;
3422 case e1000_fc_rx_pause: /* 1 */
3423 /* RX Flow control is enabled, and TX Flow control is
3424 * disabled, by a software over-ride.
3425 */
3426 /* Since there really isn't a way to advertise that we are
3427 * capable of RX Pause ONLY, we will advertise that we
3428 * support both symmetric and asymmetric RX PAUSE. Later
3429 * (in e1000_config_fc_after_link_up) we will disable the
3430 *hw's ability to send PAUSE frames.
3431 */
3432 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3433 break;
3434 case e1000_fc_tx_pause: /* 2 */
3435 /* TX Flow control is enabled, and RX Flow control is
3436 * disabled, by a software over-ride.
3437 */
3438 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3439 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3440 break;
3441 case e1000_fc_full: /* 3 */
3442 /* Flow control (both RX and TX) is enabled by a software
3443 * over-ride.
3444 */
3445 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3446 break;
3447 default:
3448 DEBUGOUT("Flow control param set incorrectly\n");
3449 return -E1000_ERR_CONFIG;
3450 }
3451
Roy Zang28f7a052009-07-31 13:34:02 +08003452 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3453 if (ret_val)
3454 return ret_val;
wdenk4e112c12003-06-03 23:54:09 +00003455
3456 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3457
Roy Zang28f7a052009-07-31 13:34:02 +08003458 if (hw->phy_type != e1000_phy_ife) {
3459 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3460 mii_1000t_ctrl_reg);
3461 if (ret_val)
3462 return ret_val;
wdenk4e112c12003-06-03 23:54:09 +00003463 }
Roy Zang28f7a052009-07-31 13:34:02 +08003464
3465 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +00003466}
3467
3468/******************************************************************************
3469* Sets the collision distance in the Transmit Control register
3470*
3471* hw - Struct containing variables accessed by shared code
3472*
3473* Link should have been established previously. Reads the speed and duplex
3474* information from the Device Status register.
3475******************************************************************************/
3476static void
3477e1000_config_collision_dist(struct e1000_hw *hw)
3478{
Roy Zang28f7a052009-07-31 13:34:02 +08003479 uint32_t tctl, coll_dist;
3480
3481 DEBUGFUNC();
3482
3483 if (hw->mac_type < e1000_82543)
3484 coll_dist = E1000_COLLISION_DISTANCE_82542;
3485 else
3486 coll_dist = E1000_COLLISION_DISTANCE;
wdenk4e112c12003-06-03 23:54:09 +00003487
3488 tctl = E1000_READ_REG(hw, TCTL);
3489
3490 tctl &= ~E1000_TCTL_COLD;
Roy Zang28f7a052009-07-31 13:34:02 +08003491 tctl |= coll_dist << E1000_COLD_SHIFT;
wdenk4e112c12003-06-03 23:54:09 +00003492
3493 E1000_WRITE_REG(hw, TCTL, tctl);
3494 E1000_WRITE_FLUSH(hw);
3495}
3496
3497/******************************************************************************
3498* Sets MAC speed and duplex settings to reflect the those in the PHY
3499*
3500* hw - Struct containing variables accessed by shared code
3501* mii_reg - data to write to the MII control register
3502*
3503* The contents of the PHY register containing the needed information need to
3504* be passed in.
3505******************************************************************************/
3506static int
3507e1000_config_mac_to_phy(struct e1000_hw *hw)
3508{
3509 uint32_t ctrl;
3510 uint16_t phy_data;
3511
3512 DEBUGFUNC();
3513
3514 /* Read the Device Control Register and set the bits to Force Speed
3515 * and Duplex.
3516 */
3517 ctrl = E1000_READ_REG(hw, CTRL);
3518 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
Marek Vasut74a13c22014-08-08 07:41:39 -07003519 ctrl &= ~(E1000_CTRL_ILOS);
3520 ctrl |= (E1000_CTRL_SPD_SEL);
wdenk4e112c12003-06-03 23:54:09 +00003521
3522 /* Set up duplex in the Device Control and Transmit Control
3523 * registers depending on negotiated values.
3524 */
3525 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3526 DEBUGOUT("PHY Read Error\n");
3527 return -E1000_ERR_PHY;
3528 }
3529 if (phy_data & M88E1000_PSSR_DPLX)
3530 ctrl |= E1000_CTRL_FD;
3531 else
3532 ctrl &= ~E1000_CTRL_FD;
3533
3534 e1000_config_collision_dist(hw);
3535
3536 /* Set up speed in the Device Control register depending on
3537 * negotiated values.
3538 */
3539 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3540 ctrl |= E1000_CTRL_SPD_1000;
3541 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3542 ctrl |= E1000_CTRL_SPD_100;
3543 /* Write the configured values back to the Device Control Reg. */
3544 E1000_WRITE_REG(hw, CTRL, ctrl);
3545 return 0;
3546}
3547
3548/******************************************************************************
3549 * Forces the MAC's flow control settings.
wdenk57b2d802003-06-27 21:31:46 +00003550 *
wdenk4e112c12003-06-03 23:54:09 +00003551 * hw - Struct containing variables accessed by shared code
3552 *
3553 * Sets the TFCE and RFCE bits in the device control register to reflect
3554 * the adapter settings. TFCE and RFCE need to be explicitly set by
3555 * software when a Copper PHY is used because autonegotiation is managed
3556 * by the PHY rather than the MAC. Software must also configure these
3557 * bits when link is forced on a fiber connection.
3558 *****************************************************************************/
3559static int
3560e1000_force_mac_fc(struct e1000_hw *hw)
3561{
3562 uint32_t ctrl;
3563
3564 DEBUGFUNC();
3565
3566 /* Get the current configuration of the Device Control Register */
3567 ctrl = E1000_READ_REG(hw, CTRL);
3568
3569 /* Because we didn't get link via the internal auto-negotiation
3570 * mechanism (we either forced link or we got link via PHY
3571 * auto-neg), we have to manually enable/disable transmit an
3572 * receive flow control.
3573 *
3574 * The "Case" statement below enables/disable flow control
3575 * according to the "hw->fc" parameter.
3576 *
3577 * The possible values of the "fc" parameter are:
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003578 * 0: Flow control is completely disabled
3579 * 1: Rx flow control is enabled (we can receive pause
3580 * frames but not send pause frames).
3581 * 2: Tx flow control is enabled (we can send pause frames
3582 * frames but we do not receive pause frames).
3583 * 3: Both Rx and TX flow control (symmetric) is enabled.
wdenk4e112c12003-06-03 23:54:09 +00003584 * other: No other values should be possible at this point.
3585 */
3586
3587 switch (hw->fc) {
3588 case e1000_fc_none:
3589 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3590 break;
3591 case e1000_fc_rx_pause:
3592 ctrl &= (~E1000_CTRL_TFCE);
3593 ctrl |= E1000_CTRL_RFCE;
3594 break;
3595 case e1000_fc_tx_pause:
3596 ctrl &= (~E1000_CTRL_RFCE);
3597 ctrl |= E1000_CTRL_TFCE;
3598 break;
3599 case e1000_fc_full:
3600 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3601 break;
3602 default:
3603 DEBUGOUT("Flow control param set incorrectly\n");
3604 return -E1000_ERR_CONFIG;
3605 }
3606
3607 /* Disable TX Flow Control for 82542 (rev 2.0) */
3608 if (hw->mac_type == e1000_82542_rev2_0)
3609 ctrl &= (~E1000_CTRL_TFCE);
3610
3611 E1000_WRITE_REG(hw, CTRL, ctrl);
3612 return 0;
3613}
3614
3615/******************************************************************************
3616 * Configures flow control settings after link is established
wdenk57b2d802003-06-27 21:31:46 +00003617 *
wdenk4e112c12003-06-03 23:54:09 +00003618 * hw - Struct containing variables accessed by shared code
3619 *
3620 * Should be called immediately after a valid link has been established.
3621 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3622 * and autonegotiation is enabled, the MAC flow control settings will be set
3623 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3624 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3625 *****************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +08003626static int32_t
wdenk4e112c12003-06-03 23:54:09 +00003627e1000_config_fc_after_link_up(struct e1000_hw *hw)
3628{
3629 int32_t ret_val;
3630 uint16_t mii_status_reg;
3631 uint16_t mii_nway_adv_reg;
3632 uint16_t mii_nway_lp_ability_reg;
3633 uint16_t speed;
3634 uint16_t duplex;
3635
3636 DEBUGFUNC();
3637
3638 /* Check for the case where we have fiber media and auto-neg failed
3639 * so we had to force link. In this case, we need to force the
3640 * configuration of the MAC to match the "fc" parameter.
3641 */
Roy Zang28f7a052009-07-31 13:34:02 +08003642 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3643 || ((hw->media_type == e1000_media_type_internal_serdes)
3644 && (hw->autoneg_failed))
3645 || ((hw->media_type == e1000_media_type_copper)
3646 && (!hw->autoneg))) {
wdenk4e112c12003-06-03 23:54:09 +00003647 ret_val = e1000_force_mac_fc(hw);
3648 if (ret_val < 0) {
3649 DEBUGOUT("Error forcing flow control settings\n");
3650 return ret_val;
3651 }
3652 }
3653
3654 /* Check for the case where we have copper media and auto-neg is
3655 * enabled. In this case, we need to check and see if Auto-Neg
3656 * has completed, and if so, how the PHY and link partner has
3657 * flow control configured.
3658 */
3659 if (hw->media_type == e1000_media_type_copper) {
3660 /* Read the MII Status Register and check to see if AutoNeg
3661 * has completed. We read this twice because this reg has
3662 * some "sticky" (latched) bits.
3663 */
3664 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
Minghuan Lian674bcd52015-03-19 09:43:51 -07003665 DEBUGOUT("PHY Read Error\n");
wdenk4e112c12003-06-03 23:54:09 +00003666 return -E1000_ERR_PHY;
3667 }
3668 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
Minghuan Lian674bcd52015-03-19 09:43:51 -07003669 DEBUGOUT("PHY Read Error\n");
wdenk4e112c12003-06-03 23:54:09 +00003670 return -E1000_ERR_PHY;
3671 }
3672
3673 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3674 /* The AutoNeg process has completed, so we now need to
3675 * read both the Auto Negotiation Advertisement Register
3676 * (Address 4) and the Auto_Negotiation Base Page Ability
3677 * Register (Address 5) to determine how flow control was
3678 * negotiated.
3679 */
3680 if (e1000_read_phy_reg
3681 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3682 DEBUGOUT("PHY Read Error\n");
3683 return -E1000_ERR_PHY;
3684 }
3685 if (e1000_read_phy_reg
3686 (hw, PHY_LP_ABILITY,
3687 &mii_nway_lp_ability_reg) < 0) {
3688 DEBUGOUT("PHY Read Error\n");
3689 return -E1000_ERR_PHY;
3690 }
3691
3692 /* Two bits in the Auto Negotiation Advertisement Register
3693 * (Address 4) and two bits in the Auto Negotiation Base
3694 * Page Ability Register (Address 5) determine flow control
3695 * for both the PHY and the link partner. The following
3696 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3697 * 1999, describes these PAUSE resolution bits and how flow
3698 * control is determined based upon these settings.
3699 * NOTE: DC = Don't Care
3700 *
3701 * LOCAL DEVICE | LINK PARTNER
3702 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3703 *-------|---------|-------|---------|--------------------
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003704 * 0 | 0 | DC | DC | e1000_fc_none
3705 * 0 | 1 | 0 | DC | e1000_fc_none
3706 * 0 | 1 | 1 | 0 | e1000_fc_none
3707 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3708 * 1 | 0 | 0 | DC | e1000_fc_none
3709 * 1 | DC | 1 | DC | e1000_fc_full
3710 * 1 | 1 | 0 | 0 | e1000_fc_none
3711 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
wdenk4e112c12003-06-03 23:54:09 +00003712 *
3713 */
3714 /* Are both PAUSE bits set to 1? If so, this implies
3715 * Symmetric Flow Control is enabled at both ends. The
3716 * ASM_DIR bits are irrelevant per the spec.
3717 *
3718 * For Symmetric Flow Control:
3719 *
3720 * LOCAL DEVICE | LINK PARTNER
3721 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3722 *-------|---------|-------|---------|--------------------
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003723 * 1 | DC | 1 | DC | e1000_fc_full
wdenk4e112c12003-06-03 23:54:09 +00003724 *
3725 */
3726 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3727 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3728 /* Now we need to check if the user selected RX ONLY
3729 * of pause frames. In this case, we had to advertise
3730 * FULL flow control because we could not advertise RX
3731 * ONLY. Hence, we must now check to see if we need to
3732 * turn OFF the TRANSMISSION of PAUSE frames.
3733 */
3734 if (hw->original_fc == e1000_fc_full) {
3735 hw->fc = e1000_fc_full;
3736 DEBUGOUT("Flow Control = FULL.\r\n");
3737 } else {
3738 hw->fc = e1000_fc_rx_pause;
3739 DEBUGOUT
3740 ("Flow Control = RX PAUSE frames only.\r\n");
3741 }
3742 }
3743 /* For receiving PAUSE frames ONLY.
3744 *
3745 * LOCAL DEVICE | LINK PARTNER
3746 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3747 *-------|---------|-------|---------|--------------------
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003748 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
wdenk4e112c12003-06-03 23:54:09 +00003749 *
3750 */
3751 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3752 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3753 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3754 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3755 {
3756 hw->fc = e1000_fc_tx_pause;
3757 DEBUGOUT
3758 ("Flow Control = TX PAUSE frames only.\r\n");
3759 }
3760 /* For transmitting PAUSE frames ONLY.
3761 *
3762 * LOCAL DEVICE | LINK PARTNER
3763 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3764 *-------|---------|-------|---------|--------------------
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003765 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
wdenk4e112c12003-06-03 23:54:09 +00003766 *
3767 */
3768 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3769 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3770 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3771 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3772 {
3773 hw->fc = e1000_fc_rx_pause;
3774 DEBUGOUT
3775 ("Flow Control = RX PAUSE frames only.\r\n");
3776 }
3777 /* Per the IEEE spec, at this point flow control should be
3778 * disabled. However, we want to consider that we could
3779 * be connected to a legacy switch that doesn't advertise
3780 * desired flow control, but can be forced on the link
3781 * partner. So if we advertised no flow control, that is
3782 * what we will resolve to. If we advertised some kind of
3783 * receive capability (Rx Pause Only or Full Flow Control)
3784 * and the link partner advertised none, we will configure
3785 * ourselves to enable Rx Flow Control only. We can do
3786 * this safely for two reasons: If the link partner really
3787 * didn't want flow control enabled, and we enable Rx, no
3788 * harm done since we won't be receiving any PAUSE frames
3789 * anyway. If the intent on the link partner was to have
3790 * flow control enabled, then by us enabling RX only, we
3791 * can at least receive pause frames and process them.
3792 * This is a good idea because in most cases, since we are
3793 * predominantly a server NIC, more times than not we will
3794 * be asked to delay transmission of packets than asking
3795 * our link partner to pause transmission of frames.
3796 */
3797 else if (hw->original_fc == e1000_fc_none ||
3798 hw->original_fc == e1000_fc_tx_pause) {
3799 hw->fc = e1000_fc_none;
3800 DEBUGOUT("Flow Control = NONE.\r\n");
3801 } else {
3802 hw->fc = e1000_fc_rx_pause;
3803 DEBUGOUT
3804 ("Flow Control = RX PAUSE frames only.\r\n");
3805 }
3806
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003807 /* Now we need to do one last check... If we auto-
wdenk4e112c12003-06-03 23:54:09 +00003808 * negotiated to HALF DUPLEX, flow control should not be
3809 * enabled per IEEE 802.3 spec.
3810 */
3811 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3812
3813 if (duplex == HALF_DUPLEX)
3814 hw->fc = e1000_fc_none;
3815
3816 /* Now we call a subroutine to actually force the MAC
3817 * controller to use the correct flow control settings.
3818 */
3819 ret_val = e1000_force_mac_fc(hw);
3820 if (ret_val < 0) {
3821 DEBUGOUT
3822 ("Error forcing flow control settings\n");
3823 return ret_val;
3824 }
3825 } else {
3826 DEBUGOUT
3827 ("Copper PHY and Auto Neg has not completed.\r\n");
3828 }
3829 }
Roy Zang28f7a052009-07-31 13:34:02 +08003830 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +00003831}
3832
3833/******************************************************************************
3834 * Checks to see if the link status of the hardware has changed.
3835 *
3836 * hw - Struct containing variables accessed by shared code
3837 *
3838 * Called by any function that needs to check the link status of the adapter.
3839 *****************************************************************************/
3840static int
Simon Glassc53abc32015-08-19 09:33:39 -06003841e1000_check_for_link(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +00003842{
wdenk4e112c12003-06-03 23:54:09 +00003843 uint32_t rxcw;
3844 uint32_t ctrl;
3845 uint32_t status;
3846 uint32_t rctl;
3847 uint32_t signal;
3848 int32_t ret_val;
3849 uint16_t phy_data;
3850 uint16_t lp_capability;
3851
3852 DEBUGFUNC();
3853
wdenk57b2d802003-06-27 21:31:46 +00003854 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3855 * set when the optics detect a signal. On older adapters, it will be
wdenk4e112c12003-06-03 23:54:09 +00003856 * cleared when there is a signal
3857 */
3858 ctrl = E1000_READ_REG(hw, CTRL);
3859 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3860 signal = E1000_CTRL_SWDPIN1;
3861 else
3862 signal = 0;
3863
3864 status = E1000_READ_REG(hw, STATUS);
3865 rxcw = E1000_READ_REG(hw, RXCW);
3866 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3867
3868 /* If we have a copper PHY then we only want to go out to the PHY
3869 * registers to see if Auto-Neg has completed and/or if our link
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003870 * status has changed. The get_link_status flag will be set if we
wdenk4e112c12003-06-03 23:54:09 +00003871 * receive a Link Status Change interrupt or we have Rx Sequence
3872 * Errors.
3873 */
3874 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3875 /* First we want to see if the MII Status Register reports
3876 * link. If so, then we want to get the current speed/duplex
3877 * of the PHY.
3878 * Read the register twice since the link bit is sticky.
3879 */
3880 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3881 DEBUGOUT("PHY Read Error\n");
3882 return -E1000_ERR_PHY;
3883 }
3884 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3885 DEBUGOUT("PHY Read Error\n");
3886 return -E1000_ERR_PHY;
3887 }
3888
3889 if (phy_data & MII_SR_LINK_STATUS) {
York Sun4a598092013-04-01 11:29:11 -07003890 hw->get_link_status = false;
wdenk4e112c12003-06-03 23:54:09 +00003891 } else {
3892 /* No link detected */
3893 return -E1000_ERR_NOLINK;
3894 }
3895
3896 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3897 * have Si on board that is 82544 or newer, Auto
3898 * Speed Detection takes care of MAC speed/duplex
3899 * configuration. So we only need to configure Collision
3900 * Distance in the MAC. Otherwise, we need to force
3901 * speed/duplex on the MAC to the current PHY speed/duplex
3902 * settings.
3903 */
3904 if (hw->mac_type >= e1000_82544)
3905 e1000_config_collision_dist(hw);
3906 else {
3907 ret_val = e1000_config_mac_to_phy(hw);
3908 if (ret_val < 0) {
3909 DEBUGOUT
3910 ("Error configuring MAC to PHY settings\n");
3911 return ret_val;
3912 }
3913 }
3914
wdenk57b2d802003-06-27 21:31:46 +00003915 /* Configure Flow Control now that Auto-Neg has completed. First, we
wdenk4e112c12003-06-03 23:54:09 +00003916 * need to restore the desired flow control settings because we may
3917 * have had to re-autoneg with a different link partner.
3918 */
3919 ret_val = e1000_config_fc_after_link_up(hw);
3920 if (ret_val < 0) {
3921 DEBUGOUT("Error configuring flow control\n");
3922 return ret_val;
3923 }
3924
3925 /* At this point we know that we are on copper and we have
3926 * auto-negotiated link. These are conditions for checking the link
Wolfgang Denk35f734f2008-04-13 09:59:26 -07003927 * parter capability register. We use the link partner capability to
wdenk4e112c12003-06-03 23:54:09 +00003928 * determine if TBI Compatibility needs to be turned on or off. If
3929 * the link partner advertises any speed in addition to Gigabit, then
3930 * we assume that they are GMII-based, and TBI compatibility is not
3931 * needed. If no other speeds are advertised, we assume the link
3932 * partner is TBI-based, and we turn on TBI Compatibility.
3933 */
3934 if (hw->tbi_compatibility_en) {
3935 if (e1000_read_phy_reg
3936 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3937 DEBUGOUT("PHY Read Error\n");
3938 return -E1000_ERR_PHY;
3939 }
3940 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3941 NWAY_LPAR_10T_FD_CAPS |
3942 NWAY_LPAR_100TX_HD_CAPS |
3943 NWAY_LPAR_100TX_FD_CAPS |
3944 NWAY_LPAR_100T4_CAPS)) {
wdenk57b2d802003-06-27 21:31:46 +00003945 /* If our link partner advertises anything in addition to
wdenk4e112c12003-06-03 23:54:09 +00003946 * gigabit, we do not need to enable TBI compatibility.
3947 */
3948 if (hw->tbi_compatibility_on) {
3949 /* If we previously were in the mode, turn it off. */
3950 rctl = E1000_READ_REG(hw, RCTL);
3951 rctl &= ~E1000_RCTL_SBP;
3952 E1000_WRITE_REG(hw, RCTL, rctl);
York Sun4a598092013-04-01 11:29:11 -07003953 hw->tbi_compatibility_on = false;
wdenk4e112c12003-06-03 23:54:09 +00003954 }
3955 } else {
3956 /* If TBI compatibility is was previously off, turn it on. For
3957 * compatibility with a TBI link partner, we will store bad
3958 * packets. Some frames have an additional byte on the end and
3959 * will look like CRC errors to to the hardware.
3960 */
3961 if (!hw->tbi_compatibility_on) {
York Sun4a598092013-04-01 11:29:11 -07003962 hw->tbi_compatibility_on = true;
wdenk4e112c12003-06-03 23:54:09 +00003963 rctl = E1000_READ_REG(hw, RCTL);
3964 rctl |= E1000_RCTL_SBP;
3965 E1000_WRITE_REG(hw, RCTL, rctl);
3966 }
3967 }
3968 }
3969 }
3970 /* If we don't have link (auto-negotiation failed or link partner cannot
3971 * auto-negotiate), the cable is plugged in (we have signal), and our
3972 * link partner is not trying to auto-negotiate with us (we are receiving
3973 * idles or data), we need to force link up. We also need to give
3974 * auto-negotiation time to complete, in case the cable was just plugged
3975 * in. The autoneg_failed flag does this.
3976 */
3977 else if ((hw->media_type == e1000_media_type_fiber) &&
3978 (!(status & E1000_STATUS_LU)) &&
3979 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3980 (!(rxcw & E1000_RXCW_C))) {
3981 if (hw->autoneg_failed == 0) {
3982 hw->autoneg_failed = 1;
3983 return 0;
3984 }
3985 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3986
3987 /* Disable auto-negotiation in the TXCW register */
3988 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3989
3990 /* Force link-up and also force full-duplex. */
3991 ctrl = E1000_READ_REG(hw, CTRL);
3992 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3993 E1000_WRITE_REG(hw, CTRL, ctrl);
3994
3995 /* Configure Flow Control after forcing link up. */
3996 ret_val = e1000_config_fc_after_link_up(hw);
3997 if (ret_val < 0) {
3998 DEBUGOUT("Error configuring flow control\n");
3999 return ret_val;
4000 }
4001 }
4002 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
4003 * auto-negotiation in the TXCW register and disable forced link in the
4004 * Device Control register in an attempt to auto-negotiate with our link
4005 * partner.
4006 */
4007 else if ((hw->media_type == e1000_media_type_fiber) &&
4008 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
4009 DEBUGOUT
4010 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
4011 E1000_WRITE_REG(hw, TXCW, hw->txcw);
4012 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4013 }
4014 return 0;
4015}
4016
4017/******************************************************************************
Roy Zang28f7a052009-07-31 13:34:02 +08004018* Configure the MAC-to-PHY interface for 10/100Mbps
4019*
4020* hw - Struct containing variables accessed by shared code
4021******************************************************************************/
4022static int32_t
4023e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
4024{
4025 int32_t ret_val = E1000_SUCCESS;
4026 uint32_t tipg;
4027 uint16_t reg_data;
4028
4029 DEBUGFUNC();
4030
4031 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
4032 ret_val = e1000_write_kmrn_reg(hw,
4033 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4034 if (ret_val)
4035 return ret_val;
4036
4037 /* Configure Transmit Inter-Packet Gap */
4038 tipg = E1000_READ_REG(hw, TIPG);
4039 tipg &= ~E1000_TIPG_IPGT_MASK;
4040 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
4041 E1000_WRITE_REG(hw, TIPG, tipg);
4042
4043 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4044
4045 if (ret_val)
4046 return ret_val;
4047
4048 if (duplex == HALF_DUPLEX)
4049 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
4050 else
4051 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4052
4053 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4054
4055 return ret_val;
4056}
4057
4058static int32_t
4059e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
4060{
4061 int32_t ret_val = E1000_SUCCESS;
4062 uint16_t reg_data;
4063 uint32_t tipg;
4064
4065 DEBUGFUNC();
4066
4067 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
4068 ret_val = e1000_write_kmrn_reg(hw,
4069 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4070 if (ret_val)
4071 return ret_val;
4072
4073 /* Configure Transmit Inter-Packet Gap */
4074 tipg = E1000_READ_REG(hw, TIPG);
4075 tipg &= ~E1000_TIPG_IPGT_MASK;
4076 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
4077 E1000_WRITE_REG(hw, TIPG, tipg);
4078
4079 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4080
4081 if (ret_val)
4082 return ret_val;
4083
4084 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4085 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4086
4087 return ret_val;
4088}
4089
4090/******************************************************************************
wdenk4e112c12003-06-03 23:54:09 +00004091 * Detects the current speed and duplex settings of the hardware.
4092 *
4093 * hw - Struct containing variables accessed by shared code
4094 * speed - Speed of the connection
4095 * duplex - Duplex setting of the connection
4096 *****************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +08004097static int
4098e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
4099 uint16_t *duplex)
wdenk4e112c12003-06-03 23:54:09 +00004100{
4101 uint32_t status;
Roy Zang28f7a052009-07-31 13:34:02 +08004102 int32_t ret_val;
4103 uint16_t phy_data;
wdenk4e112c12003-06-03 23:54:09 +00004104
4105 DEBUGFUNC();
4106
4107 if (hw->mac_type >= e1000_82543) {
4108 status = E1000_READ_REG(hw, STATUS);
4109 if (status & E1000_STATUS_SPEED_1000) {
4110 *speed = SPEED_1000;
4111 DEBUGOUT("1000 Mbs, ");
4112 } else if (status & E1000_STATUS_SPEED_100) {
4113 *speed = SPEED_100;
4114 DEBUGOUT("100 Mbs, ");
4115 } else {
4116 *speed = SPEED_10;
4117 DEBUGOUT("10 Mbs, ");
4118 }
4119
4120 if (status & E1000_STATUS_FD) {
4121 *duplex = FULL_DUPLEX;
4122 DEBUGOUT("Full Duplex\r\n");
4123 } else {
4124 *duplex = HALF_DUPLEX;
4125 DEBUGOUT(" Half Duplex\r\n");
4126 }
4127 } else {
4128 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
4129 *speed = SPEED_1000;
4130 *duplex = FULL_DUPLEX;
4131 }
Roy Zang28f7a052009-07-31 13:34:02 +08004132
4133 /* IGP01 PHY may advertise full duplex operation after speed downgrade
4134 * even if it is operating at half duplex. Here we set the duplex
4135 * settings to match the duplex in the link partner's capabilities.
4136 */
4137 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
4138 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4139 if (ret_val)
4140 return ret_val;
4141
4142 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4143 *duplex = HALF_DUPLEX;
4144 else {
4145 ret_val = e1000_read_phy_reg(hw,
4146 PHY_LP_ABILITY, &phy_data);
4147 if (ret_val)
4148 return ret_val;
4149 if ((*speed == SPEED_100 &&
4150 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
4151 || (*speed == SPEED_10
4152 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4153 *duplex = HALF_DUPLEX;
4154 }
4155 }
4156
4157 if ((hw->mac_type == e1000_80003es2lan) &&
4158 (hw->media_type == e1000_media_type_copper)) {
4159 if (*speed == SPEED_1000)
4160 ret_val = e1000_configure_kmrn_for_1000(hw);
4161 else
4162 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4163 if (ret_val)
4164 return ret_val;
4165 }
4166 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +00004167}
4168
4169/******************************************************************************
4170* Blocks until autoneg completes or times out (~4.5 seconds)
4171*
4172* hw - Struct containing variables accessed by shared code
4173******************************************************************************/
4174static int
4175e1000_wait_autoneg(struct e1000_hw *hw)
4176{
4177 uint16_t i;
4178 uint16_t phy_data;
4179
4180 DEBUGFUNC();
4181 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4182
Stefan Roese497c7312015-08-11 17:12:44 +02004183 /* We will wait for autoneg to complete or timeout to expire. */
wdenk4e112c12003-06-03 23:54:09 +00004184 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4185 /* Read the MII Status Register and wait for Auto-Neg
4186 * Complete bit to be set.
4187 */
4188 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4189 DEBUGOUT("PHY Read Error\n");
4190 return -E1000_ERR_PHY;
4191 }
4192 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4193 DEBUGOUT("PHY Read Error\n");
4194 return -E1000_ERR_PHY;
4195 }
4196 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4197 DEBUGOUT("Auto-Neg complete.\n");
4198 return 0;
4199 }
4200 mdelay(100);
4201 }
4202 DEBUGOUT("Auto-Neg timedout.\n");
4203 return -E1000_ERR_TIMEOUT;
4204}
4205
4206/******************************************************************************
4207* Raises the Management Data Clock
4208*
4209* hw - Struct containing variables accessed by shared code
4210* ctrl - Device control register's current value
4211******************************************************************************/
4212static void
4213e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4214{
4215 /* Raise the clock input to the Management Data Clock (by setting the MDC
4216 * bit), and then delay 2 microseconds.
4217 */
4218 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4219 E1000_WRITE_FLUSH(hw);
4220 udelay(2);
4221}
4222
4223/******************************************************************************
4224* Lowers the Management Data Clock
4225*
4226* hw - Struct containing variables accessed by shared code
4227* ctrl - Device control register's current value
4228******************************************************************************/
4229static void
4230e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4231{
4232 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4233 * bit), and then delay 2 microseconds.
4234 */
4235 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4236 E1000_WRITE_FLUSH(hw);
4237 udelay(2);
4238}
4239
4240/******************************************************************************
4241* Shifts data bits out to the PHY
4242*
4243* hw - Struct containing variables accessed by shared code
4244* data - Data to send out to the PHY
4245* count - Number of bits to shift out
4246*
4247* Bits are shifted out in MSB to LSB order.
4248******************************************************************************/
4249static void
4250e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4251{
4252 uint32_t ctrl;
4253 uint32_t mask;
4254
4255 /* We need to shift "count" number of bits out to the PHY. So, the value
wdenk57b2d802003-06-27 21:31:46 +00004256 * in the "data" parameter will be shifted out to the PHY one bit at a
wdenk4e112c12003-06-03 23:54:09 +00004257 * time. In order to do this, "data" must be broken down into bits.
4258 */
4259 mask = 0x01;
4260 mask <<= (count - 1);
4261
4262 ctrl = E1000_READ_REG(hw, CTRL);
4263
4264 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4265 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4266
4267 while (mask) {
4268 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4269 * then raising and lowering the Management Data Clock. A "0" is
4270 * shifted out to the PHY by setting the MDIO bit to "0" and then
4271 * raising and lowering the clock.
4272 */
4273 if (data & mask)
4274 ctrl |= E1000_CTRL_MDIO;
4275 else
4276 ctrl &= ~E1000_CTRL_MDIO;
4277
4278 E1000_WRITE_REG(hw, CTRL, ctrl);
4279 E1000_WRITE_FLUSH(hw);
4280
4281 udelay(2);
4282
4283 e1000_raise_mdi_clk(hw, &ctrl);
4284 e1000_lower_mdi_clk(hw, &ctrl);
4285
4286 mask = mask >> 1;
4287 }
4288}
4289
4290/******************************************************************************
4291* Shifts data bits in from the PHY
4292*
4293* hw - Struct containing variables accessed by shared code
4294*
wdenk57b2d802003-06-27 21:31:46 +00004295* Bits are shifted in in MSB to LSB order.
wdenk4e112c12003-06-03 23:54:09 +00004296******************************************************************************/
4297static uint16_t
4298e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4299{
4300 uint32_t ctrl;
4301 uint16_t data = 0;
4302 uint8_t i;
4303
4304 /* In order to read a register from the PHY, we need to shift in a total
4305 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4306 * to avoid contention on the MDIO pin when a read operation is performed.
4307 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4308 * by raising the input to the Management Data Clock (setting the MDC bit),
4309 * and then reading the value of the MDIO bit.
4310 */
4311 ctrl = E1000_READ_REG(hw, CTRL);
4312
4313 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4314 ctrl &= ~E1000_CTRL_MDIO_DIR;
4315 ctrl &= ~E1000_CTRL_MDIO;
4316
4317 E1000_WRITE_REG(hw, CTRL, ctrl);
4318 E1000_WRITE_FLUSH(hw);
4319
4320 /* Raise and Lower the clock before reading in the data. This accounts for
4321 * the turnaround bits. The first clock occurred when we clocked out the
4322 * last bit of the Register Address.
4323 */
4324 e1000_raise_mdi_clk(hw, &ctrl);
4325 e1000_lower_mdi_clk(hw, &ctrl);
4326
4327 for (data = 0, i = 0; i < 16; i++) {
4328 data = data << 1;
4329 e1000_raise_mdi_clk(hw, &ctrl);
4330 ctrl = E1000_READ_REG(hw, CTRL);
4331 /* Check to see if we shifted in a "1". */
4332 if (ctrl & E1000_CTRL_MDIO)
4333 data |= 1;
4334 e1000_lower_mdi_clk(hw, &ctrl);
4335 }
4336
4337 e1000_raise_mdi_clk(hw, &ctrl);
4338 e1000_lower_mdi_clk(hw, &ctrl);
4339
4340 return data;
4341}
4342
4343/*****************************************************************************
4344* Reads the value from a PHY register
4345*
4346* hw - Struct containing variables accessed by shared code
4347* reg_addr - address of the PHY register to read
4348******************************************************************************/
4349static int
4350e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4351{
4352 uint32_t i;
4353 uint32_t mdic = 0;
4354 const uint32_t phy_addr = 1;
4355
4356 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4357 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4358 return -E1000_ERR_PARAM;
4359 }
4360
4361 if (hw->mac_type > e1000_82543) {
4362 /* Set up Op-code, Phy Address, and register address in the MDI
4363 * Control register. The MAC will take care of interfacing with the
4364 * PHY to retrieve the desired data.
4365 */
4366 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4367 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4368 (E1000_MDIC_OP_READ));
4369
4370 E1000_WRITE_REG(hw, MDIC, mdic);
4371
4372 /* Poll the ready bit to see if the MDI read completed */
4373 for (i = 0; i < 64; i++) {
4374 udelay(10);
4375 mdic = E1000_READ_REG(hw, MDIC);
4376 if (mdic & E1000_MDIC_READY)
4377 break;
4378 }
4379 if (!(mdic & E1000_MDIC_READY)) {
4380 DEBUGOUT("MDI Read did not complete\n");
4381 return -E1000_ERR_PHY;
4382 }
4383 if (mdic & E1000_MDIC_ERROR) {
4384 DEBUGOUT("MDI Error\n");
4385 return -E1000_ERR_PHY;
4386 }
4387 *phy_data = (uint16_t) mdic;
4388 } else {
4389 /* We must first send a preamble through the MDIO pin to signal the
4390 * beginning of an MII instruction. This is done by sending 32
4391 * consecutive "1" bits.
4392 */
4393 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4394
4395 /* Now combine the next few fields that are required for a read
4396 * operation. We use this method instead of calling the
4397 * e1000_shift_out_mdi_bits routine five different times. The format of
4398 * a MII read instruction consists of a shift out of 14 bits and is
4399 * defined as follows:
4400 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4401 * followed by a shift in of 18 bits. This first two bits shifted in
4402 * are TurnAround bits used to avoid contention on the MDIO pin when a
4403 * READ operation is performed. These two bits are thrown away
4404 * followed by a shift in of 16 bits which contains the desired data.
4405 */
4406 mdic = ((reg_addr) | (phy_addr << 5) |
4407 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4408
4409 e1000_shift_out_mdi_bits(hw, mdic, 14);
4410
4411 /* Now that we've shifted out the read command to the MII, we need to
4412 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4413 * register address.
4414 */
4415 *phy_data = e1000_shift_in_mdi_bits(hw);
4416 }
4417 return 0;
4418}
4419
4420/******************************************************************************
4421* Writes a value to a PHY register
4422*
4423* hw - Struct containing variables accessed by shared code
4424* reg_addr - address of the PHY register to write
4425* data - data to write to the PHY
4426******************************************************************************/
4427static int
4428e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4429{
4430 uint32_t i;
4431 uint32_t mdic = 0;
4432 const uint32_t phy_addr = 1;
4433
4434 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4435 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4436 return -E1000_ERR_PARAM;
4437 }
4438
4439 if (hw->mac_type > e1000_82543) {
4440 /* Set up Op-code, Phy Address, register address, and data intended
4441 * for the PHY register in the MDI Control register. The MAC will take
4442 * care of interfacing with the PHY to send the desired data.
4443 */
4444 mdic = (((uint32_t) phy_data) |
4445 (reg_addr << E1000_MDIC_REG_SHIFT) |
4446 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4447 (E1000_MDIC_OP_WRITE));
4448
4449 E1000_WRITE_REG(hw, MDIC, mdic);
4450
4451 /* Poll the ready bit to see if the MDI read completed */
4452 for (i = 0; i < 64; i++) {
4453 udelay(10);
4454 mdic = E1000_READ_REG(hw, MDIC);
4455 if (mdic & E1000_MDIC_READY)
4456 break;
Roy Zang28f7a052009-07-31 13:34:02 +08004457 }
4458 if (!(mdic & E1000_MDIC_READY)) {
4459 DEBUGOUT("MDI Write did not complete\n");
4460 return -E1000_ERR_PHY;
4461 }
4462 } else {
4463 /* We'll need to use the SW defined pins to shift the write command
4464 * out to the PHY. We first send a preamble to the PHY to signal the
4465 * beginning of the MII instruction. This is done by sending 32
4466 * consecutive "1" bits.
4467 */
4468 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4469
4470 /* Now combine the remaining required fields that will indicate a
4471 * write operation. We use this method instead of calling the
4472 * e1000_shift_out_mdi_bits routine for each field in the command. The
4473 * format of a MII write instruction is as follows:
4474 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4475 */
4476 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4477 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4478 mdic <<= 16;
4479 mdic |= (uint32_t) phy_data;
4480
4481 e1000_shift_out_mdi_bits(hw, mdic, 32);
4482 }
4483 return 0;
4484}
4485
4486/******************************************************************************
4487 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4488 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4489 * the caller to figure out how to deal with it.
4490 *
4491 * hw - Struct containing variables accessed by shared code
4492 *
4493 * returns: - E1000_BLK_PHY_RESET
4494 * E1000_SUCCESS
4495 *
4496 *****************************************************************************/
4497int32_t
4498e1000_check_phy_reset_block(struct e1000_hw *hw)
4499{
4500 uint32_t manc = 0;
4501 uint32_t fwsm = 0;
4502
4503 if (hw->mac_type == e1000_ich8lan) {
4504 fwsm = E1000_READ_REG(hw, FWSM);
4505 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4506 : E1000_BLK_PHY_RESET;
4507 }
4508
4509 if (hw->mac_type > e1000_82547_rev_2)
4510 manc = E1000_READ_REG(hw, MANC);
4511 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4512 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4513}
4514
4515/***************************************************************************
4516 * Checks if the PHY configuration is done
4517 *
4518 * hw: Struct containing variables accessed by shared code
4519 *
4520 * returns: - E1000_ERR_RESET if fail to reset MAC
4521 * E1000_SUCCESS at any other case.
4522 *
4523 ***************************************************************************/
4524static int32_t
4525e1000_get_phy_cfg_done(struct e1000_hw *hw)
4526{
4527 int32_t timeout = PHY_CFG_TIMEOUT;
4528 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4529
4530 DEBUGFUNC();
4531
4532 switch (hw->mac_type) {
4533 default:
4534 mdelay(10);
4535 break;
Kyle Moffett7376f8d2010-09-13 05:52:22 +00004536
Roy Zang28f7a052009-07-31 13:34:02 +08004537 case e1000_80003es2lan:
4538 /* Separate *_CFG_DONE_* bit for each port */
Kyle Moffett7376f8d2010-09-13 05:52:22 +00004539 if (e1000_is_second_port(hw))
Roy Zang28f7a052009-07-31 13:34:02 +08004540 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
Kyle Moffett7376f8d2010-09-13 05:52:22 +00004541 /* Fall Through */
4542
Roy Zang28f7a052009-07-31 13:34:02 +08004543 case e1000_82571:
4544 case e1000_82572:
Marek Vasut74a13c22014-08-08 07:41:39 -07004545 case e1000_igb:
Roy Zang28f7a052009-07-31 13:34:02 +08004546 while (timeout) {
Marek Vasut74a13c22014-08-08 07:41:39 -07004547 if (hw->mac_type == e1000_igb) {
Marjolaine Amatee4913352024-03-04 16:23:38 +01004548 if (hw->phy_type == e1000_phy_igc)
4549 break;
Marek Vasut74a13c22014-08-08 07:41:39 -07004550 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4551 break;
4552 } else {
4553 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4554 break;
4555 }
4556 mdelay(1);
Roy Zang28f7a052009-07-31 13:34:02 +08004557 timeout--;
wdenk4e112c12003-06-03 23:54:09 +00004558 }
Roy Zang28f7a052009-07-31 13:34:02 +08004559 if (!timeout) {
4560 DEBUGOUT("MNG configuration cycle has not "
4561 "completed.\n");
4562 return -E1000_ERR_RESET;
wdenk4e112c12003-06-03 23:54:09 +00004563 }
Roy Zang28f7a052009-07-31 13:34:02 +08004564 break;
wdenk4e112c12003-06-03 23:54:09 +00004565 }
Roy Zang28f7a052009-07-31 13:34:02 +08004566
4567 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +00004568}
4569
4570/******************************************************************************
4571* Returns the PHY to the power-on reset state
4572*
4573* hw - Struct containing variables accessed by shared code
4574******************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +08004575int32_t
wdenk4e112c12003-06-03 23:54:09 +00004576e1000_phy_hw_reset(struct e1000_hw *hw)
4577{
Kyle Moffett7376f8d2010-09-13 05:52:22 +00004578 uint16_t swfw = E1000_SWFW_PHY0_SM;
Roy Zang28f7a052009-07-31 13:34:02 +08004579 uint32_t ctrl, ctrl_ext;
4580 uint32_t led_ctrl;
4581 int32_t ret_val;
wdenk4e112c12003-06-03 23:54:09 +00004582
4583 DEBUGFUNC();
4584
Roy Zang28f7a052009-07-31 13:34:02 +08004585 /* In the case of the phy reset being blocked, it's not an error, we
4586 * simply return success without performing the reset. */
4587 ret_val = e1000_check_phy_reset_block(hw);
4588 if (ret_val)
4589 return E1000_SUCCESS;
4590
wdenk4e112c12003-06-03 23:54:09 +00004591 DEBUGOUT("Resetting Phy...\n");
4592
4593 if (hw->mac_type > e1000_82543) {
Kyle Moffett7376f8d2010-09-13 05:52:22 +00004594 if (e1000_is_second_port(hw))
Roy Zang28f7a052009-07-31 13:34:02 +08004595 swfw = E1000_SWFW_PHY1_SM;
Kyle Moffett7376f8d2010-09-13 05:52:22 +00004596
Roy Zang28f7a052009-07-31 13:34:02 +08004597 if (e1000_swfw_sync_acquire(hw, swfw)) {
4598 DEBUGOUT("Unable to acquire swfw sync\n");
4599 return -E1000_ERR_SWFW_SYNC;
4600 }
Kyle Moffett7376f8d2010-09-13 05:52:22 +00004601
wdenk4e112c12003-06-03 23:54:09 +00004602 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4603 * bit. Then, take it out of reset.
4604 */
4605 ctrl = E1000_READ_REG(hw, CTRL);
4606 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4607 E1000_WRITE_FLUSH(hw);
Roy Zang28f7a052009-07-31 13:34:02 +08004608
4609 if (hw->mac_type < e1000_82571)
4610 udelay(10);
4611 else
4612 udelay(100);
4613
wdenk4e112c12003-06-03 23:54:09 +00004614 E1000_WRITE_REG(hw, CTRL, ctrl);
4615 E1000_WRITE_FLUSH(hw);
Roy Zang28f7a052009-07-31 13:34:02 +08004616
4617 if (hw->mac_type >= e1000_82571)
4618 mdelay(10);
Tim Harveydca35652015-05-19 10:01:19 -07004619
wdenk4e112c12003-06-03 23:54:09 +00004620 } else {
4621 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4622 * bit to put the PHY into reset. Then, take it out of reset.
4623 */
4624 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4625 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4626 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4627 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4628 E1000_WRITE_FLUSH(hw);
4629 mdelay(10);
4630 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4631 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4632 E1000_WRITE_FLUSH(hw);
4633 }
4634 udelay(150);
Roy Zang28f7a052009-07-31 13:34:02 +08004635
4636 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4637 /* Configure activity LED after PHY reset */
4638 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4639 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4640 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4641 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4642 }
4643
Tim Harvey5cb59ec2015-05-19 10:01:18 -07004644 e1000_swfw_sync_release(hw, swfw);
4645
Roy Zang28f7a052009-07-31 13:34:02 +08004646 /* Wait for FW to finish PHY configuration. */
4647 ret_val = e1000_get_phy_cfg_done(hw);
4648 if (ret_val != E1000_SUCCESS)
4649 return ret_val;
4650
4651 return ret_val;
4652}
4653
4654/******************************************************************************
4655 * IGP phy init script - initializes the GbE PHY
4656 *
4657 * hw - Struct containing variables accessed by shared code
4658 *****************************************************************************/
4659static void
4660e1000_phy_init_script(struct e1000_hw *hw)
4661{
4662 uint32_t ret_val;
4663 uint16_t phy_saved_data;
4664 DEBUGFUNC();
4665
4666 if (hw->phy_init_script) {
4667 mdelay(20);
4668
4669 /* Save off the current value of register 0x2F5B to be
4670 * restored at the end of this routine. */
4671 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4672
4673 /* Disabled the PHY transmitter */
4674 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4675
4676 mdelay(20);
4677
4678 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4679
4680 mdelay(5);
4681
4682 switch (hw->mac_type) {
4683 case e1000_82541:
4684 case e1000_82547:
4685 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4686
4687 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4688
4689 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4690
4691 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4692
4693 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4694
4695 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4696
4697 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4698
4699 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4700
4701 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4702 break;
4703
4704 case e1000_82541_rev_2:
4705 case e1000_82547_rev_2:
4706 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4707 break;
4708 default:
4709 break;
4710 }
4711
4712 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4713
4714 mdelay(20);
4715
4716 /* Now enable the transmitter */
Zang Roy-R61911e36d67c2011-11-06 22:22:36 +00004717 if (!ret_val)
4718 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
Roy Zang28f7a052009-07-31 13:34:02 +08004719
4720 if (hw->mac_type == e1000_82547) {
4721 uint16_t fused, fine, coarse;
4722
4723 /* Move to analog registers page */
4724 e1000_read_phy_reg(hw,
4725 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4726
4727 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4728 e1000_read_phy_reg(hw,
4729 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4730
4731 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4732 coarse = fused
4733 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4734
4735 if (coarse >
4736 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4737 coarse -=
4738 IGP01E1000_ANALOG_FUSE_COARSE_10;
4739 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4740 } else if (coarse
4741 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4742 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4743
4744 fused = (fused
4745 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4746 (fine
4747 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4748 (coarse
4749 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4750
4751 e1000_write_phy_reg(hw,
4752 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4753 e1000_write_phy_reg(hw,
4754 IGP01E1000_ANALOG_FUSE_BYPASS,
4755 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4756 }
4757 }
4758 }
wdenk4e112c12003-06-03 23:54:09 +00004759}
4760
4761/******************************************************************************
4762* Resets the PHY
4763*
4764* hw - Struct containing variables accessed by shared code
4765*
Roy Zang28f7a052009-07-31 13:34:02 +08004766* Sets bit 15 of the MII Control register
wdenk4e112c12003-06-03 23:54:09 +00004767******************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +08004768int32_t
wdenk4e112c12003-06-03 23:54:09 +00004769e1000_phy_reset(struct e1000_hw *hw)
4770{
Roy Zang28f7a052009-07-31 13:34:02 +08004771 int32_t ret_val;
wdenk4e112c12003-06-03 23:54:09 +00004772 uint16_t phy_data;
4773
4774 DEBUGFUNC();
4775
Roy Zang28f7a052009-07-31 13:34:02 +08004776 /* In the case of the phy reset being blocked, it's not an error, we
4777 * simply return success without performing the reset. */
4778 ret_val = e1000_check_phy_reset_block(hw);
4779 if (ret_val)
4780 return E1000_SUCCESS;
4781
4782 switch (hw->phy_type) {
4783 case e1000_phy_igp:
4784 case e1000_phy_igp_2:
4785 case e1000_phy_igp_3:
4786 case e1000_phy_ife:
Marek Vasut74a13c22014-08-08 07:41:39 -07004787 case e1000_phy_igb:
Marjolaine Amatee4913352024-03-04 16:23:38 +01004788 case e1000_phy_igc:
Roy Zang28f7a052009-07-31 13:34:02 +08004789 ret_val = e1000_phy_hw_reset(hw);
4790 if (ret_val)
4791 return ret_val;
4792 break;
4793 default:
4794 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4795 if (ret_val)
4796 return ret_val;
4797
4798 phy_data |= MII_CR_RESET;
4799 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4800 if (ret_val)
4801 return ret_val;
4802
4803 udelay(1);
4804 break;
wdenk4e112c12003-06-03 23:54:09 +00004805 }
Roy Zang28f7a052009-07-31 13:34:02 +08004806
4807 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4808 e1000_phy_init_script(hw);
4809
4810 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +00004811}
4812
Wolfgang Denk35f734f2008-04-13 09:59:26 -07004813static int e1000_set_phy_type (struct e1000_hw *hw)
Andre Schwarz68c2a302008-03-06 16:45:44 +01004814{
Wolfgang Denk35f734f2008-04-13 09:59:26 -07004815 DEBUGFUNC ();
Andre Schwarz68c2a302008-03-06 16:45:44 +01004816
Wolfgang Denk35f734f2008-04-13 09:59:26 -07004817 if (hw->mac_type == e1000_undefined)
4818 return -E1000_ERR_PHY_TYPE;
Andre Schwarz68c2a302008-03-06 16:45:44 +01004819
Wolfgang Denk35f734f2008-04-13 09:59:26 -07004820 switch (hw->phy_id) {
4821 case M88E1000_E_PHY_ID:
4822 case M88E1000_I_PHY_ID:
4823 case M88E1011_I_PHY_ID:
Roy Zang28f7a052009-07-31 13:34:02 +08004824 case M88E1111_I_PHY_ID:
Wolfgang Denk35f734f2008-04-13 09:59:26 -07004825 hw->phy_type = e1000_phy_m88;
4826 break;
4827 case IGP01E1000_I_PHY_ID:
4828 if (hw->mac_type == e1000_82541 ||
Roy Zang28f7a052009-07-31 13:34:02 +08004829 hw->mac_type == e1000_82541_rev_2 ||
4830 hw->mac_type == e1000_82547 ||
4831 hw->mac_type == e1000_82547_rev_2) {
Wolfgang Denk35f734f2008-04-13 09:59:26 -07004832 hw->phy_type = e1000_phy_igp;
Roy Zang28f7a052009-07-31 13:34:02 +08004833 break;
4834 }
Andre Przywarabb6b6aa2025-03-27 15:33:06 +00004835 fallthrough;
Roy Zang28f7a052009-07-31 13:34:02 +08004836 case IGP03E1000_E_PHY_ID:
4837 hw->phy_type = e1000_phy_igp_3;
4838 break;
4839 case IFE_E_PHY_ID:
4840 case IFE_PLUS_E_PHY_ID:
4841 case IFE_C_E_PHY_ID:
4842 hw->phy_type = e1000_phy_ife;
4843 break;
4844 case GG82563_E_PHY_ID:
4845 if (hw->mac_type == e1000_80003es2lan) {
4846 hw->phy_type = e1000_phy_gg82563;
Wolfgang Denk35f734f2008-04-13 09:59:26 -07004847 break;
4848 }
Andre Przywarabb6b6aa2025-03-27 15:33:06 +00004849 fallthrough;
Roy Zang181119b2011-01-21 11:29:38 +08004850 case BME1000_E_PHY_ID:
4851 hw->phy_type = e1000_phy_bm;
4852 break;
Marek Vasut74a13c22014-08-08 07:41:39 -07004853 case I210_I_PHY_ID:
4854 hw->phy_type = e1000_phy_igb;
4855 break;
Marjolaine Amatee4913352024-03-04 16:23:38 +01004856 case I225_I_PHY_ID:
ZhiJie.zhang87e00132025-04-21 17:08:26 +08004857 case I225_V_PHY_ID:
Marjolaine Amate0cef7802024-06-24 19:15:32 +00004858 case I226_LM_PHY_ID:
4859 case I226_I_PHY_ID:
Marjolaine Amatee4913352024-03-04 16:23:38 +01004860 hw->phy_type = e1000_phy_igc;
4861 break;
Wolfgang Denk35f734f2008-04-13 09:59:26 -07004862 /* Fall Through */
4863 default:
4864 /* Should never have loaded on this device */
4865 hw->phy_type = e1000_phy_undefined;
4866 return -E1000_ERR_PHY_TYPE;
4867 }
Andre Schwarz68c2a302008-03-06 16:45:44 +01004868
Wolfgang Denk35f734f2008-04-13 09:59:26 -07004869 return E1000_SUCCESS;
Andre Schwarz68c2a302008-03-06 16:45:44 +01004870}
4871
wdenk4e112c12003-06-03 23:54:09 +00004872/******************************************************************************
4873* Probes the expected PHY address for known PHY IDs
4874*
4875* hw - Struct containing variables accessed by shared code
4876******************************************************************************/
Roy Zang28f7a052009-07-31 13:34:02 +08004877static int32_t
wdenk4e112c12003-06-03 23:54:09 +00004878e1000_detect_gig_phy(struct e1000_hw *hw)
4879{
Roy Zang28f7a052009-07-31 13:34:02 +08004880 int32_t phy_init_status, ret_val;
wdenk4e112c12003-06-03 23:54:09 +00004881 uint16_t phy_id_high, phy_id_low;
York Sun4a598092013-04-01 11:29:11 -07004882 bool match = false;
wdenk4e112c12003-06-03 23:54:09 +00004883
4884 DEBUGFUNC();
4885
Roy Zang28f7a052009-07-31 13:34:02 +08004886 /* The 82571 firmware may still be configuring the PHY. In this
4887 * case, we cannot access the PHY until the configuration is done. So
4888 * we explicitly set the PHY values. */
4889 if (hw->mac_type == e1000_82571 ||
4890 hw->mac_type == e1000_82572) {
4891 hw->phy_id = IGP01E1000_I_PHY_ID;
4892 hw->phy_type = e1000_phy_igp_2;
4893 return E1000_SUCCESS;
wdenk4e112c12003-06-03 23:54:09 +00004894 }
Roy Zang28f7a052009-07-31 13:34:02 +08004895
4896 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4897 * work- around that forces PHY page 0 to be set or the reads fail.
4898 * The rest of the code in this routine uses e1000_read_phy_reg to
4899 * read the PHY ID. So for ESB-2 we need to have this set so our
4900 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4901 * the routines below will figure this out as well. */
4902 if (hw->mac_type == e1000_80003es2lan)
4903 hw->phy_type = e1000_phy_gg82563;
4904
4905 /* Read the PHY ID Registers to identify which PHY is onboard. */
4906 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4907 if (ret_val)
4908 return ret_val;
4909
wdenk4e112c12003-06-03 23:54:09 +00004910 hw->phy_id = (uint32_t) (phy_id_high << 16);
Roy Zang28f7a052009-07-31 13:34:02 +08004911 udelay(20);
4912 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4913 if (ret_val)
4914 return ret_val;
4915
wdenk4e112c12003-06-03 23:54:09 +00004916 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
Roy Zang28f7a052009-07-31 13:34:02 +08004917 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
wdenk4e112c12003-06-03 23:54:09 +00004918
4919 switch (hw->mac_type) {
4920 case e1000_82543:
4921 if (hw->phy_id == M88E1000_E_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004922 match = true;
wdenk4e112c12003-06-03 23:54:09 +00004923 break;
4924 case e1000_82544:
4925 if (hw->phy_id == M88E1000_I_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004926 match = true;
wdenk4e112c12003-06-03 23:54:09 +00004927 break;
4928 case e1000_82540:
4929 case e1000_82545:
Roy Zang28f7a052009-07-31 13:34:02 +08004930 case e1000_82545_rev_3:
wdenk4e112c12003-06-03 23:54:09 +00004931 case e1000_82546:
Roy Zang28f7a052009-07-31 13:34:02 +08004932 case e1000_82546_rev_3:
wdenk4e112c12003-06-03 23:54:09 +00004933 if (hw->phy_id == M88E1011_I_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004934 match = true;
Andre Schwarz68c2a302008-03-06 16:45:44 +01004935 break;
Roy Zang28f7a052009-07-31 13:34:02 +08004936 case e1000_82541:
Andre Schwarz68c2a302008-03-06 16:45:44 +01004937 case e1000_82541_rev_2:
Roy Zang28f7a052009-07-31 13:34:02 +08004938 case e1000_82547:
4939 case e1000_82547_rev_2:
Andre Schwarz68c2a302008-03-06 16:45:44 +01004940 if(hw->phy_id == IGP01E1000_I_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004941 match = true;
Andre Schwarz68c2a302008-03-06 16:45:44 +01004942
wdenk4e112c12003-06-03 23:54:09 +00004943 break;
Roy Zang28f7a052009-07-31 13:34:02 +08004944 case e1000_82573:
4945 if (hw->phy_id == M88E1111_I_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004946 match = true;
Roy Zang28f7a052009-07-31 13:34:02 +08004947 break;
Roy Zang181119b2011-01-21 11:29:38 +08004948 case e1000_82574:
4949 if (hw->phy_id == BME1000_E_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004950 match = true;
Roy Zang181119b2011-01-21 11:29:38 +08004951 break;
Roy Zang28f7a052009-07-31 13:34:02 +08004952 case e1000_80003es2lan:
4953 if (hw->phy_id == GG82563_E_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004954 match = true;
Roy Zang28f7a052009-07-31 13:34:02 +08004955 break;
4956 case e1000_ich8lan:
4957 if (hw->phy_id == IGP03E1000_E_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004958 match = true;
Roy Zang28f7a052009-07-31 13:34:02 +08004959 if (hw->phy_id == IFE_E_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004960 match = true;
Roy Zang28f7a052009-07-31 13:34:02 +08004961 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004962 match = true;
Roy Zang28f7a052009-07-31 13:34:02 +08004963 if (hw->phy_id == IFE_C_E_PHY_ID)
York Sun4a598092013-04-01 11:29:11 -07004964 match = true;
Roy Zang28f7a052009-07-31 13:34:02 +08004965 break;
Marek Vasut74a13c22014-08-08 07:41:39 -07004966 case e1000_igb:
4967 if (hw->phy_id == I210_I_PHY_ID)
4968 match = true;
Marjolaine Amatee4913352024-03-04 16:23:38 +01004969 if (hw->phy_id == I225_I_PHY_ID)
4970 match = true;
ZhiJie.zhang87e00132025-04-21 17:08:26 +08004971 if (hw->phy_id == I225_V_PHY_ID)
4972 match = true;
Marjolaine Amate0cef7802024-06-24 19:15:32 +00004973 if (hw->phy_id == I226_LM_PHY_ID)
4974 match = true;
4975 if (hw->phy_id == I226_I_PHY_ID)
4976 match = true;
Marek Vasut74a13c22014-08-08 07:41:39 -07004977 break;
wdenk4e112c12003-06-03 23:54:09 +00004978 default:
4979 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4980 return -E1000_ERR_CONFIG;
4981 }
Andre Schwarz68c2a302008-03-06 16:45:44 +01004982
4983 phy_init_status = e1000_set_phy_type(hw);
4984
4985 if ((match) && (phy_init_status == E1000_SUCCESS)) {
wdenk4e112c12003-06-03 23:54:09 +00004986 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4987 return 0;
4988 }
4989 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4990 return -E1000_ERR_PHY;
4991}
4992
Roy Zang28f7a052009-07-31 13:34:02 +08004993/*****************************************************************************
4994 * Set media type and TBI compatibility.
4995 *
4996 * hw - Struct containing variables accessed by shared code
4997 * **************************************************************************/
4998void
4999e1000_set_media_type(struct e1000_hw *hw)
5000{
5001 uint32_t status;
5002
5003 DEBUGFUNC();
5004
5005 if (hw->mac_type != e1000_82543) {
5006 /* tbi_compatibility is only valid on 82543 */
York Sun4a598092013-04-01 11:29:11 -07005007 hw->tbi_compatibility_en = false;
Roy Zang28f7a052009-07-31 13:34:02 +08005008 }
5009
5010 switch (hw->device_id) {
5011 case E1000_DEV_ID_82545GM_SERDES:
5012 case E1000_DEV_ID_82546GB_SERDES:
5013 case E1000_DEV_ID_82571EB_SERDES:
5014 case E1000_DEV_ID_82571EB_SERDES_DUAL:
5015 case E1000_DEV_ID_82571EB_SERDES_QUAD:
5016 case E1000_DEV_ID_82572EI_SERDES:
5017 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
5018 hw->media_type = e1000_media_type_internal_serdes;
5019 break;
5020 default:
5021 switch (hw->mac_type) {
5022 case e1000_82542_rev2_0:
5023 case e1000_82542_rev2_1:
5024 hw->media_type = e1000_media_type_fiber;
5025 break;
5026 case e1000_ich8lan:
5027 case e1000_82573:
Roy Zang181119b2011-01-21 11:29:38 +08005028 case e1000_82574:
Marek Vasut74a13c22014-08-08 07:41:39 -07005029 case e1000_igb:
Roy Zang28f7a052009-07-31 13:34:02 +08005030 /* The STATUS_TBIMODE bit is reserved or reused
5031 * for the this device.
5032 */
5033 hw->media_type = e1000_media_type_copper;
5034 break;
5035 default:
5036 status = E1000_READ_REG(hw, STATUS);
5037 if (status & E1000_STATUS_TBIMODE) {
5038 hw->media_type = e1000_media_type_fiber;
5039 /* tbi_compatibility not valid on fiber */
York Sun4a598092013-04-01 11:29:11 -07005040 hw->tbi_compatibility_en = false;
Roy Zang28f7a052009-07-31 13:34:02 +08005041 } else {
5042 hw->media_type = e1000_media_type_copper;
5043 }
5044 break;
5045 }
5046 }
5047}
5048
wdenk4e112c12003-06-03 23:54:09 +00005049/**
5050 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
5051 *
5052 * e1000_sw_init initializes the Adapter private data structure.
5053 * Fields are initialized based on PCI device information and
5054 * OS network device settings (MTU size).
5055 **/
5056
5057static int
Simon Glassc53abc32015-08-19 09:33:39 -06005058e1000_sw_init(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +00005059{
wdenk4e112c12003-06-03 23:54:09 +00005060 int result;
5061
5062 /* PCI config space info */
Bin Meng83cf24c2016-02-02 05:58:01 -08005063 dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5064 dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5065 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5066 &hw->subsystem_vendor_id);
5067 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5068
5069 dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5070 dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
wdenk4e112c12003-06-03 23:54:09 +00005071
5072 /* identify the MAC */
5073 result = e1000_set_mac_type(hw);
5074 if (result) {
Simon Glassc53abc32015-08-19 09:33:39 -06005075 E1000_ERR(hw, "Unknown MAC Type\n");
wdenk4e112c12003-06-03 23:54:09 +00005076 return result;
5077 }
5078
Roy Zang28f7a052009-07-31 13:34:02 +08005079 switch (hw->mac_type) {
5080 default:
5081 break;
5082 case e1000_82541:
5083 case e1000_82547:
5084 case e1000_82541_rev_2:
5085 case e1000_82547_rev_2:
5086 hw->phy_init_script = 1;
5087 break;
5088 }
5089
wdenk4e112c12003-06-03 23:54:09 +00005090 /* flow control settings */
5091 hw->fc_high_water = E1000_FC_HIGH_THRESH;
5092 hw->fc_low_water = E1000_FC_LOW_THRESH;
5093 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
5094 hw->fc_send_xon = 1;
5095
5096 /* Media type - copper or fiber */
Marek Vasut74a13c22014-08-08 07:41:39 -07005097 hw->tbi_compatibility_en = true;
Roy Zang28f7a052009-07-31 13:34:02 +08005098 e1000_set_media_type(hw);
wdenk4e112c12003-06-03 23:54:09 +00005099
5100 if (hw->mac_type >= e1000_82543) {
5101 uint32_t status = E1000_READ_REG(hw, STATUS);
5102
5103 if (status & E1000_STATUS_TBIMODE) {
5104 DEBUGOUT("fiber interface\n");
5105 hw->media_type = e1000_media_type_fiber;
5106 } else {
5107 DEBUGOUT("copper interface\n");
5108 hw->media_type = e1000_media_type_copper;
5109 }
5110 } else {
5111 hw->media_type = e1000_media_type_fiber;
5112 }
5113
York Sun4a598092013-04-01 11:29:11 -07005114 hw->wait_autoneg_complete = true;
wdenk4e112c12003-06-03 23:54:09 +00005115 if (hw->mac_type < e1000_82543)
5116 hw->report_tx_early = 0;
5117 else
5118 hw->report_tx_early = 1;
5119
wdenk4e112c12003-06-03 23:54:09 +00005120 return E1000_SUCCESS;
5121}
5122
5123void
5124fill_rx(struct e1000_hw *hw)
5125{
5126 struct e1000_rx_desc *rd;
Minghuan Liane2e4b782015-01-22 13:21:54 +08005127 unsigned long flush_start, flush_end;
wdenk4e112c12003-06-03 23:54:09 +00005128
5129 rx_last = rx_tail;
5130 rd = rx_base + rx_tail;
5131 rx_tail = (rx_tail + 1) % 8;
5132 memset(rd, 0, 16);
Stefan Roesee1789942020-11-16 18:02:30 +01005133 rd->buffer_addr = cpu_to_le64(virt_to_phys(packet));
Marek Vasut742c5c22014-08-08 07:41:38 -07005134
5135 /*
5136 * Make sure there are no stale data in WB over this area, which
5137 * might get written into the memory while the e1000 also writes
5138 * into the same memory area.
5139 */
Minghuan Liane2e4b782015-01-22 13:21:54 +08005140 invalidate_dcache_range((unsigned long)packet,
5141 (unsigned long)packet + 4096);
Marek Vasut742c5c22014-08-08 07:41:38 -07005142 /* Dump the DMA descriptor into RAM. */
Minghuan Liane2e4b782015-01-22 13:21:54 +08005143 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
Marek Vasut742c5c22014-08-08 07:41:38 -07005144 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5145 flush_dcache_range(flush_start, flush_end);
5146
wdenk4e112c12003-06-03 23:54:09 +00005147 E1000_WRITE_REG(hw, RDT, rx_tail);
5148}
5149
5150/**
5151 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
5152 * @adapter: board private structure
5153 *
5154 * Configure the Tx unit of the MAC after a reset.
5155 **/
5156
5157static void
5158e1000_configure_tx(struct e1000_hw *hw)
5159{
wdenk4e112c12003-06-03 23:54:09 +00005160 unsigned long tctl;
Roy Zang28f7a052009-07-31 13:34:02 +08005161 unsigned long tipg, tarc;
5162 uint32_t ipgr1, ipgr2;
wdenk4e112c12003-06-03 23:54:09 +00005163
Stefan Roesee1789942020-11-16 18:02:30 +01005164 E1000_WRITE_REG(hw, TDBAL, lower_32_bits(virt_to_phys(tx_base)));
5165 E1000_WRITE_REG(hw, TDBAH, upper_32_bits(virt_to_phys(tx_base)));
wdenk4e112c12003-06-03 23:54:09 +00005166
5167 E1000_WRITE_REG(hw, TDLEN, 128);
5168
5169 /* Setup the HW Tx Head and Tail descriptor pointers */
5170 E1000_WRITE_REG(hw, TDH, 0);
5171 E1000_WRITE_REG(hw, TDT, 0);
5172 tx_tail = 0;
5173
5174 /* Set the default values for the Tx Inter Packet Gap timer */
Roy Zang28f7a052009-07-31 13:34:02 +08005175 if (hw->mac_type <= e1000_82547_rev_2 &&
5176 (hw->media_type == e1000_media_type_fiber ||
5177 hw->media_type == e1000_media_type_internal_serdes))
5178 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5179 else
5180 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5181
5182 /* Set the default values for the Tx Inter Packet Gap timer */
wdenk4e112c12003-06-03 23:54:09 +00005183 switch (hw->mac_type) {
5184 case e1000_82542_rev2_0:
5185 case e1000_82542_rev2_1:
5186 tipg = DEFAULT_82542_TIPG_IPGT;
Roy Zang28f7a052009-07-31 13:34:02 +08005187 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5188 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5189 break;
5190 case e1000_80003es2lan:
5191 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5192 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
wdenk4e112c12003-06-03 23:54:09 +00005193 break;
5194 default:
Roy Zang28f7a052009-07-31 13:34:02 +08005195 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5196 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5197 break;
wdenk4e112c12003-06-03 23:54:09 +00005198 }
Roy Zang28f7a052009-07-31 13:34:02 +08005199 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5200 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
wdenk4e112c12003-06-03 23:54:09 +00005201 E1000_WRITE_REG(hw, TIPG, tipg);
wdenk4e112c12003-06-03 23:54:09 +00005202 /* Program the Transmit Control Register */
5203 tctl = E1000_READ_REG(hw, TCTL);
5204 tctl &= ~E1000_TCTL_CT;
5205 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5206 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
Roy Zang28f7a052009-07-31 13:34:02 +08005207
5208 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5209 tarc = E1000_READ_REG(hw, TARC0);
5210 /* set the speed mode bit, we'll clear it if we're not at
5211 * gigabit link later */
5212 /* git bit can be set to 1*/
5213 } else if (hw->mac_type == e1000_80003es2lan) {
5214 tarc = E1000_READ_REG(hw, TARC0);
5215 tarc |= 1;
5216 E1000_WRITE_REG(hw, TARC0, tarc);
5217 tarc = E1000_READ_REG(hw, TARC1);
5218 tarc |= 1;
5219 E1000_WRITE_REG(hw, TARC1, tarc);
5220 }
5221
wdenk4e112c12003-06-03 23:54:09 +00005222 e1000_config_collision_dist(hw);
Roy Zang28f7a052009-07-31 13:34:02 +08005223 /* Setup Transmit Descriptor Settings for eop descriptor */
5224 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
wdenk4e112c12003-06-03 23:54:09 +00005225
Roy Zang28f7a052009-07-31 13:34:02 +08005226 /* Need to set up RS bit */
5227 if (hw->mac_type < e1000_82543)
5228 hw->txd_cmd |= E1000_TXD_CMD_RPS;
wdenk4e112c12003-06-03 23:54:09 +00005229 else
Roy Zang28f7a052009-07-31 13:34:02 +08005230 hw->txd_cmd |= E1000_TXD_CMD_RS;
Marek Vasut74a13c22014-08-08 07:41:39 -07005231
Marek Vasut74a13c22014-08-08 07:41:39 -07005232 if (hw->mac_type == e1000_igb) {
5233 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5234
5235 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5236 reg_txdctl |= 1 << 25;
5237 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5238 mdelay(20);
5239 }
5240
Roy Zang28f7a052009-07-31 13:34:02 +08005241 E1000_WRITE_REG(hw, TCTL, tctl);
wdenk4e112c12003-06-03 23:54:09 +00005242}
5243
5244/**
5245 * e1000_setup_rctl - configure the receive control register
5246 * @adapter: Board private structure
5247 **/
5248static void
5249e1000_setup_rctl(struct e1000_hw *hw)
5250{
5251 uint32_t rctl;
5252
5253 rctl = E1000_READ_REG(hw, RCTL);
5254
5255 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5256
Roy Zang28f7a052009-07-31 13:34:02 +08005257 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5258 | E1000_RCTL_RDMTS_HALF; /* |
5259 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
wdenk4e112c12003-06-03 23:54:09 +00005260
5261 if (hw->tbi_compatibility_on == 1)
5262 rctl |= E1000_RCTL_SBP;
5263 else
5264 rctl &= ~E1000_RCTL_SBP;
5265
5266 rctl &= ~(E1000_RCTL_SZ_4096);
wdenk4e112c12003-06-03 23:54:09 +00005267 rctl |= E1000_RCTL_SZ_2048;
5268 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
wdenk4e112c12003-06-03 23:54:09 +00005269 E1000_WRITE_REG(hw, RCTL, rctl);
5270}
5271
5272/**
5273 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5274 * @adapter: board private structure
5275 *
5276 * Configure the Rx unit of the MAC after a reset.
5277 **/
5278static void
5279e1000_configure_rx(struct e1000_hw *hw)
5280{
Roy Zang28f7a052009-07-31 13:34:02 +08005281 unsigned long rctl, ctrl_ext;
wdenk4e112c12003-06-03 23:54:09 +00005282 rx_tail = 0;
Bin Mengd0ee7d02015-08-26 06:17:27 -07005283
wdenk4e112c12003-06-03 23:54:09 +00005284 /* make sure receives are disabled while setting up the descriptors */
5285 rctl = E1000_READ_REG(hw, RCTL);
5286 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
wdenk4e112c12003-06-03 23:54:09 +00005287 if (hw->mac_type >= e1000_82540) {
wdenk4e112c12003-06-03 23:54:09 +00005288 /* Set the interrupt throttling rate. Value is calculated
5289 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
Wolfgang Denk35f734f2008-04-13 09:59:26 -07005290#define MAX_INTS_PER_SEC 8000
5291#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
wdenk4e112c12003-06-03 23:54:09 +00005292 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5293 }
5294
Roy Zang28f7a052009-07-31 13:34:02 +08005295 if (hw->mac_type >= e1000_82571) {
5296 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5297 /* Reset delay timers after every interrupt */
5298 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5299 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5300 E1000_WRITE_FLUSH(hw);
5301 }
wdenk4e112c12003-06-03 23:54:09 +00005302 /* Setup the Base and Length of the Rx Descriptor Ring */
Stefan Roesee1789942020-11-16 18:02:30 +01005303 E1000_WRITE_REG(hw, RDBAL, lower_32_bits(virt_to_phys(rx_base)));
5304 E1000_WRITE_REG(hw, RDBAH, upper_32_bits(virt_to_phys(rx_base)));
wdenk4e112c12003-06-03 23:54:09 +00005305
5306 E1000_WRITE_REG(hw, RDLEN, 128);
5307
5308 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5309 E1000_WRITE_REG(hw, RDH, 0);
5310 E1000_WRITE_REG(hw, RDT, 0);
wdenk4e112c12003-06-03 23:54:09 +00005311 /* Enable Receives */
5312
Marek Vasut74a13c22014-08-08 07:41:39 -07005313 if (hw->mac_type == e1000_igb) {
5314
5315 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5316 reg_rxdctl |= 1 << 25;
5317 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5318 mdelay(20);
5319 }
5320
wdenk4e112c12003-06-03 23:54:09 +00005321 E1000_WRITE_REG(hw, RCTL, rctl);
Marek Vasut74a13c22014-08-08 07:41:39 -07005322
wdenk4e112c12003-06-03 23:54:09 +00005323 fill_rx(hw);
5324}
5325
5326/**************************************************************************
5327POLL - Wait for a frame
5328***************************************************************************/
5329static int
Simon Glassc53abc32015-08-19 09:33:39 -06005330_e1000_poll(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +00005331{
wdenk4e112c12003-06-03 23:54:09 +00005332 struct e1000_rx_desc *rd;
Minghuan Liane2e4b782015-01-22 13:21:54 +08005333 unsigned long inval_start, inval_end;
Marek Vasut742c5c22014-08-08 07:41:38 -07005334 uint32_t len;
5335
wdenk4e112c12003-06-03 23:54:09 +00005336 /* return true if there's an ethernet packet ready to read */
5337 rd = rx_base + rx_last;
Marek Vasut742c5c22014-08-08 07:41:38 -07005338
5339 /* Re-load the descriptor from RAM. */
Minghuan Liane2e4b782015-01-22 13:21:54 +08005340 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
Marek Vasut742c5c22014-08-08 07:41:38 -07005341 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5342 invalidate_dcache_range(inval_start, inval_end);
5343
Miao Yan41a084a2015-12-21 02:07:02 -08005344 if (!(rd->status & E1000_RXD_STAT_DD))
wdenk4e112c12003-06-03 23:54:09 +00005345 return 0;
Minghuan Lian674bcd52015-03-19 09:43:51 -07005346 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
Marek Vasut742c5c22014-08-08 07:41:38 -07005347 /* Packet received, make sure the data are re-loaded from RAM. */
Miao Yan41a084a2015-12-21 02:07:02 -08005348 len = le16_to_cpu(rd->length);
Minghuan Liane2e4b782015-01-22 13:21:54 +08005349 invalidate_dcache_range((unsigned long)packet,
5350 (unsigned long)packet +
5351 roundup(len, ARCH_DMA_MINALIGN));
Simon Glassc53abc32015-08-19 09:33:39 -06005352 return len;
wdenk4e112c12003-06-03 23:54:09 +00005353}
5354
Simon Glassc53abc32015-08-19 09:33:39 -06005355static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
wdenk4e112c12003-06-03 23:54:09 +00005356{
Marek Vasut742c5c22014-08-08 07:41:38 -07005357 void *nv_packet = (void *)txpacket;
wdenk4e112c12003-06-03 23:54:09 +00005358 struct e1000_tx_desc *txp;
5359 int i = 0;
Minghuan Liane2e4b782015-01-22 13:21:54 +08005360 unsigned long flush_start, flush_end;
wdenk4e112c12003-06-03 23:54:09 +00005361
5362 txp = tx_base + tx_tail;
5363 tx_tail = (tx_tail + 1) % 8;
5364
Stefan Roese0a1a3292020-11-16 18:02:29 +01005365 txp->buffer_addr = cpu_to_le64(virt_to_phys(nv_packet));
Roy Zang28f7a052009-07-31 13:34:02 +08005366 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
wdenk4e112c12003-06-03 23:54:09 +00005367 txp->upper.data = 0;
Marek Vasut742c5c22014-08-08 07:41:38 -07005368
5369 /* Dump the packet into RAM so e1000 can pick them. */
Minghuan Liane2e4b782015-01-22 13:21:54 +08005370 flush_dcache_range((unsigned long)nv_packet,
5371 (unsigned long)nv_packet +
5372 roundup(length, ARCH_DMA_MINALIGN));
Marek Vasut742c5c22014-08-08 07:41:38 -07005373 /* Dump the descriptor into RAM as well. */
Minghuan Liane2e4b782015-01-22 13:21:54 +08005374 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
Marek Vasut742c5c22014-08-08 07:41:38 -07005375 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5376 flush_dcache_range(flush_start, flush_end);
5377
wdenk4e112c12003-06-03 23:54:09 +00005378 E1000_WRITE_REG(hw, TDT, tx_tail);
5379
Roy Zang28f7a052009-07-31 13:34:02 +08005380 E1000_WRITE_FLUSH(hw);
Marek Vasut742c5c22014-08-08 07:41:38 -07005381 while (1) {
5382 invalidate_dcache_range(flush_start, flush_end);
5383 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5384 break;
wdenk4e112c12003-06-03 23:54:09 +00005385 if (i++ > TOUT_LOOP) {
5386 DEBUGOUT("e1000: tx timeout\n");
5387 return 0;
5388 }
5389 udelay(10); /* give the nic a chance to write to the register */
5390 }
5391 return 1;
5392}
5393
wdenk4e112c12003-06-03 23:54:09 +00005394static void
Simon Glassc53abc32015-08-19 09:33:39 -06005395_e1000_disable(struct e1000_hw *hw)
wdenk4e112c12003-06-03 23:54:09 +00005396{
wdenk4e112c12003-06-03 23:54:09 +00005397 /* Turn off the ethernet interface */
5398 E1000_WRITE_REG(hw, RCTL, 0);
5399 E1000_WRITE_REG(hw, TCTL, 0);
5400
5401 /* Clear the transmit ring */
5402 E1000_WRITE_REG(hw, TDH, 0);
5403 E1000_WRITE_REG(hw, TDT, 0);
5404
5405 /* Clear the receive ring */
5406 E1000_WRITE_REG(hw, RDH, 0);
5407 E1000_WRITE_REG(hw, RDT, 0);
5408
wdenk4e112c12003-06-03 23:54:09 +00005409 mdelay(10);
Simon Glassc53abc32015-08-19 09:33:39 -06005410}
wdenk4e112c12003-06-03 23:54:09 +00005411
Simon Glassc53abc32015-08-19 09:33:39 -06005412/*reset function*/
5413static inline int
5414e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5415{
5416 e1000_reset_hw(hw);
5417 if (hw->mac_type >= e1000_82544)
5418 E1000_WRITE_REG(hw, WUC, 0);
5419
5420 return e1000_init_hw(hw, enetaddr);
wdenk4e112c12003-06-03 23:54:09 +00005421}
5422
wdenk4e112c12003-06-03 23:54:09 +00005423static int
Simon Glassc53abc32015-08-19 09:33:39 -06005424_e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
wdenk4e112c12003-06-03 23:54:09 +00005425{
wdenk4e112c12003-06-03 23:54:09 +00005426 int ret_val = 0;
5427
Simon Glassc53abc32015-08-19 09:33:39 -06005428 ret_val = e1000_reset(hw, enetaddr);
wdenk4e112c12003-06-03 23:54:09 +00005429 if (ret_val < 0) {
5430 if ((ret_val == -E1000_ERR_NOLINK) ||
5431 (ret_val == -E1000_ERR_TIMEOUT)) {
Simon Glassc53abc32015-08-19 09:33:39 -06005432 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
wdenk4e112c12003-06-03 23:54:09 +00005433 } else {
Simon Glassc53abc32015-08-19 09:33:39 -06005434 E1000_ERR(hw, "Hardware Initialization Failed\n");
wdenk4e112c12003-06-03 23:54:09 +00005435 }
Simon Glassc53abc32015-08-19 09:33:39 -06005436 return ret_val;
wdenk4e112c12003-06-03 23:54:09 +00005437 }
5438 e1000_configure_tx(hw);
5439 e1000_setup_rctl(hw);
5440 e1000_configure_rx(hw);
Simon Glassc53abc32015-08-19 09:33:39 -06005441 return 0;
wdenk4e112c12003-06-03 23:54:09 +00005442}
5443
Roy Zang28f7a052009-07-31 13:34:02 +08005444/******************************************************************************
5445 * Gets the current PCI bus type of hardware
5446 *
5447 * hw - Struct containing variables accessed by shared code
5448 *****************************************************************************/
5449void e1000_get_bus_type(struct e1000_hw *hw)
5450{
5451 uint32_t status;
5452
5453 switch (hw->mac_type) {
5454 case e1000_82542_rev2_0:
5455 case e1000_82542_rev2_1:
5456 hw->bus_type = e1000_bus_type_pci;
5457 break;
5458 case e1000_82571:
5459 case e1000_82572:
5460 case e1000_82573:
Roy Zang181119b2011-01-21 11:29:38 +08005461 case e1000_82574:
Roy Zang28f7a052009-07-31 13:34:02 +08005462 case e1000_80003es2lan:
Roy Zang28f7a052009-07-31 13:34:02 +08005463 case e1000_ich8lan:
Marek Vasut74a13c22014-08-08 07:41:39 -07005464 case e1000_igb:
Roy Zang28f7a052009-07-31 13:34:02 +08005465 hw->bus_type = e1000_bus_type_pci_express;
5466 break;
5467 default:
5468 status = E1000_READ_REG(hw, STATUS);
5469 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5470 e1000_bus_type_pcix : e1000_bus_type_pci;
5471 break;
5472 }
5473}
5474
Bin Meng83cf24c2016-02-02 05:58:01 -08005475static int e1000_init_one(struct e1000_hw *hw, int cardnum,
5476 struct udevice *devno, unsigned char enetaddr[6])
Simon Glassc53abc32015-08-19 09:33:39 -06005477{
5478 u32 val;
5479
5480 /* Assign the passed-in values */
Bin Meng83cf24c2016-02-02 05:58:01 -08005481 hw->pdev = devno;
Simon Glassc53abc32015-08-19 09:33:39 -06005482 hw->cardnum = cardnum;
5483
5484 /* Print a debug message with the IO base address */
Bin Meng83cf24c2016-02-02 05:58:01 -08005485 dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
Simon Glassc53abc32015-08-19 09:33:39 -06005486 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5487
5488 /* Try to enable I/O accesses and bus-mastering */
5489 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
Bin Meng83cf24c2016-02-02 05:58:01 -08005490 dm_pci_write_config32(devno, PCI_COMMAND, val);
Simon Glassc53abc32015-08-19 09:33:39 -06005491
5492 /* Make sure it worked */
Bin Meng83cf24c2016-02-02 05:58:01 -08005493 dm_pci_read_config32(devno, PCI_COMMAND, &val);
Simon Glassc53abc32015-08-19 09:33:39 -06005494 if (!(val & PCI_COMMAND_MEMORY)) {
5495 E1000_ERR(hw, "Can't enable I/O memory\n");
5496 return -ENOSPC;
5497 }
5498 if (!(val & PCI_COMMAND_MASTER)) {
5499 E1000_ERR(hw, "Can't enable bus-mastering\n");
5500 return -EPERM;
5501 }
5502
5503 /* Are these variables needed? */
5504 hw->fc = e1000_fc_default;
5505 hw->original_fc = e1000_fc_default;
5506 hw->autoneg_failed = 0;
5507 hw->autoneg = 1;
5508 hw->get_link_status = true;
5509#ifndef CONFIG_E1000_NO_NVM
5510 hw->eeprom_semaphore_present = true;
5511#endif
Andrew Scull58c61022022-04-21 16:11:10 +00005512 hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, 0, 0,
Andrew Scull6520c822022-04-21 16:11:13 +00005513 PCI_REGION_TYPE, PCI_REGION_MEM);
Simon Glassc53abc32015-08-19 09:33:39 -06005514 hw->mac_type = e1000_undefined;
5515
5516 /* MAC and Phy settings */
5517 if (e1000_sw_init(hw) < 0) {
5518 E1000_ERR(hw, "Software init failed\n");
5519 return -EIO;
5520 }
5521 if (e1000_check_phy_reset_block(hw))
5522 E1000_ERR(hw, "PHY Reset is blocked!\n");
5523
5524 /* Basic init was OK, reset the hardware and allow SPI access */
5525 e1000_reset_hw(hw);
5526
5527#ifndef CONFIG_E1000_NO_NVM
5528 /* Validate the EEPROM and get chipset information */
Simon Glassc53abc32015-08-19 09:33:39 -06005529 if (e1000_init_eeprom_params(hw)) {
5530 E1000_ERR(hw, "EEPROM is invalid!\n");
5531 return -EINVAL;
5532 }
5533 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5534 e1000_validate_eeprom_checksum(hw))
5535 return -ENXIO;
Simon Glassc53abc32015-08-19 09:33:39 -06005536 e1000_read_mac_addr(hw, enetaddr);
5537#endif
5538 e1000_get_bus_type(hw);
5539
5540#ifndef CONFIG_E1000_NO_NVM
5541 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5542 enetaddr[0], enetaddr[1], enetaddr[2],
5543 enetaddr[3], enetaddr[4], enetaddr[5]);
5544#else
5545 memset(enetaddr, 0, 6);
5546 printf("e1000: no NVM\n");
5547#endif
5548
5549 return 0;
5550}
5551
5552/* Put the name of a device in a string */
5553static void e1000_name(char *str, int cardnum)
5554{
5555 sprintf(str, "e1000#%u", cardnum);
5556}
5557
Ian Ray9635e2d2020-11-04 17:26:01 +01005558static int e1000_write_hwaddr(struct udevice *dev)
Hannu Lounento68d31f62018-01-10 20:31:26 +01005559{
5560#ifndef CONFIG_E1000_NO_NVM
Hannu Lounento68d31f62018-01-10 20:31:26 +01005561 unsigned char current_mac[6];
Ian Ray9635e2d2020-11-04 17:26:01 +01005562 struct eth_pdata *plat = dev_get_plat(dev);
5563 struct e1000_hw *hw = dev_get_priv(dev);
5564 u8 *mac = plat->enetaddr;
Hannu Lounento68d31f62018-01-10 20:31:26 +01005565 uint16_t data[3];
5566 int ret_val, i;
5567
5568 DEBUGOUT("%s: mac=%pM\n", __func__, mac);
5569
Tim Harvey893bd6e2021-04-16 13:25:09 -07005570 if ((hw->eeprom.type == e1000_eeprom_invm) &&
5571 !(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210))
5572 return -ENOSYS;
5573
Hannu Lounento68d31f62018-01-10 20:31:26 +01005574 memset(current_mac, 0, 6);
5575
5576 /* Read from EEPROM, not from registers, to make sure
5577 * the address is persistently configured
5578 */
5579 ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
5580 DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
5581
5582 /* Only write to EEPROM if the given address is different or
5583 * reading the current address failed
5584 */
5585 if (!ret_val && memcmp(current_mac, mac, 6) == 0)
5586 return 0;
5587
5588 for (i = 0; i < 3; ++i)
5589 data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
5590
5591 ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
5592
5593 if (!ret_val)
5594 ret_val = e1000_update_eeprom_checksum_i210(hw);
5595
5596 return ret_val;
5597#else
5598 return 0;
5599#endif
5600}
Kyle Moffett64b94dd2011-10-18 11:05:29 +00005601
5602#ifdef CONFIG_CMD_E1000
Simon Glassed38aef2020-05-10 11:40:03 -06005603static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
5604 char *const argv[])
Kyle Moffett64b94dd2011-10-18 11:05:29 +00005605{
Simon Glassc53abc32015-08-19 09:33:39 -06005606 unsigned char *mac = NULL;
Simon Glass9f86b382015-08-19 09:33:40 -06005607 struct eth_pdata *plat;
5608 struct udevice *dev;
5609 char name[30];
5610 int ret;
Tom Rini90fc4ba2022-11-27 10:25:09 -05005611#if defined(CONFIG_E1000_SPI)
Kyle Moffett64b94dd2011-10-18 11:05:29 +00005612 struct e1000_hw *hw;
Simon Glass9f86b382015-08-19 09:33:40 -06005613#endif
5614 int cardnum;
Kyle Moffett64b94dd2011-10-18 11:05:29 +00005615
5616 if (argc < 3) {
5617 cmd_usage(cmdtp);
5618 return 1;
5619 }
5620
5621 /* Make sure we can find the requested e1000 card */
Simon Glassff9b9032021-07-24 09:03:30 -06005622 cardnum = dectoul(argv[1], NULL);
Simon Glass9f86b382015-08-19 09:33:40 -06005623 e1000_name(name, cardnum);
5624 ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5625 if (!ret) {
Simon Glassfa20e932020-12-03 16:55:20 -07005626 plat = dev_get_plat(dev);
Simon Glass9f86b382015-08-19 09:33:40 -06005627 mac = plat->enetaddr;
5628 }
Simon Glassc53abc32015-08-19 09:33:39 -06005629 if (!mac) {
Kyle Moffett64b94dd2011-10-18 11:05:29 +00005630 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5631 return 1;
5632 }
5633
5634 if (!strcmp(argv[2], "print-mac-address")) {
Kyle Moffett64b94dd2011-10-18 11:05:29 +00005635 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5636 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5637 return 0;
5638 }
5639
5640#ifdef CONFIG_E1000_SPI
Alban Bedelc1255dd2016-08-03 11:31:03 +02005641 hw = dev_get_priv(dev);
Kyle Moffett64b94dd2011-10-18 11:05:29 +00005642 /* Handle the "SPI" subcommand */
5643 if (!strcmp(argv[2], "spi"))
5644 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5645#endif
5646
5647 cmd_usage(cmdtp);
5648 return 1;
5649}
5650
5651U_BOOT_CMD(
5652 e1000, 7, 0, do_e1000,
5653 "Intel e1000 controller management",
5654 /* */"<card#> print-mac-address\n"
5655#ifdef CONFIG_E1000_SPI
5656 "e1000 <card#> spi show [<offset> [<length>]]\n"
5657 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5658 "e1000 <card#> spi program <addr> <offset> <length>\n"
5659 "e1000 <card#> spi checksum [update]\n"
5660#endif
5661 " - Manage the Intel E1000 PCI device"
5662);
5663#endif /* not CONFIG_CMD_E1000 */
Simon Glass9f86b382015-08-19 09:33:40 -06005664
Simon Glass9f86b382015-08-19 09:33:40 -06005665static int e1000_eth_start(struct udevice *dev)
5666{
Simon Glassfa20e932020-12-03 16:55:20 -07005667 struct eth_pdata *plat = dev_get_plat(dev);
Simon Glass9f86b382015-08-19 09:33:40 -06005668 struct e1000_hw *hw = dev_get_priv(dev);
5669
5670 return _e1000_init(hw, plat->enetaddr);
5671}
5672
5673static void e1000_eth_stop(struct udevice *dev)
5674{
5675 struct e1000_hw *hw = dev_get_priv(dev);
5676
5677 _e1000_disable(hw);
5678}
5679
5680static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5681{
5682 struct e1000_hw *hw = dev_get_priv(dev);
5683 int ret;
5684
5685 ret = _e1000_transmit(hw, packet, length);
5686
5687 return ret ? 0 : -ETIMEDOUT;
5688}
5689
5690static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5691{
5692 struct e1000_hw *hw = dev_get_priv(dev);
5693 int len;
5694
5695 len = _e1000_poll(hw);
5696 if (len)
5697 *packetp = packet;
5698
5699 return len ? len : -EAGAIN;
5700}
5701
5702static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5703{
5704 struct e1000_hw *hw = dev_get_priv(dev);
5705
5706 fill_rx(hw);
5707
5708 return 0;
5709}
5710
5711static int e1000_eth_probe(struct udevice *dev)
5712{
Simon Glassfa20e932020-12-03 16:55:20 -07005713 struct eth_pdata *plat = dev_get_plat(dev);
Simon Glass9f86b382015-08-19 09:33:40 -06005714 struct e1000_hw *hw = dev_get_priv(dev);
5715 int ret;
5716
5717 hw->name = dev->name;
Simon Glasseaa14892015-11-29 13:17:47 -07005718 ret = e1000_init_one(hw, trailing_strtol(dev->name),
Bin Meng83cf24c2016-02-02 05:58:01 -08005719 dev, plat->enetaddr);
Simon Glass9f86b382015-08-19 09:33:40 -06005720 if (ret < 0) {
5721 printf(pr_fmt("failed to initialize card: %d\n"), ret);
5722 return ret;
5723 }
5724
5725 return 0;
5726}
5727
5728static int e1000_eth_bind(struct udevice *dev)
5729{
5730 char name[20];
5731
5732 /*
5733 * A simple way to number the devices. When device tree is used this
5734 * is unnecessary, but when the device is just discovered on the PCI
5735 * bus we need a name. We could instead have the uclass figure out
5736 * which devices are different and number them.
5737 */
5738 e1000_name(name, num_cards++);
5739
5740 return device_set_name(dev, name);
5741}
5742
5743static const struct eth_ops e1000_eth_ops = {
5744 .start = e1000_eth_start,
5745 .send = e1000_eth_send,
5746 .recv = e1000_eth_recv,
5747 .stop = e1000_eth_stop,
5748 .free_pkt = e1000_free_pkt,
Ian Ray9635e2d2020-11-04 17:26:01 +01005749 .write_hwaddr = e1000_write_hwaddr,
Simon Glass9f86b382015-08-19 09:33:40 -06005750};
5751
Simon Glass9f86b382015-08-19 09:33:40 -06005752U_BOOT_DRIVER(eth_e1000) = {
5753 .name = "eth_e1000",
5754 .id = UCLASS_ETH,
Simon Glass9f86b382015-08-19 09:33:40 -06005755 .bind = e1000_eth_bind,
5756 .probe = e1000_eth_probe,
5757 .ops = &e1000_eth_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -07005758 .priv_auto = sizeof(struct e1000_hw),
Simon Glass71fa5b42020-12-03 16:55:18 -07005759 .plat_auto = sizeof(struct eth_pdata),
Simon Glass9f86b382015-08-19 09:33:40 -06005760};
5761
5762U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);