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git01.mediatek.com / filogic / uboot / 035f6bfefd22f98e64c5664acb22e1ffbb45990d / . / configs / phycore-imx8mp_defconfig
blob: 519e0cfb3d4c8c2e119108dfa8d714f70e7ac510 [file] [log] [blame]
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_IMX8M=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]3CONFIG_TEXT_BASE=0x40200000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]4CONFIG_SYS_MALLOC_LEN=0x2000000
Simon Glass035939e2021-07-10 21:14:30 -0600[diff] [blame]5CONFIG_SPL_GPIO=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]6CONFIG_SPL_LIBCOMMON_SUPPORT=y
7CONFIG_SPL_LIBGENERIC_SUPPORT=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]8CONFIG_ENV_SIZE=0x10000
9CONFIG_ENV_OFFSET=0x3C0000
10CONFIG_SYS_I2C_MXC_I2C1=y
11CONFIG_DM_GPIO=y
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]12CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk"
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]13CONFIG_SPL_TEXT_BASE=0x920000
14CONFIG_TARGET_PHYCORE_IMX8MP=y
Teresa Remmetc884afc2023-08-17 10:57:08 +0200[diff] [blame]15CONFIG_PHYTEC_SOM_DETECTION=y
Tom Rini3d2b97c2023-05-29 10:43:26 -0400[diff] [blame]16CONFIG_SYS_MONITOR_LEN=524288
Simon Glassb58bfe02021-08-08 12:20:09 -0600[diff] [blame]17CONFIG_SPL_MMC=y
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]18CONFIG_SPL_SERIAL=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]19CONFIG_SPL_DRIVERS_MISC=y
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]20CONFIG_SPL_STACK=0x960000
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]21CONFIG_SPL=y
22CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]23CONFIG_SYS_LOAD_ADDR=0x40480000
Teresa Remmet5737d332023-06-14 14:36:47 +0200[diff] [blame]24CONFIG_LTO=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]25CONFIG_FIT=y
26CONFIG_FIT_EXTERNAL_OFFSET=0x3000
27CONFIG_SPL_LOAD_FIT=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]28CONFIG_OF_SYSTEM_SETUP=y
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]29CONFIG_USE_BOOTCOMMAND=y
30CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]31CONFIG_DEFAULT_FDT_FILE="oftree"
Tom Rini914a8c02024-01-03 09:26:16 -0500[diff] [blame]32CONFIG_SYS_CBSIZE=2048
33CONFIG_SYS_PBSIZE=2074
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]34CONFIG_BOARD_LATE_INIT=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]35CONFIG_SPL_MAX_SIZE=0x26000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame]36CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
37CONFIG_SPL_BSS_START_ADDR=0x98fc00
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]38CONFIG_SPL_BSS_MAX_SIZE=0x400
Teresa Remmetfe1f1072021-07-07 12:58:01 +0000[diff] [blame]39CONFIG_SPL_BOARD_INIT=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]40CONFIG_SPL_BOOTROM_SUPPORT=y
41CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]42# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Simon Glass67e3fca2023-09-26 08:14:16 -0600[diff] [blame]43CONFIG_SPL_SYS_MALLOC=y
44CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
45CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
46CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]47CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
48CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]49CONFIG_SPL_I2C=y
Simon Glasse91ac4c2021-07-10 21:14:24 -0600[diff] [blame]50CONFIG_SPL_POWER=y
Simon Glass1ba1d4e2021-07-10 21:14:28 -0600[diff] [blame]51CONFIG_SPL_WATCHDOG=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]52CONFIG_HUSH_PARSER=y
Tom Rinic4359852023-10-02 10:35:27 -0400[diff] [blame]53CONFIG_SYS_PROMPT="u-boot=> "
Tom Riniba5c2b02022-05-11 16:21:06 -0400[diff] [blame]54CONFIG_SYS_MAXARGS=64
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]55# CONFIG_CMD_EXPORTENV is not set
56# CONFIG_CMD_IMPORTENV is not set
57# CONFIG_CMD_CRC32 is not set
58CONFIG_CMD_EEPROM=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]59CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
60CONFIG_SYS_EEPROM_SIZE=4096
61CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
62CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]63CONFIG_CMD_CLK=y
64CONFIG_CMD_FUSE=y
65CONFIG_CMD_GPIO=y
66CONFIG_CMD_I2C=y
67CONFIG_CMD_MMC=y
68CONFIG_CMD_DHCP=y
69CONFIG_CMD_MII=y
70CONFIG_CMD_PING=y
71CONFIG_CMD_CACHE=y
72CONFIG_CMD_REGULATOR=y
73CONFIG_CMD_EXT2=y
74CONFIG_CMD_EXT4=y
75CONFIG_CMD_EXT4_WRITE=y
76CONFIG_CMD_FAT=y
77CONFIG_OF_CONTROL=y
78CONFIG_SPL_OF_CONTROL=y
79CONFIG_ENV_OVERWRITE=y
80CONFIG_ENV_IS_IN_MMC=y
81CONFIG_SYS_RELOC_GD_ENV_ADDR=y
82CONFIG_SYS_MMC_ENV_DEV=2
83CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
Teresa Remmet7de60a62021-07-07 12:58:00 +0000[diff] [blame]84CONFIG_NET_RANDOM_ETHADDR=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]85CONFIG_SPL_DM=y
86CONFIG_CLK_COMPOSITE_CCF=y
87CONFIG_CLK_IMX8MP=y
88CONFIG_MXC_GPIO=y
89CONFIG_DM_I2C=y
Igor Opaniuk5f4de782021-02-09 13:52:44 +0200[diff] [blame]90# CONFIG_SPL_DM_I2C is not set
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]91CONFIG_SPL_SYS_I2C_LEGACY=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]92CONFIG_MISC=y
93CONFIG_I2C_EEPROM=y
94CONFIG_SYS_I2C_EEPROM_ADDR=0x51
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]95CONFIG_SUPPORT_EMMC_BOOT=y
96CONFIG_MMC_IO_VOLTAGE=y
97CONFIG_MMC_UHS_SUPPORT=y
98CONFIG_MMC_HS400_ES_SUPPORT=y
99CONFIG_MMC_HS400_SUPPORT=y
Tom Rinid479a9f2021-11-07 22:59:37 -0500[diff] [blame]100CONFIG_FSL_USDHC=y
Teresa Remmet7de60a62021-07-07 12:58:00 +0000[diff] [blame]101CONFIG_PHYLIB=y
102CONFIG_PHY_TI_DP83867=y
Teresa Remmet7de60a62021-07-07 12:58:00 +0000[diff] [blame]103CONFIG_DM_ETH_PHY=y
104CONFIG_FEC_MXC=y
105CONFIG_RGMII=y
106CONFIG_MII=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]107CONFIG_PINCTRL=y
108CONFIG_SPL_PINCTRL=y
109CONFIG_PINCTRL_IMX8M=y
Simon Glass31339412021-08-08 12:20:27 -0600[diff] [blame]110CONFIG_SPL_POWER_LEGACY=y
Tom Rinib2f15962022-12-02 16:42:26 -0500[diff] [blame]111CONFIG_POWER_PCA9450=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]112CONFIG_DM_REGULATOR=y
113CONFIG_DM_REGULATOR_FIXED=y
114CONFIG_DM_REGULATOR_GPIO=y
Simon Glass31339412021-08-08 12:20:27 -0600[diff] [blame]115CONFIG_SPL_POWER_I2C=y
Peng Fan38aeb5f2022-06-11 20:20:58 +0800[diff] [blame]116CONFIG_DM_SERIAL=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]117CONFIG_MXC_UART=y
118CONFIG_SYSRESET=y
119CONFIG_SPL_SYSRESET=y
120CONFIG_SYSRESET_PSCI=y
121CONFIG_SYSRESET_WATCHDOG=y
122CONFIG_DM_THERMAL=y
123CONFIG_IMX_WATCHDOG=y