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git01.mediatek.com / filogic / uboot / 8a14ac4ca6c50dac8ec10b4943dc5a2451741b38 / . / configs / phycore-imx8mp_defconfig
blob: 8d783d30cc32c53186d298d8d5991f5616a26419 [file] [log] [blame]
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_IMX8M=y
3CONFIG_SYS_TEXT_BASE=0x40200000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]4CONFIG_SYS_MALLOC_LEN=0x2000000
Simon Glass035939e2021-07-10 21:14:30 -0600[diff] [blame]5CONFIG_SPL_GPIO=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]6CONFIG_SPL_LIBCOMMON_SUPPORT=y
7CONFIG_SPL_LIBGENERIC_SUPPORT=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]8CONFIG_ENV_SIZE=0x10000
9CONFIG_ENV_OFFSET=0x3C0000
10CONFIG_SYS_I2C_MXC_I2C1=y
11CONFIG_DM_GPIO=y
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]12CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk"
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]13CONFIG_SPL_TEXT_BASE=0x920000
14CONFIG_TARGET_PHYCORE_IMX8MP=y
Simon Glassb58bfe02021-08-08 12:20:09 -0600[diff] [blame]15CONFIG_SPL_MMC=y
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]16CONFIG_SPL_SERIAL=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]17CONFIG_SPL_DRIVERS_MISC=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]18CONFIG_SPL=y
19CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]20CONFIG_SYS_LOAD_ADDR=0x40480000
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]21CONFIG_FIT=y
22CONFIG_FIT_EXTERNAL_OFFSET=0x3000
23CONFIG_SPL_LOAD_FIT=y
Teresa Remmet9acb7012021-07-07 12:58:04 +0000[diff] [blame]24# CONFIG_USE_SPL_FIT_GENERATOR is not set
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]25CONFIG_OF_SYSTEM_SETUP=y
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]26CONFIG_USE_BOOTCOMMAND=y
27CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]28CONFIG_DEFAULT_FDT_FILE="oftree"
29CONFIG_BOARD_LATE_INIT=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]30CONFIG_SPL_MAX_SIZE=0x26000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]31CONFIG_SPL_BSS_MAX_SIZE=0x400
Teresa Remmetfe1f1072021-07-07 12:58:01 +0000[diff] [blame]32CONFIG_SPL_BOARD_INIT=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]33CONFIG_SPL_BOOTROM_SUPPORT=y
34CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame^]35# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
36CONFIG_SPL_STACK=0x960000
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]37CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
38CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]39CONFIG_SPL_I2C=y
Simon Glasse91ac4c2021-07-10 21:14:24 -0600[diff] [blame]40CONFIG_SPL_POWER=y
Simon Glass1ba1d4e2021-07-10 21:14:28 -0600[diff] [blame]41CONFIG_SPL_WATCHDOG=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]42CONFIG_HUSH_PARSER=y
43CONFIG_SYS_PROMPT="u-boot=> "
Tom Riniba5c2b02022-05-11 16:21:06 -0400[diff] [blame]44CONFIG_SYS_MAXARGS=64
Tom Riniae17fa32022-05-11 18:01:06 -0400[diff] [blame]45CONFIG_SYS_CBSIZE=2048
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]46CONFIG_SYS_PBSIZE=2074
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]47# CONFIG_CMD_EXPORTENV is not set
48# CONFIG_CMD_IMPORTENV is not set
49# CONFIG_CMD_CRC32 is not set
50CONFIG_CMD_EEPROM=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]51CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
52CONFIG_SYS_EEPROM_SIZE=4096
53CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
54CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]55CONFIG_CMD_CLK=y
56CONFIG_CMD_FUSE=y
57CONFIG_CMD_GPIO=y
58CONFIG_CMD_I2C=y
59CONFIG_CMD_MMC=y
60CONFIG_CMD_DHCP=y
61CONFIG_CMD_MII=y
62CONFIG_CMD_PING=y
63CONFIG_CMD_CACHE=y
64CONFIG_CMD_REGULATOR=y
65CONFIG_CMD_EXT2=y
66CONFIG_CMD_EXT4=y
67CONFIG_CMD_EXT4_WRITE=y
68CONFIG_CMD_FAT=y
69CONFIG_OF_CONTROL=y
70CONFIG_SPL_OF_CONTROL=y
71CONFIG_ENV_OVERWRITE=y
72CONFIG_ENV_IS_IN_MMC=y
73CONFIG_SYS_RELOC_GD_ENV_ADDR=y
74CONFIG_SYS_MMC_ENV_DEV=2
75CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
Teresa Remmet7de60a62021-07-07 12:58:00 +0000[diff] [blame]76CONFIG_NET_RANDOM_ETHADDR=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]77CONFIG_SPL_DM=y
78CONFIG_CLK_COMPOSITE_CCF=y
79CONFIG_CLK_IMX8MP=y
80CONFIG_MXC_GPIO=y
81CONFIG_DM_I2C=y
Igor Opaniuk5f4de782021-02-09 13:52:44 +0200[diff] [blame]82# CONFIG_SPL_DM_I2C is not set
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]83CONFIG_SPL_SYS_I2C_LEGACY=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]84CONFIG_MISC=y
85CONFIG_I2C_EEPROM=y
86CONFIG_SYS_I2C_EEPROM_ADDR=0x51
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]87CONFIG_SUPPORT_EMMC_BOOT=y
88CONFIG_MMC_IO_VOLTAGE=y
89CONFIG_MMC_UHS_SUPPORT=y
90CONFIG_MMC_HS400_ES_SUPPORT=y
91CONFIG_MMC_HS400_SUPPORT=y
Tom Rinid479a9f2021-11-07 22:59:37 -0500[diff] [blame]92CONFIG_FSL_USDHC=y
Teresa Remmet7de60a62021-07-07 12:58:00 +0000[diff] [blame]93CONFIG_PHYLIB=y
94CONFIG_PHY_TI_DP83867=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]95CONFIG_DM_ETH=y
Teresa Remmet7de60a62021-07-07 12:58:00 +0000[diff] [blame]96CONFIG_DM_ETH_PHY=y
97CONFIG_FEC_MXC=y
98CONFIG_RGMII=y
99CONFIG_MII=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]100CONFIG_PINCTRL=y
101CONFIG_SPL_PINCTRL=y
102CONFIG_PINCTRL_IMX8M=y
Simon Glass31339412021-08-08 12:20:27 -0600[diff] [blame]103CONFIG_SPL_POWER_LEGACY=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]104CONFIG_DM_REGULATOR=y
105CONFIG_DM_REGULATOR_FIXED=y
106CONFIG_DM_REGULATOR_GPIO=y
Simon Glass31339412021-08-08 12:20:27 -0600[diff] [blame]107CONFIG_SPL_POWER_I2C=y
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]108CONFIG_MXC_UART=y
109CONFIG_SYSRESET=y
110CONFIG_SPL_SYSRESET=y
111CONFIG_SYSRESET_PSCI=y
112CONFIG_SYSRESET_WATCHDOG=y
113CONFIG_DM_THERMAL=y
114CONFIG_IMX_WATCHDOG=y