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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Christophe Leroy35982952017-07-07 10:16:42 +02002/*
3 * Copyright (C) 2010-2017 CS Systemes d'Information
4 * Christophe Leroy <christophe.leroy@c-s.fr>
Christophe Leroy35982952017-07-07 10:16:42 +02005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/* High Level Configuration Options */
Christophe Leroy35982952017-07-07 10:16:42 +020011
12#define CONFIG_EXTRA_ENV_SETTINGS \
13 "sdram_type=SDRAM\0" \
14 "flash_type=AM29LV160DB\0" \
15 "loadaddr=0x400000\0" \
16 "filename=uImage.lzma\0" \
17 "nfsroot=/opt/ofs\0" \
18 "dhcp_ip=ip=:::::eth0:dhcp\0" \
19 "console_args=console=ttyCPM0,115200N8\0" \
20 "flashboot=setenv bootargs " \
21 "${console_args} " \
22 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
23 "mcr3k:eth0:off;" \
24 "${ofl_args}; " \
25 "bootm 0x04060000 - 0x04050000\0" \
26 "tftpboot=setenv bootargs " \
27 "${console_args} " \
28 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
29 "mcr3k:eth0:off " \
30 "${ofl_args}; " \
31 "tftp ${loadaddr} ${filename};" \
32 "tftp 0xf00000 mcr3000.dtb;" \
33 "bootm ${loadaddr} - 0xf00000\0" \
34 "netboot=dhcp ${loadaddr} ${filename};" \
35 "tftp 0xf00000 mcr3000.dtb;" \
36 "setenv bootargs " \
37 "root=/dev/nfs rw " \
38 "${console_args} " \
39 "${dhcp_ip};" \
40 "bootm ${loadaddr} - 0xf00000\0" \
41 "nfsboot=setenv bootargs " \
42 "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \
43 "${console_args} " \
44 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
45 "mcr3k:eth0:off;" \
46 "bootm 0x04060000 - 0x04050000\0" \
47 "dhcpboot=dhcp ${loadaddr} ${filename};" \
48 "tftp 0xf00000 mcr3000.dtb;" \
49 "setenv bootargs " \
50 "${console_args} " \
51 "${dhcp_ip} " \
52 "${ofl_args}; " \
53 "bootm ${loadaddr} - 0xf00000\0"
54
Christophe Leroy35982952017-07-07 10:16:42 +020055#define CONFIG_IPADDR 192.168.0.3
56#define CONFIG_SERVERIP 192.168.0.1
57#define CONFIG_NETMASK 255.0.0.0
58
Christophe Leroy35982952017-07-07 10:16:42 +020059#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Christophe Leroy35982952017-07-07 10:16:42 +020060
Christophe Leroy35982952017-07-07 10:16:42 +020061/* Miscellaneous configurable options */
Christophe Leroy35982952017-07-07 10:16:42 +020062
Christophe Leroy35982952017-07-07 10:16:42 +020063#define CONFIG_SYS_MEMTEST_START 0x00002000
64#define CONFIG_SYS_MEMTEST_END 0x00800000
65
66#define CONFIG_SYS_LOAD_ADDR 0x200000
67
68#define CONFIG_SYS_HZ 1000
69
70/* Definitions for initial stack pointer and data area (in DPRAM) */
Christophe Leroyc0857952018-03-16 17:20:51 +010071#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
72#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
Christophe Leroy35982952017-07-07 10:16:42 +020073
74/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
75#define CONFIG_SYS_SDRAM_BASE 0x00000000
Christophe Leroy35982952017-07-07 10:16:42 +020076
77/* FLASH organization */
78#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
Christophe Leroy35982952017-07-07 10:16:42 +020079#define CONFIG_SYS_MAX_FLASH_BANKS 1
80#define CONFIG_SYS_MAX_FLASH_SECT 35
81#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
82#define CONFIG_SYS_FLASH_WRITE_TOUT 500
83
84/*
85 * For booting Linux, the board info and command line data
86 * have to be in the first 8 MB of memory, since this is
87 * the maximum mapped by the Linux kernel during initialization.
88 */
89#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
Christophe Leroy92b792b2018-03-16 17:20:55 +010090#define CONFIG_SYS_MONITOR_LEN (320 << 10)
Christophe Leroy35982952017-07-07 10:16:42 +020091#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
92#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
93
94/* Environment Configuration */
95
96/* environment is in FLASH */
Christophe Leroy92b792b2018-03-16 17:20:55 +010097#define CONFIG_ENV_SECT_SIZE 0x2000
98#define CONFIG_ENV_OFFSET 0x4000
Christophe Leroy35982952017-07-07 10:16:42 +020099#define CONFIG_ENV_OVERWRITE 1
100
Christophe Leroy35982952017-07-07 10:16:42 +0200101/* Ethernet configuration part */
102#define CONFIG_SYS_DISCOVER_PHY 1
Christophe Leroy35982952017-07-07 10:16:42 +0200103#define CONFIG_MII_INIT 1
Christophe Leroy35982952017-07-07 10:16:42 +0200104
105/* NAND configuration part */
106#define CONFIG_SYS_MAX_NAND_DEVICE 1
107#define CONFIG_SYS_NAND_MAX_CHIPS 1
108#define CONFIG_SYS_NAND_BASE 0x0C000000
109
Christophe Leroy35982952017-07-07 10:16:42 +0200110#endif /* __CONFIG_H */