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Christophe Leroy35982952017-07-07 10:16:42 +02001/*
2 * Copyright (C) 2010-2017 CS Systemes d'Information
3 * Christophe Leroy <christophe.leroy@c-s.fr>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/* High Level Configuration Options */
Christophe Leroy35982952017-07-07 10:16:42 +020012#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
13
14#define CONFIG_EXTRA_ENV_SETTINGS \
15 "sdram_type=SDRAM\0" \
16 "flash_type=AM29LV160DB\0" \
17 "loadaddr=0x400000\0" \
18 "filename=uImage.lzma\0" \
19 "nfsroot=/opt/ofs\0" \
20 "dhcp_ip=ip=:::::eth0:dhcp\0" \
21 "console_args=console=ttyCPM0,115200N8\0" \
22 "flashboot=setenv bootargs " \
23 "${console_args} " \
24 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
25 "mcr3k:eth0:off;" \
26 "${ofl_args}; " \
27 "bootm 0x04060000 - 0x04050000\0" \
28 "tftpboot=setenv bootargs " \
29 "${console_args} " \
30 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
31 "mcr3k:eth0:off " \
32 "${ofl_args}; " \
33 "tftp ${loadaddr} ${filename};" \
34 "tftp 0xf00000 mcr3000.dtb;" \
35 "bootm ${loadaddr} - 0xf00000\0" \
36 "netboot=dhcp ${loadaddr} ${filename};" \
37 "tftp 0xf00000 mcr3000.dtb;" \
38 "setenv bootargs " \
39 "root=/dev/nfs rw " \
40 "${console_args} " \
41 "${dhcp_ip};" \
42 "bootm ${loadaddr} - 0xf00000\0" \
43 "nfsboot=setenv bootargs " \
44 "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \
45 "${console_args} " \
46 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
47 "mcr3k:eth0:off;" \
48 "bootm 0x04060000 - 0x04050000\0" \
49 "dhcpboot=dhcp ${loadaddr} ${filename};" \
50 "tftp 0xf00000 mcr3000.dtb;" \
51 "setenv bootargs " \
52 "${console_args} " \
53 "${dhcp_ip} " \
54 "${ofl_args}; " \
55 "bootm ${loadaddr} - 0xf00000\0"
56
Christophe Leroy35982952017-07-07 10:16:42 +020057#define CONFIG_IPADDR 192.168.0.3
58#define CONFIG_SERVERIP 192.168.0.1
59#define CONFIG_NETMASK 255.0.0.0
60
Christophe Leroy35982952017-07-07 10:16:42 +020061#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Christophe Leroy35982952017-07-07 10:16:42 +020062
63#define CONFIG_WATCHDOG 1 /* watchdog enabled */
64
65/* Miscellaneous configurable options */
Christophe Leroy35982952017-07-07 10:16:42 +020066
Christophe Leroy35982952017-07-07 10:16:42 +020067#define CONFIG_SYS_MEMTEST_START 0x00002000
68#define CONFIG_SYS_MEMTEST_END 0x00800000
69
70#define CONFIG_SYS_LOAD_ADDR 0x200000
71
72#define CONFIG_SYS_HZ 1000
73
74/* Definitions for initial stack pointer and data area (in DPRAM) */
Christophe Leroyc0857952018-03-16 17:20:51 +010075#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
76#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
Christophe Leroy35982952017-07-07 10:16:42 +020077
78/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
79#define CONFIG_SYS_SDRAM_BASE 0x00000000
Christophe Leroy35982952017-07-07 10:16:42 +020080
81/* FLASH organization */
82#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
83#define CONFIG_SYS_FLASH_CFI 1
84#define CONFIG_FLASH_CFI_DRIVER 1
85#define CONFIG_SYS_MAX_FLASH_BANKS 1
86#define CONFIG_SYS_MAX_FLASH_SECT 35
87#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
88#define CONFIG_SYS_FLASH_WRITE_TOUT 500
89
90/*
91 * For booting Linux, the board info and command line data
92 * have to be in the first 8 MB of memory, since this is
93 * the maximum mapped by the Linux kernel during initialization.
94 */
95#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
Christophe Leroy92b792b2018-03-16 17:20:55 +010096#define CONFIG_SYS_MONITOR_LEN (320 << 10)
Christophe Leroy35982952017-07-07 10:16:42 +020097#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
98#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
99
100/* Environment Configuration */
101
102/* environment is in FLASH */
Christophe Leroy92b792b2018-03-16 17:20:55 +0100103#define CONFIG_ENV_SECT_SIZE 0x2000
104#define CONFIG_ENV_OFFSET 0x4000
Christophe Leroy35982952017-07-07 10:16:42 +0200105#define CONFIG_ENV_OVERWRITE 1
106
Christophe Leroy35982952017-07-07 10:16:42 +0200107/* Ethernet configuration part */
108#define CONFIG_SYS_DISCOVER_PHY 1
Christophe Leroy35982952017-07-07 10:16:42 +0200109#define CONFIG_MII_INIT 1
Christophe Leroy35982952017-07-07 10:16:42 +0200110
111/* NAND configuration part */
112#define CONFIG_SYS_MAX_NAND_DEVICE 1
113#define CONFIG_SYS_NAND_MAX_CHIPS 1
114#define CONFIG_SYS_NAND_BASE 0x0C000000
115
Christophe Leroy35982952017-07-07 10:16:42 +0200116#endif /* __CONFIG_H */