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Enric Balletbò i Serra458d6032013-12-06 21:30:23 +01001/*
2 * ti_omap3_common.h
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * For more details, please see the technical documents listed at
9 * http://www.ti.com/product/omap3530
10 * http://www.ti.com/product/omap3630
11 * http://www.ti.com/product/dm3730
12 */
13
14#ifndef __CONFIG_TI_OMAP3_COMMON_H__
15#define __CONFIG_TI_OMAP3_COMMON_H__
16
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010017
18#include <asm/arch/cpu.h>
Nishanth Menonfa96c962015-03-09 17:12:04 -050019#include <asm/arch/omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010020
Nishanth Menon3e46e3e2015-03-09 17:12:08 -050021/* Common ARM Erratas */
22#define CONFIG_ARM_ERRATA_454179
23#define CONFIG_ARM_ERRATA_430973
24#define CONFIG_ARM_ERRATA_621766
25
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010026/* The chip has SDRC controller */
27#define CONFIG_SDRC
28
29/* Clock Defines */
30#define V_OSCK 26000000 /* Clock output from T2 */
31#define V_SCLK (V_OSCK >> 1)
32
33/* NS16550 Configuration */
34#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
35#define CONFIG_SYS_NS16550
Thomas Chou52ac4432015-11-19 21:48:12 +080036#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Simon Glassbc0f4ea2014-10-22 21:37:15 -060037#ifdef CONFIG_SPL_BUILD
38# define CONFIG_SYS_NS16550_SERIAL
39# define CONFIG_SYS_NS16550_REG_SIZE (-4)
Simon Glassbc0f4ea2014-10-22 21:37:15 -060040#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010041#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
42 115200}
43
44/* Select serial console configuration */
45#define CONFIG_CONS_INDEX 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -060046#ifdef CONFIG_SPL_BUILD
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010047#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
48#define CONFIG_SERIAL3 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -060049#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010050
51/* Physical Memory Map */
52#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
53#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
54
55/*
56 * OMAP3 has 12 GP timers, they can be driven by the system clock
57 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
58 * This rate is divided by a local divisor.
59 */
60#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
61
62#define CONFIG_SYS_MONITOR_LEN (256 << 10)
63
64/* TWL4030 */
Igor Grinberg48b034a2015-10-08 21:12:25 +030065#define CONFIG_TWL4030_POWER
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010066
67/* SPL */
68#define CONFIG_SPL_TEXT_BASE 0x40200800
69#define CONFIG_SPL_MAX_SIZE (54 * 1024)
70#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
71#define CONFIG_SPL_POWER_SUPPORT
Tom Rinid9f808d2014-04-03 07:52:53 -040072#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
73 (64 << 20))
74
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010075
76#ifdef CONFIG_NAND
77#define CONFIG_SPL_NAND_SUPPORT
78#define CONFIG_SPL_NAND_SIMPLE
Tom Rinie10247f2014-04-03 15:17:15 -040079#define CONFIG_SYS_NAND_BASE 0x30000000
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010080#endif
81
82/* Now bring in the rest of the common code. */
Nishanth Menonad63dd72015-07-22 18:05:41 -050083#include <configs/ti_armv7_omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +010084
85#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */