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Tom Warrena3e280b2011-01-27 10:58:07 +00001/*
Tom Warrenc570d7a2012-05-22 12:19:25 +00002 * (C) Copyright 2010-2012
Tom Warrena3e280b2011-01-27 10:58:07 +00003 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Allen Martin55d98a12012-08-31 08:30:00 +000024#ifndef __TEGRA20_COMMON_H
25#define __TEGRA20_COMMON_H
Tom Warrena3e280b2011-01-27 10:58:07 +000026#include <asm/sizes.h>
Marek Vasut1b476f92012-09-23 17:41:25 +020027#include <linux/stringify.h>
Tom Warrena3e280b2011-01-27 10:58:07 +000028
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
Allen Martin55d98a12012-08-31 08:30:00 +000033#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
Allen Martin04e38f42012-08-31 08:30:02 +000034#define CONFIG_TEGRA /* which is a Tegra generic machine */
Aneesh Vecee9c82011-06-16 23:30:48 +000035#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
Tom Warrena3e280b2011-01-27 10:58:07 +000036
Anton staaf5420cba2011-10-03 13:54:58 +000037#define CONFIG_SYS_CACHELINE_SIZE 32
38
Tom Warrenab371962012-09-19 15:50:56 -070039#include <asm/arch/tegra.h> /* get chip and board defs */
Tom Warrena3e280b2011-01-27 10:58:07 +000040
41/*
42 * Display CPU and Board information
43 */
44#define CONFIG_DISPLAY_CPUINFO
45#define CONFIG_DISPLAY_BOARDINFO
46
Tom Warrena3e280b2011-01-27 10:58:07 +000047#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Grant Likely100b8492011-03-28 09:59:07 +000048#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
Tom Warrena3e280b2011-01-27 10:58:07 +000049
Tom Warren22562a42012-09-04 17:00:24 -070050#ifdef CONFIG_TEGRA_LP0
Simon Glassef2fb1a2012-04-02 13:19:03 +000051#define TEGRA_LP0_ADDR 0x1C406000
52#define TEGRA_LP0_SIZE 0x2000
53#define TEGRA_LP0_VEC \
Marek Vasut1b476f92012-09-23 17:41:25 +020054 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
55 "@" __stringify(TEGRA_LP0_ADDR) " "
Simon Glassef2fb1a2012-04-02 13:19:03 +000056#else
57#define TEGRA_LP0_VEC
58#endif
59
Tom Warrena3e280b2011-01-27 10:58:07 +000060/* Environment */
Stephen Warren018a34c2012-05-22 09:21:55 +000061#define CONFIG_ENV_VARS_UBOOT_CONFIG
Simon Glass4e61a342011-11-05 04:46:48 +000062#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
Tom Warrena3e280b2011-01-27 10:58:07 +000063
64/*
65 * Size of malloc() pool
66 */
67#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
68
69/*
70 * PllX Configuration
71 */
72#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
73
74/*
75 * NS16550 Configuration
76 */
77#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
78
79#define CONFIG_SYS_NS16550
80#define CONFIG_SYS_NS16550_SERIAL
81#define CONFIG_SYS_NS16550_REG_SIZE (-4)
82#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
83
84/*
85 * select serial console configuration
86 */
87#define CONFIG_CONS_INDEX 1
88
89/* allow to overwrite serial and ethaddr */
90#define CONFIG_ENV_OVERWRITE
91#define CONFIG_BAUDRATE 115200
92#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
93 115200}
94
Simon Glass9d580862012-02-27 10:52:51 +000095/*
96 * This parameter affects a TXFILLTUNING field that controls how much data is
97 * sent to the latency fifo before it is sent to the wire. Without this
98 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
99 * packets depending on the buffer address and size.
100 */
101#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
102#define CONFIG_EHCI_IS_TDI
Simon Glass9d580862012-02-27 10:52:51 +0000103
Allen Martin55d98a12012-08-31 08:30:00 +0000104/* Total I2C ports on Tegra20 */
Simon Glassaac60882012-02-03 15:13:59 +0000105#define TEGRA_I2C_NUM_CONTROLLERS 4
106
Tom Warrena3e280b2011-01-27 10:58:07 +0000107/* include default commands */
108#include <config_cmd_default.h>
Stephen Warren91623dd2012-09-25 13:32:26 +0000109#define CONFIG_PARTITION_UUIDS
110#define CONFIG_CMD_PART
Tom Warrena3e280b2011-01-27 10:58:07 +0000111
112/* remove unused commands */
113#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
114#undef CONFIG_CMD_FPGA /* FPGA configuration support */
115#undef CONFIG_CMD_IMI
116#undef CONFIG_CMD_IMLS
117#undef CONFIG_CMD_NFS /* NFS support */
118#undef CONFIG_CMD_NET /* network support */
119
120/* turn on command-line edit/hist/auto */
121#define CONFIG_CMDLINE_EDITING
122#define CONFIG_COMMAND_HISTORY
Mike Frysingerc1285cb2011-10-26 00:19:58 +0000123#define CONFIG_AUTO_COMPLETE
Tom Warrena3e280b2011-01-27 10:58:07 +0000124
125#define CONFIG_SYS_NO_FLASH
126
Simon Glassa32d33d2012-04-17 09:01:36 +0000127#define CONFIG_CONSOLE_MUX
128#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Simon Glassa32d33d2012-04-17 09:01:36 +0000129
Tom Warrena3e280b2011-01-27 10:58:07 +0000130#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
131#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
132
133/*
134 * Miscellaneous configurable options
135 */
136#define CONFIG_SYS_LONGHELP /* undef to save memory */
137#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Tom Warrena3e280b2011-01-27 10:58:07 +0000138#define CONFIG_SYS_PROMPT V_PROMPT
139/*
140 * Increasing the size of the IO buffer as default nfsargs size is more
141 * than 256 and so it is not possible to edit it
142 */
143#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
144/* Print Buffer Size */
145#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
146 sizeof(CONFIG_SYS_PROMPT) + 16)
147#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
148/* Boot Argument Buffer Size */
149#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
150
Tom Warren22562a42012-09-04 17:00:24 -0700151#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
Tom Warrena3e280b2011-01-27 10:58:07 +0000152#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
153
154#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
155#define CONFIG_SYS_HZ 1000
156
Tom Warrena3e280b2011-01-27 10:58:07 +0000157#define CONFIG_STACKBASE 0x2800000 /* 40MB */
Tom Warrena3e280b2011-01-27 10:58:07 +0000158
159/*-----------------------------------------------------------------------
160 * Physical Memory Map
161 */
162#define CONFIG_NR_DRAM_BANKS 1
Tom Warren22562a42012-09-04 17:00:24 -0700163#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
Tom Warrena3e280b2011-01-27 10:58:07 +0000164#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
165
Allen Martinc9c98462012-08-31 08:30:12 +0000166#define CONFIG_SYS_TEXT_BASE 0x0010c000
Allen Martin36ea6272012-10-19 21:08:23 +0000167#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
Tom Warrena3e280b2011-01-27 10:58:07 +0000168#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
169
Stephen Warren875508c2012-09-20 09:29:03 +0000170#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
171
Tom Warrena3e280b2011-01-27 10:58:07 +0000172#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
173#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
174#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
175 CONFIG_SYS_INIT_RAM_SIZE - \
176 GENERATED_GBL_DATA_SIZE)
177
Tom Warrenc570d7a2012-05-22 12:19:25 +0000178#define CONFIG_TEGRA_GPIO
Tom Warren6e3806b2011-06-17 06:27:29 +0000179#define CONFIG_CMD_GPIO
Stephen Warren3c7643c2012-06-04 09:23:55 +0000180#define CONFIG_CMD_ENTERRCM
Stephen Warrenaf4c9e42012-06-13 09:55:11 +0000181#define CONFIG_CMD_BOOTZ
Allen Martinc9c98462012-08-31 08:30:12 +0000182
183/* Defines for SPL */
184#define CONFIG_SPL
Allen Martin36ea6272012-10-19 21:08:23 +0000185#define CONFIG_SPL_FRAMEWORK
186#define CONFIG_SPL_RAM_DEVICE
187#define CONFIG_SPL_BOARD_INIT
Allen Martinc9c98462012-08-31 08:30:12 +0000188#define CONFIG_SPL_NAND_SIMPLE
189#define CONFIG_SPL_TEXT_BASE 0x00108000
Stephen Warrend889e8a2012-10-22 06:19:34 +0000190#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
191 CONFIG_SPL_TEXT_BASE)
Allen Martinc9c98462012-08-31 08:30:12 +0000192#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
193#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
194#define CONFIG_SPL_STACK 0x000ffffc
195
196#define CONFIG_SPL_LIBCOMMON_SUPPORT
197#define CONFIG_SPL_LIBGENERIC_SUPPORT
198#define CONFIG_SPL_SERIAL_SUPPORT
199#define CONFIG_SPL_GPIO_SUPPORT
200#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
201
Simon Glassbad90ee2012-07-29 20:53:30 +0000202#define CONFIG_SYS_NAND_SELF_INIT
Lucas Stach8a538552012-10-07 11:29:38 +0000203#define CONFIG_SYS_NAND_ONFI_DETECTION
Simon Glassbad90ee2012-07-29 20:53:30 +0000204
Stephen Warrenf227e452012-11-06 11:27:30 +0000205/* Misc utility code */
206#define CONFIG_BOUNCE_BUFFER
207
Allen Martin55d98a12012-08-31 08:30:00 +0000208#endif /* __TEGRA20_COMMON_H */