blob: ef376847a35eac9c89e96548f54bb0aaa36c19ad [file] [log] [blame]
developerf8871e82023-03-08 17:22:32 +08001From 764731bb9676e58e8819bdbe48719b1076625032 Mon Sep 17 00:00:00 2001
developeraace7f52022-06-24 13:40:42 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Wed, 22 Jun 2022 10:39:47 +0800
developerf8871e82023-03-08 17:22:32 +08004Subject: [PATCH 1001/1009] mt76: mt7915: add mtk internal debug tools for mt76
developer3fa816c2022-04-19 10:21:20 +08005
6---
developerf3f5d9b2023-02-07 15:24:34 +08007 mt76_connac_mcu.h | 6 +
developer27b55252022-09-05 19:09:45 +08008 mt7915/Makefile | 2 +-
9 mt7915/debugfs.c | 73 +-
10 mt7915/mac.c | 14 +
11 mt7915/main.c | 4 +
developerf3f5d9b2023-02-07 15:24:34 +080012 mt7915/mcu.c | 48 +-
developer27b55252022-09-05 19:09:45 +080013 mt7915/mcu.h | 4 +
developer5eddc512023-02-13 16:01:56 +080014 mt7915/mt7915.h | 43 +
developer79a21a22023-01-09 13:57:39 +080015 mt7915/mt7915_debug.h | 1363 +++++++++++++++++++
16 mt7915/mtk_debugfs.c | 3003 +++++++++++++++++++++++++++++++++++++++++
developer27b55252022-09-05 19:09:45 +080017 mt7915/mtk_mcu.c | 51 +
18 tools/fwlog.c | 44 +-
developer5eddc512023-02-13 16:01:56 +080019 12 files changed, 4641 insertions(+), 14 deletions(-)
developer27b55252022-09-05 19:09:45 +080020 create mode 100644 mt7915/mt7915_debug.h
21 create mode 100644 mt7915/mtk_debugfs.c
22 create mode 100644 mt7915/mtk_mcu.c
developer3fa816c2022-04-19 10:21:20 +080023
24diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developerf8871e82023-03-08 17:22:32 +080025index 40a99e0c..312e7b3c 100644
developer3fa816c2022-04-19 10:21:20 +080026--- a/mt76_connac_mcu.h
27+++ b/mt76_connac_mcu.h
developerf8871e82023-03-08 17:22:32 +080028@@ -1148,6 +1148,7 @@ enum {
developer9e5bcc52022-09-27 10:30:15 +080029 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
30 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
31 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
32+ MCU_EXT_CMD_MEC_CTRL = 0x1f,
33 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
34 MCU_EXT_CMD_THERMAL_PROT = 0x23,
35 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
developerf8871e82023-03-08 17:22:32 +080036@@ -1171,6 +1172,11 @@ enum {
developer3fa816c2022-04-19 10:21:20 +080037 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
38 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
39 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
40+#ifdef MTK_DEBUG
developer3fa816c2022-04-19 10:21:20 +080041+ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
42+ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
43+ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
44+#endif
45 MCU_EXT_CMD_TXDPD_CAL = 0x60,
46 MCU_EXT_CMD_CAL_CACHE = 0x67,
developerf3f5d9b2023-02-07 15:24:34 +080047 MCU_EXT_CMD_RED_ENABLE = 0x68,
developer3fa816c2022-04-19 10:21:20 +080048diff --git a/mt7915/Makefile b/mt7915/Makefile
developerb8853042023-02-17 11:50:45 +080049index f033116c..cbcb64be 100644
developer3fa816c2022-04-19 10:21:20 +080050--- a/mt7915/Makefile
51+++ b/mt7915/Makefile
developerf3f5d9b2023-02-07 15:24:34 +080052@@ -4,7 +4,7 @@ EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
developer3fa816c2022-04-19 10:21:20 +080053 obj-$(CONFIG_MT7915E) += mt7915e.o
54
55 mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
56- debugfs.o mmio.o
57+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
58
59 mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
60 mt7915e-$(CONFIG_MT7986_WMAC) += soc.o
developer3fa816c2022-04-19 10:21:20 +080061diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
developerb8853042023-02-17 11:50:45 +080062index 5a46813a..f1f3f2f3 100644
developer3fa816c2022-04-19 10:21:20 +080063--- a/mt7915/debugfs.c
64+++ b/mt7915/debugfs.c
65@@ -8,6 +8,9 @@
66 #include "mac.h"
67
68 #define FW_BIN_LOG_MAGIC 0x44e98caf
69+#ifdef MTK_DEBUG
70+#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
71+#endif
72
73 /** global debugfs **/
74
developer2cbf2fb2022-11-16 12:20:48 +080075@@ -504,6 +507,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080076 int ret;
77
developer42b63282022-06-16 13:33:13 +080078 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
developer3fa816c2022-04-19 10:21:20 +080079+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +080080+ dev->fw.debug_wm = val;
developer3fa816c2022-04-19 10:21:20 +080081+#endif
82
developer42b63282022-06-16 13:33:13 +080083 if (dev->fw.debug_bin)
developer3fa816c2022-04-19 10:21:20 +080084 val = 16;
developer2cbf2fb2022-11-16 12:20:48 +080085@@ -528,6 +534,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080086 if (ret)
developer42b63282022-06-16 13:33:13 +080087 goto out;
developer3fa816c2022-04-19 10:21:20 +080088 }
89+#ifdef MTK_DEBUG
90+ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
91+#endif
92
93 /* WM CPU info record control */
94 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
developer2cbf2fb2022-11-16 12:20:48 +080095@@ -535,6 +544,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080096 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
97 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
98
99+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800100+ if (dev->fw.debug_bin & BIT(3))
developer3fa816c2022-04-19 10:21:20 +0800101+ /* use bit 7 to indicate v2 magic number */
developer42b63282022-06-16 13:33:13 +0800102+ dev->fw.debug_wm |= BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800103+#endif
104+
developer42b63282022-06-16 13:33:13 +0800105 out:
106 if (ret)
107 dev->fw.debug_wm = 0;
developer2cbf2fb2022-11-16 12:20:48 +0800108@@ -547,7 +562,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
developer3fa816c2022-04-19 10:21:20 +0800109 {
110 struct mt7915_dev *dev = data;
111
developer42b63282022-06-16 13:33:13 +0800112- *val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800113+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800114+ *val = dev->fw.debug_wm & ~BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800115+#else
developer42b63282022-06-16 13:33:13 +0800116+ val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800117+#endif
118
119 return 0;
120 }
developer2cbf2fb2022-11-16 12:20:48 +0800121@@ -632,6 +651,17 @@ mt7915_fw_debug_bin_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +0800122
123 relay_reset(dev->relay_fwlog);
124
125+#ifdef MTK_DEBUG
126+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
127+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
128+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
129+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
130+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
131+ if (!(val & GENMASK(3, 0)))
132+ return 0;
133+#endif
134+
developer42b63282022-06-16 13:33:13 +0800135+
136 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm);
developer3fa816c2022-04-19 10:21:20 +0800137 }
138
developer2458e702022-12-13 15:52:04 +0800139@@ -1257,6 +1287,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
developer3fa816c2022-04-19 10:21:20 +0800140 if (!ext_phy)
141 dev->debugfs_dir = dir;
142
143+#ifdef MTK_DEBUG
144+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
145+ mt7915_mtk_init_debugfs(phy, dir);
146+#endif
147+
148 return 0;
149 }
150
developer2458e702022-12-13 15:52:04 +0800151@@ -1297,17 +1332,53 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
developer3fa816c2022-04-19 10:21:20 +0800152 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
153 };
154
155+#ifdef MTK_DEBUG
156+ struct {
157+ __le32 magic;
158+ u8 version;
159+ u8 _rsv;
160+ __le16 serial_id;
161+ __le32 timestamp;
162+ __le16 msg_type;
163+ __le16 len;
164+ } hdr2 = {
165+ .version = 0x1,
166+ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
167+ .msg_type = PKT_TYPE_RX_FW_MONITOR,
168+ };
169+#endif
170+
171 if (!dev->relay_fwlog)
172 return;
173
174+#ifdef MTK_DEBUG
175+ /* old magic num */
developer42b63282022-06-16 13:33:13 +0800176+ if (!(dev->fw.debug_wm & BIT(7))) {
developer3fa816c2022-04-19 10:21:20 +0800177+ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
178+ hdr.len = *(__le16 *)data;
179+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
180+ } else {
181+ hdr2.serial_id = dev->dbg.fwlog_seq++;
182+ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
183+ hdr2.len = *(__le16 *)data;
184+ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
185+ }
186+#else
187 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
188 hdr.len = *(__le16 *)data;
189 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
190+#endif
191 }
192
193 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
194 {
195+#ifdef MTK_DEBUG
196+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
197+ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2 &&
198+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
199+#else
200 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
201+#endif
202 return false;
203
204 if (dev->relay_fwlog)
205diff --git a/mt7915/mac.c b/mt7915/mac.c
developerb8853042023-02-17 11:50:45 +0800206index 97ca55d2..1ba4096d 100644
developer3fa816c2022-04-19 10:21:20 +0800207--- a/mt7915/mac.c
208+++ b/mt7915/mac.c
developerf3f5d9b2023-02-07 15:24:34 +0800209@@ -299,6 +299,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800210 __le16 fc = 0;
211 int idx;
212
213+#ifdef MTK_DEBUG
214+ if (dev->dbg.dump_rx_raw)
215+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
216+#endif
217 memset(status, 0, sizeof(*status));
218
developer2458e702022-12-13 15:52:04 +0800219 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) {
developerf3f5d9b2023-02-07 15:24:34 +0800220@@ -482,6 +486,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800221 }
222
223 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
224+#ifdef MTK_DEBUG
225+ if (dev->dbg.dump_rx_pkt)
226+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
227+#endif
228 if (hdr_trans && ieee80211_has_morefrags(fc)) {
developeraace7f52022-06-24 13:40:42 +0800229 struct ieee80211_vif *vif;
230 int err;
developerf3f5d9b2023-02-07 15:24:34 +0800231@@ -819,6 +827,12 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer3fa816c2022-04-19 10:21:20 +0800232 tx_info->buf[1].skip_unmap = true;
233 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
234
235+#ifdef MTK_DEBUG
236+ if (dev->dbg.dump_txd)
237+ mt7915_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
238+ if (dev->dbg.dump_tx_pkt)
239+ mt7915_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
240+#endif
241 return 0;
242 }
243
developeraace7f52022-06-24 13:40:42 +0800244diff --git a/mt7915/main.c b/mt7915/main.c
developerb8853042023-02-17 11:50:45 +0800245index 3bbccbdf..94ecded5 100644
developeraace7f52022-06-24 13:40:42 +0800246--- a/mt7915/main.c
247+++ b/mt7915/main.c
developer2aa1e642022-12-19 11:33:22 +0800248@@ -73,7 +73,11 @@ int mt7915_run(struct ieee80211_hw *hw)
developeraace7f52022-06-24 13:40:42 +0800249 if (ret)
250 goto out;
251
252+#ifdef MTK_DEBUG
253+ ret = mt7915_mcu_set_sku_en(phy, !dev->dbg.sku_disable);
254+#else
255 ret = mt7915_mcu_set_sku_en(phy, true);
256+#endif
257 if (ret)
258 goto out;
259
developer3fa816c2022-04-19 10:21:20 +0800260diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developerf8871e82023-03-08 17:22:32 +0800261index d08907f5..1fecd4b1 100644
developer3fa816c2022-04-19 10:21:20 +0800262--- a/mt7915/mcu.c
263+++ b/mt7915/mcu.c
developer3d5faf22022-11-29 18:07:22 +0800264@@ -199,6 +199,11 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
developeraace7f52022-06-24 13:40:42 +0800265 else
266 qid = MT_MCUQ_WM;
developer3fa816c2022-04-19 10:21:20 +0800267
developer3fa816c2022-04-19 10:21:20 +0800268+#ifdef MTK_DEBUG
269+ if (dev->dbg.dump_mcu_pkt)
270+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
271+#endif
developeraace7f52022-06-24 13:40:42 +0800272+
273 return mt76_tx_queue_skb_raw(dev, mdev->q_mcu[qid], skb, 0);
274 }
275
developerf3f5d9b2023-02-07 15:24:34 +0800276@@ -2315,7 +2320,10 @@ static int mt7915_red_set_watermark(struct mt7915_dev *dev)
277 sizeof(req), false);
278 }
279
280-static int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
281+#ifndef MTK_DEBUG
282+static
283+#endif
284+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
285 {
286 #define RED_DISABLE 0
287 #define RED_BY_WA_ENABLE 2
developerf8871e82023-03-08 17:22:32 +0800288@@ -3379,6 +3387,8 @@ int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable)
developeraace7f52022-06-24 13:40:42 +0800289 .sku_enable = enable,
290 };
developer3fa816c2022-04-19 10:21:20 +0800291
developeraace7f52022-06-24 13:40:42 +0800292+ pr_info("%s: enable = %d\n", __func__, enable);
293+
294 return mt76_mcu_send_msg(&dev->mt76,
295 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
296 sizeof(req), true);
developerf8871e82023-03-08 17:22:32 +0800297@@ -3816,6 +3826,23 @@ int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
developer3fa816c2022-04-19 10:21:20 +0800298 &req, sizeof(req), true);
299 }
developer1eeb8e82022-05-03 14:10:10 +0800300
developer3fa816c2022-04-19 10:21:20 +0800301+#ifdef MTK_DEBUG
302+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
303+{
304+ struct {
305+ __le32 args[3];
306+ } req = {
307+ .args = {
308+ cpu_to_le32(a1),
309+ cpu_to_le32(a2),
310+ cpu_to_le32(a3),
311+ },
312+ };
313+
314+ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
315+}
developer3fa816c2022-04-19 10:21:20 +0800316+#endif
developer1eeb8e82022-05-03 14:10:10 +0800317+
318 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
319 {
320 struct {
developerf8871e82023-03-08 17:22:32 +0800321@@ -3844,3 +3871,22 @@ int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
developer9e5bcc52022-09-27 10:30:15 +0800322
323 return 0;
324 }
325+
326+#ifdef MTK_DEBUG
327+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable)
328+{
329+ struct {
330+ u16 action;
331+ u8 _rsv1[2];
332+ u16 wcid;
333+ u8 enable;
334+ u8 _rsv2[5];
335+ } __packed req = {
336+ .action = cpu_to_le16(1),
337+ .wcid = cpu_to_le16(wcid),
338+ .enable = enable,
339+ };
340+
341+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MEC_CTRL), &req, sizeof(req), true);
342+}
343+#endif
developer3fa816c2022-04-19 10:21:20 +0800344diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developerb8853042023-02-17 11:50:45 +0800345index b9ea297f..da863601 100644
developer3fa816c2022-04-19 10:21:20 +0800346--- a/mt7915/mcu.h
347+++ b/mt7915/mcu.h
developer2458e702022-12-13 15:52:04 +0800348@@ -278,6 +278,10 @@ enum {
developer3fa816c2022-04-19 10:21:20 +0800349 MCU_WA_PARAM_PDMA_RX = 0x04,
350 MCU_WA_PARAM_CPU_UTIL = 0x0b,
351 MCU_WA_PARAM_RED = 0x0e,
352+#ifdef MTK_DEBUG
353+ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
354+ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
355+#endif
developerf3f5d9b2023-02-07 15:24:34 +0800356 MCU_WA_PARAM_RED_SETTING = 0x40,
developer3fa816c2022-04-19 10:21:20 +0800357 };
358
developer3fa816c2022-04-19 10:21:20 +0800359diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerb8853042023-02-17 11:50:45 +0800360index 3cbfb9b6..5fcc8ace 100644
developer3fa816c2022-04-19 10:21:20 +0800361--- a/mt7915/mt7915.h
362+++ b/mt7915/mt7915.h
363@@ -9,6 +9,7 @@
364 #include "../mt76_connac.h"
365 #include "regs.h"
366
367+#define MTK_DEBUG 1
368 #define MT7915_MAX_INTERFACES 19
developer3fa816c2022-04-19 10:21:20 +0800369 #define MT7915_WTBL_SIZE 288
developeraace7f52022-06-24 13:40:42 +0800370 #define MT7916_WTBL_SIZE 544
developer5eddc512023-02-13 16:01:56 +0800371@@ -373,6 +374,28 @@ struct mt7915_dev {
developer3fa816c2022-04-19 10:21:20 +0800372 struct reset_control *rstc;
373 void __iomem *dcm;
374 void __iomem *sku;
375+
376+#ifdef MTK_DEBUG
377+ u16 wlan_idx;
378+ struct {
379+ u32 fixed_rate;
380+ u32 l1debugfs_reg;
381+ u32 l2debugfs_reg;
382+ u32 mac_reg;
383+ u32 fw_dbg_module;
384+ u8 fw_dbg_lv;
385+ u32 bcn_total_cnt[2];
386+ u16 fwlog_seq;
387+ bool dump_mcu_pkt;
388+ bool dump_txd;
389+ bool dump_tx_pkt;
390+ bool dump_rx_pkt;
391+ bool dump_rx_raw;
392+ u32 token_idx;
developeraace7f52022-06-24 13:40:42 +0800393+ u8 sku_disable;
developer3fa816c2022-04-19 10:21:20 +0800394+ } dbg;
395+ const struct mt7915_dbg_reg_desc *dbg_reg;
396+#endif
397 };
398
399 enum {
developer5eddc512023-02-13 16:01:56 +0800400@@ -651,4 +674,24 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerf1313102022-10-11 11:02:55 +0800401 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
402 bool pci, int *irq);
developer3fa816c2022-04-19 10:21:20 +0800403
404+#ifdef MTK_DEBUG
405+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
406+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
407+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
408+void mt7915_dump_tmac_info(u8 *tmac_info);
409+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
410+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len);
developer9e5bcc52022-09-27 10:30:15 +0800411+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable);
developer3fa816c2022-04-19 10:21:20 +0800412+
413+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
414+enum {
415+ PKT_BIN_DEBUG_MCU,
416+ PKT_BIN_DEBUG_TXD,
417+ PKT_BIN_DEBUG_TX,
418+ PKT_BIN_DEBUG_RX,
419+ PKT_BIN_DEBUG_RX_RAW,
420+};
421+
422+#endif
423+
424 #endif
425diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
426new file mode 100644
developerb8853042023-02-17 11:50:45 +0800427index 00000000..ca553dca
developer3fa816c2022-04-19 10:21:20 +0800428--- /dev/null
429+++ b/mt7915/mt7915_debug.h
developer79a21a22023-01-09 13:57:39 +0800430@@ -0,0 +1,1363 @@
developer3fa816c2022-04-19 10:21:20 +0800431+#ifndef __MT7915_DEBUG_H
432+#define __MT7915_DEBUG_H
433+
434+#ifdef MTK_DEBUG
435+
436+#define DBG_INVALID_BASE 0xffffffff
437+#define DBG_INVALID_OFFSET 0x0
438+
439+struct __dbg_map {
440+ u32 phys;
441+ u32 maps;
442+ u32 size;
443+};
444+
445+struct __dbg_reg {
446+ u32 base;
447+ u32 offs;
448+};
449+
450+struct __dbg_mask {
451+ u32 end;
452+ u32 start;
453+};
454+
455+enum dbg_base_rev {
456+ MT_DBG_WFDMA0_BASE,
457+ MT_DBG_WFDMA1_BASE,
458+ MT_DBG_WFDMA0_PCIE1_BASE,
459+ MT_DBG_WFDMA1_PCIE1_BASE,
460+ MT_DBG_WFDMA_EXT_CSR_BASE,
461+ MT_DBG_SWDEF_BASE,
462+ __MT_DBG_BASE_REV_MAX,
463+};
464+
465+enum dbg_reg_rev {
466+ DBG_INT_SOURCE_CSR,
467+ DBG_INT_MASK_CSR,
468+ DBG_INT1_SOURCE_CSR,
469+ DBG_INT1_MASK_CSR,
470+ DBG_TX_RING_BASE,
471+ DBG_RX_EVENT_RING_BASE,
472+ DBG_RX_STS_RING_BASE,
473+ DBG_RX_DATA_RING_BASE,
474+ DBG_DMA_ICSC_FR0,
475+ DBG_DMA_ICSC_FR1,
476+ DBG_TMAC_ICSCR0,
477+ DBG_RMAC_RXICSRPT,
478+ DBG_MIB_M0SDR0,
479+ DBG_MIB_M0SDR3,
480+ DBG_MIB_M0SDR4,
481+ DBG_MIB_M0SDR5,
482+ DBG_MIB_M0SDR7,
483+ DBG_MIB_M0SDR8,
484+ DBG_MIB_M0SDR9,
485+ DBG_MIB_M0SDR10,
486+ DBG_MIB_M0SDR11,
487+ DBG_MIB_M0SDR12,
488+ DBG_MIB_M0SDR14,
489+ DBG_MIB_M0SDR15,
490+ DBG_MIB_M0SDR16,
491+ DBG_MIB_M0SDR17,
492+ DBG_MIB_M0SDR18,
493+ DBG_MIB_M0SDR19,
494+ DBG_MIB_M0SDR20,
495+ DBG_MIB_M0SDR21,
496+ DBG_MIB_M0SDR22,
497+ DBG_MIB_M0SDR23,
498+ DBG_MIB_M0DR0,
499+ DBG_MIB_M0DR1,
500+ DBG_MIB_MUBF,
501+ DBG_MIB_M0DR6,
502+ DBG_MIB_M0DR7,
503+ DBG_MIB_M0DR8,
504+ DBG_MIB_M0DR9,
505+ DBG_MIB_M0DR10,
506+ DBG_MIB_M0DR11,
507+ DBG_MIB_M0DR12,
508+ DBG_WTBLON_WDUCR,
509+ DBG_UWTBL_WDUCR,
510+ DBG_PLE_DRR_TABLE_CTRL,
511+ DBG_PLE_DRR_TABLE_RDATA,
512+ DBG_PLE_PBUF_CTRL,
513+ DBG_PLE_QUEUE_EMPTY,
514+ DBG_PLE_FREEPG_CNT,
515+ DBG_PLE_FREEPG_HEAD_TAIL,
516+ DBG_PLE_PG_HIF_GROUP,
517+ DBG_PLE_HIF_PG_INFO,
518+ DBG_PLE_PG_HIF_TXCMD_GROUP,
519+ DBG_PLE_HIF_TXCMD_PG_INFO,
520+ DBG_PLE_PG_CPU_GROUP,
521+ DBG_PLE_CPU_PG_INFO,
522+ DBG_PLE_FL_QUE_CTRL,
523+ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
524+ DBG_PLE_TXCMD_Q_EMPTY,
525+ DBG_PLE_AC_QEMPTY,
526+ DBG_PLE_AC_OFFSET,
527+ DBG_PLE_STATION_PAUSE,
528+ DBG_PLE_DIS_STA_MAP,
529+ DBG_PSE_PBUF_CTRL,
530+ DBG_PSE_FREEPG_CNT,
531+ DBG_PSE_FREEPG_HEAD_TAIL,
532+ DBG_PSE_HIF0_PG_INFO,
533+ DBG_PSE_PG_HIF1_GROUP,
534+ DBG_PSE_HIF1_PG_INFO,
535+ DBG_PSE_PG_CPU_GROUP,
536+ DBG_PSE_CPU_PG_INFO,
537+ DBG_PSE_PG_PLE_GROUP,
538+ DBG_PSE_PLE_PG_INFO,
539+ DBG_PSE_PG_LMAC0_GROUP,
540+ DBG_PSE_LMAC0_PG_INFO,
541+ DBG_PSE_PG_LMAC1_GROUP,
542+ DBG_PSE_LMAC1_PG_INFO,
543+ DBG_PSE_PG_LMAC2_GROUP,
544+ DBG_PSE_LMAC2_PG_INFO,
545+ DBG_PSE_PG_LMAC3_GROUP,
546+ DBG_PSE_LMAC3_PG_INFO,
547+ DBG_PSE_PG_MDP_GROUP,
548+ DBG_PSE_MDP_PG_INFO,
549+ DBG_PSE_PG_PLE1_GROUP,
550+ DBG_PSE_PLE1_PG_INFO,
551+ DBG_AGG_AALCR0,
552+ DBG_AGG_AALCR1,
553+ DBG_AGG_AALCR2,
554+ DBG_AGG_AALCR3,
555+ DBG_AGG_AALCR4,
556+ DBG_AGG_B0BRR0,
557+ DBG_AGG_B1BRR0,
558+ DBG_AGG_B2BRR0,
559+ DBG_AGG_B3BRR0,
560+ DBG_AGG_AWSCR0,
561+ DBG_AGG_PCR0,
562+ DBG_AGG_TTCR0,
563+ DBG_MIB_M0ARNG0,
564+ DBG_MIB_M0DR2,
565+ DBG_MIB_M0DR13,
developer79a21a22023-01-09 13:57:39 +0800566+ DBG_WFDMA_WED_TX_CTRL,
567+ DBG_WFDMA_WED_RX_CTRL,
developer3fa816c2022-04-19 10:21:20 +0800568+ __MT_DBG_REG_REV_MAX,
569+};
570+
571+enum dbg_mask_rev {
572+ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
573+ DBG_MIB_M0SDR14_AMPDU,
574+ DBG_MIB_M0SDR15_AMPDU_ACKED,
575+ DBG_MIB_RX_FCS_ERROR_COUNT,
576+ __MT_DBG_MASK_REV_MAX,
577+};
578+
579+enum dbg_bit_rev {
580+ __MT_DBG_BIT_REV_MAX,
581+};
582+
583+static const u32 mt7915_dbg_base[] = {
584+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
585+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
586+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
587+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
588+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
589+ [MT_DBG_SWDEF_BASE] = 0x41f200,
590+};
591+
592+static const u32 mt7916_dbg_base[] = {
593+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
594+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
595+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
596+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
597+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
598+ [MT_DBG_SWDEF_BASE] = 0x411400,
599+};
600+
601+static const u32 mt7986_dbg_base[] = {
602+ [MT_DBG_WFDMA0_BASE] = 0x24000,
603+ [MT_DBG_WFDMA1_BASE] = 0x25000,
604+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
605+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
606+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
607+ [MT_DBG_SWDEF_BASE] = 0x411400,
608+};
609+
610+/* mt7915 regs with different base and offset */
611+static const struct __dbg_reg mt7915_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800612+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
613+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800614+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
615+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
616+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
617+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
618+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
619+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
620+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
621+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
622+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
623+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
624+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
625+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
626+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
627+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
628+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
629+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
630+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
631+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
632+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
633+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
634+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
635+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
636+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
637+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
638+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
639+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
640+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
641+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
642+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
643+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
644+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
645+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
646+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
647+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
648+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
649+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
650+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
651+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
652+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
653+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
654+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
655+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
656+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
657+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
658+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
659+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
660+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
661+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
662+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
663+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
664+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
665+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
666+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
667+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
668+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
669+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
670+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
671+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
672+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
673+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
674+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
675+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
676+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
developerf32dabf2022-06-01 10:59:24 +0800677+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
developer3fa816c2022-04-19 10:21:20 +0800678+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
679+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
680+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
681+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
682+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
683+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
684+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
685+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
686+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
687+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
688+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
689+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
690+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
691+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
692+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
693+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
694+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
695+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
696+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
697+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
698+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
699+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
700+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
701+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
702+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
703+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
704+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
705+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
706+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
707+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
708+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
709+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
710+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
711+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
712+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
713+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
714+};
715+
716+/* mt7986/mt7916 regs with different base and offset */
717+static const struct __dbg_reg mt7916_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800718+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
719+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800720+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
721+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
722+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
723+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
724+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
725+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
726+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
727+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
728+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
729+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
730+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
731+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
732+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
733+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
734+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
735+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
736+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
737+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
738+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
739+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
740+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
741+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
742+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
743+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
744+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
745+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
746+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
747+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
748+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
749+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
750+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
751+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
752+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
753+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
754+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
755+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
756+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
757+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
758+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
759+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
760+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
761+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
762+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
763+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
764+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
765+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
766+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
767+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
768+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
769+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
770+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
771+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
772+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
773+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
774+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
775+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
776+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
777+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
developerf32dabf2022-06-01 10:59:24 +0800778+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x36c},
developer3fa816c2022-04-19 10:21:20 +0800779+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
780+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
781+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
782+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
783+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
784+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
785+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
786+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
787+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
788+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
789+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
790+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
791+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
792+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
793+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
794+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
795+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
796+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
797+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
798+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
799+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
800+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
801+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
802+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
803+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
804+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
805+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
806+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
807+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
808+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
809+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
810+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
811+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
812+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
813+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
814+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
815+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
816+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
817+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
818+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
819+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
820+};
821+
822+static const struct __dbg_mask mt7915_dbg_mask[] = {
823+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
824+ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
825+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
826+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
827+};
828+
829+static const struct __dbg_mask mt7916_dbg_mask[] = {
830+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
831+ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
832+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
833+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
834+};
835+
836+/* used to differentiate between generations */
837+struct mt7915_dbg_reg_desc {
838+ const u32 id;
839+ const u32 *base_rev;
840+ const struct __dbg_reg *reg_rev;
841+ const struct __dbg_mask *mask_rev;
842+};
843+
844+static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
845+ { 0x7915,
846+ mt7915_dbg_base,
847+ mt7915_dbg_reg,
848+ mt7915_dbg_mask
849+ },
850+ { 0x7906,
851+ mt7916_dbg_base,
852+ mt7916_dbg_reg,
853+ mt7916_dbg_mask
854+ },
855+ { 0x7986,
856+ mt7986_dbg_base,
857+ mt7916_dbg_reg,
858+ mt7916_dbg_mask
859+ },
860+};
861+
862+struct bin_debug_hdr {
863+ __le32 magic_num;
864+ __le16 serial_id;
865+ __le16 msg_type;
866+ __le16 len;
867+ __le16 des_len; /* descriptor len for rxd */
868+} __packed;
869+
870+#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
871+#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
872+#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
873+
874+#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
875+ (_dev)->dbg_reg->mask_rev[(id)].start)
876+#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
877+ __DBG_REG_OFFS((_dev), (id)))
878+
879+#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
880+ dev->dbg_reg->mask_rev[(id)].start)
881+#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
882+ __DBG_MASK(dev, (id)))
883+
884+
885+#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
886+#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
887+#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
888+#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
developer79a21a22023-01-09 13:57:39 +0800889+#define MT_DBG_WFDMA_WED_TX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_TX_CTRL)
890+#define MT_DBG_WFDMA_WED_RX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_RX_CTRL)
developer3fa816c2022-04-19 10:21:20 +0800891+
892+#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
893+#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
894+#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
895+
developer79a21a22023-01-09 13:57:39 +0800896+#define MT_DBG_WFDMA_WED_TX_CTRL(n) (MT_DBG_WFDMA_WED_TX_CTRL_BASE + (0x10 * (n)))
897+#define MT_DBG_WFDMA_WED_RX_CTRL(n) (MT_DBG_WFDMA_WED_RX_CTRL_BASE + (0x10 * (n)))
developer3fa816c2022-04-19 10:21:20 +0800898+/* WFDMA COMMON */
899+#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
900+#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
901+#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
902+#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
903+
904+/* WFDMA0 */
905+#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
906+
907+#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
908+#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
909+
910+#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
911+#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
912+#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
913+#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
914+#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
915+
916+
917+/* WFDMA1 */
918+#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
919+#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
920+#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
921+
922+#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
923+
924+#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
925+#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
926+#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
927+#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
928+
929+/* WFDMA0 PCIE1 */
930+#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
931+
932+#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
933+#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
934+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
935+#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
936+
937+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
938+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
939+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
940+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
941+
942+/* WFDMA1 PCIE1 */
943+#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
944+#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
945+#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
946+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
947+#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
948+#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
949+
950+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
951+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
952+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
953+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
954+
955+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
956+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
957+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
958+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
959+
960+
961+/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
962+#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
963+#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
964+
965+#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
966+#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
967+#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
968+
969+#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
970+#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
971+#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
972+#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
973+#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
974+#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
975+
976+#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
977+#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
978+#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
979+
980+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
981+#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
982+#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
983+
984+#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
985+#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
986+
987+/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
988+#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
989+#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
990+
991+#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
992+#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
993+
994+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
995+#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
996+#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
997+
998+
999+#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
1000+#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
1001+
1002+#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
1003+#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
1004+#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
1005+#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
1006+#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
1007+#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
1008+#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
1009+#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
1010+#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
1011+#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
1012+#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
1013+#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
1014+
1015+#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
1016+
1017+#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
1018+#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
1019+#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
1020+#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
1021+#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
1022+#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
1023+#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
1024+#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
1025+#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
1026+#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
1027+#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
1028+#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
1029+#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
1030+#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
1031+
1032+#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
1033+#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
1034+#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
1035+#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
1036+#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
1037+#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
1038+#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
1039+ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
1040+
1041+/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
1042+#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
1043+#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
1044+#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
1045+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
1046+
1047+#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
1048+#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
1049+#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
1050+#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
1051+#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
1052+#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
1053+#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
1054+#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
1055+#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
1056+#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
1057+
1058+#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
1059+
1060+/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
1061+#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
1062+#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
1063+
developerf1313102022-10-11 11:02:55 +08001064+#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_UWTBL_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
developer3fa816c2022-04-19 10:21:20 +08001065+
1066+#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
1067+#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
1068+
1069+
1070+/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
1071+#define MT_DBG_WTBL_BASE 0x820D8000
1072+
1073+/* PLE related CRs. */
1074+#define MT_DBG_PLE_BASE 0x820C0000
1075+#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
1076+
1077+#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
1078+#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
1079+
1080+#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
1081+#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
1082+#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
1083+#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
1084+#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
1085+#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
1086+#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
1087+#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
1088+
1089+#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
1090+#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
1091+#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
1092+#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
1093+#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
1094+#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
1095+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
1096+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
1097+#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
1098+#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
1099+#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
1100+#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
1101+#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
1102+#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
1103+#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
1104+#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
1105+#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
1106+
1107+#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
1108+#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
1109+#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1110+
1111+#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1112+#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1113+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1114+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1115+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
1116+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
1117+
1118+#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
1119+#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
1120+
1121+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
1122+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
1123+
1124+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1125+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1126+
1127+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1128+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1129+
1130+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1131+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1132+
1133+#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1134+#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1135+
1136+#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
1137+#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
1138+#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
1139+
1140+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
1141+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
1142+
1143+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
1144+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
1145+#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
1146+
1147+#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
1148+#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
1149+#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
1150+ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
1151+
1152+#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
1153+
1154+/* pseinfo related CRs. */
1155+#define MT_DBG_PSE_BASE 0x820C8000
1156+#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
1157+
developerf32dabf2022-06-01 10:59:24 +08001158+#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
1159+#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PSE(0x0b0)
1160+#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
1161+#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
1162+#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PSE(0x110)
1163+#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
1164+#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
1165+#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
1166+#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
1167+#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
1168+#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
1169+#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
1170+#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
1171+#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
1172+#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
1173+#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
1174+#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
1175+#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
1176+#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
1177+#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
1178+#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
1179+#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
1180+#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
1181+#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
developer3fa816c2022-04-19 10:21:20 +08001182+
1183+#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
1184+#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
1185+#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1186+#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
1187+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
1188+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
1189+#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
1190+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
1191+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
1192+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
1193+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
1194+#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
1195+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
1196+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
1197+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
1198+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
1199+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
1200+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
1201+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
1202+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
1203+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
1204+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
1205+#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1206+#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1207+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1208+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1209+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1210+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1211+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1212+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1213+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
1214+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
1215+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
1216+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
1217+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
1218+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
1219+#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1220+#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1221+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
1222+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
1223+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1224+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1225+#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
1226+#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
1227+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
1228+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
1229+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
1230+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
1231+#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
1232+#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
1233+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
1234+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
1235+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
1236+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
1237+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
1238+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
1239+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1240+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1241+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
1242+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
1243+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1244+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1245+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
1246+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
1247+#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
1248+#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
1249+
1250+#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
1251+#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
1252+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
1253+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
1254+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
1255+
1256+#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
1257+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
1258+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
1259+
1260+#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
1261+#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
1262+
1263+
1264+/* AGG */
1265+#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
1266+#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
1267+
1268+#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
1269+#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
1270+#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
1271+#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
1272+#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
1273+#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
1274+#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
1275+#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
1276+#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
1277+#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
1278+#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
1279+#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
1280+#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
1281+#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
1282+#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
1283+
1284+#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
1285+#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
1286+#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
1287+#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
1288+#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
1289+
1290+#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
1291+#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
1292+#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
1293+#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
1294+
1295+#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
1296+#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
1297+#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
1298+#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
1299+
1300+#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
1301+#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
1302+#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
1303+#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
1304+
1305+#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
1306+#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
1307+#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
1308+
1309+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
1310+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
1311+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
1312+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
1313+
1314+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
1315+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
1316+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
1317+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
1318+
1319+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
1320+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
1321+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
1322+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
1323+
1324+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
1325+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
1326+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
1327+
1328+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
1329+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
1330+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
1331+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
1332+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
1333+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
1334+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
1335+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
1336+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
1337+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
1338+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
1339+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
1340+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
1341+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
1342+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
1343+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
1344+
1345+/* mt7915 host DMA*/
1346+#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
1347+#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
1348+#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
1349+
1350+#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
1351+#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
1352+#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
1353+#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
1354+#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
1355+
1356+#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
1357+#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
1358+
1359+/* mt7986 host DMA */
1360+#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
1361+#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
1362+#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
1363+#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
1364+#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
1365+#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
1366+
1367+#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
1368+#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
1369+#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
1370+#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
1371+#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
1372+
1373+/* MCU DMA */
1374+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1375+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1376+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1377+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1378+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1379+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1380+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1381+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1382+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1383+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1384+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1385+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1386+
1387+#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
1388+#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
1389+#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
1390+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
1391+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1392+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1393+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1394+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1395+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1396+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1397+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1398+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1399+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
1400+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
1401+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
1402+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
1403+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
1404+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
1405+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
1406+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
1407+
1408+#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
1409+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
1410+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
1411+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
1412+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1413+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1414+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1415+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1416+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1417+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1418+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1419+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1420+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
1421+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
1422+
1423+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1424+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1425+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1426+/* mt7986 add */
1427+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1428+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1429+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1430+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1431+
1432+
1433+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1434+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1435+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1436+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1437+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1438+
1439+/* mt7986 add */
1440+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1441+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1442+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1443+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1444+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1445+
1446+/* MEM DMA */
1447+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1448+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1449+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1450+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1451+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1452+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1453+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1454+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1455+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1456+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1457+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1458+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1459+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1460+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1461+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1462+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1463+
1464+enum resource_attr {
1465+ HIF_TX_DATA,
1466+ HIF_TX_CMD,
1467+ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
1468+ HIF_TX_FWDL,
1469+ HIF_RX_DATA,
1470+ HIF_RX_EVENT,
1471+ RING_ATTR_NUM
1472+};
1473+
1474+struct hif_pci_tx_ring_desc {
1475+ u32 hw_int_mask;
1476+ u16 ring_size;
1477+ enum resource_attr ring_attr;
1478+ u8 band_idx;
1479+ char *const ring_info;
1480+};
1481+
1482+struct hif_pci_rx_ring_desc {
1483+ u32 hw_desc_base;
1484+ u32 hw_int_mask;
1485+ u16 ring_size;
1486+ enum resource_attr ring_attr;
1487+ u16 max_rx_process_cnt;
1488+ u16 max_sw_read_idx_inc;
1489+ char *const ring_info;
developer79a21a22023-01-09 13:57:39 +08001490+ bool flags;
developer3fa816c2022-04-19 10:21:20 +08001491+};
1492+
1493+const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
1494+ {
1495+ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
1496+ .ring_size = 128,
1497+ .ring_attr = HIF_TX_FWDL,
1498+ .ring_info = "FWDL"
1499+ },
1500+ {
1501+ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
1502+ .ring_size = 256,
1503+ .ring_attr = HIF_TX_CMD_WM,
1504+ .ring_info = "cmd to WM"
1505+ },
1506+ {
1507+ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
1508+ .ring_size = 2048,
1509+ .ring_attr = HIF_TX_DATA,
1510+ .ring_info = "band0 TXD"
1511+ },
1512+ {
1513+ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
1514+ .ring_size = 2048,
1515+ .ring_attr = HIF_TX_DATA,
1516+ .ring_info = "band1 TXD"
1517+ },
1518+ {
1519+ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
1520+ .ring_size = 256,
1521+ .ring_attr = HIF_TX_CMD,
1522+ .ring_info = "cmd to WA"
1523+ }
1524+};
1525+
1526+const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
1527+ {
1528+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
1529+ .ring_size = 1536,
1530+ .ring_attr = HIF_RX_DATA,
1531+ .ring_info = "band0 RX data"
1532+ },
1533+ {
1534+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
1535+ .ring_size = 1536,
1536+ .ring_attr = HIF_RX_DATA,
1537+ .ring_info = "band1 RX data"
1538+ },
1539+ {
1540+ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
1541+ .ring_size = 512,
1542+ .ring_attr = HIF_RX_EVENT,
1543+ .ring_info = "event from WM"
1544+ },
1545+ {
1546+ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
1547+ .ring_size = 1024,
1548+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001549+ .ring_info = "event from WA band0",
1550+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001551+ },
1552+ {
1553+ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
1554+ .ring_size = 512,
1555+ .ring_attr = HIF_RX_EVENT,
1556+ .ring_info = "event from WA band1"
1557+ }
1558+};
1559+
1560+const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
1561+ {
1562+ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
1563+ .ring_size = 128,
1564+ .ring_attr = HIF_TX_FWDL,
1565+ .ring_info = "FWDL"
1566+ },
1567+ {
1568+ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
1569+ .ring_size = 256,
1570+ .ring_attr = HIF_TX_CMD_WM,
1571+ .ring_info = "cmd to WM"
1572+ },
1573+ {
1574+ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
1575+ .ring_size = 2048,
1576+ .ring_attr = HIF_TX_DATA,
1577+ .ring_info = "band0 TXD"
1578+ },
1579+ {
1580+ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
1581+ .ring_size = 2048,
1582+ .ring_attr = HIF_TX_DATA,
1583+ .ring_info = "band1 TXD"
1584+ },
1585+ {
1586+ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
1587+ .ring_size = 256,
1588+ .ring_attr = HIF_TX_CMD,
1589+ .ring_info = "cmd to WA"
1590+ }
1591+};
1592+
1593+const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
1594+ {
1595+ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
1596+ .ring_size = 1536,
1597+ .ring_attr = HIF_RX_DATA,
1598+ .ring_info = "band0 RX data"
1599+ },
1600+ {
1601+ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
1602+ .ring_size = 1536,
1603+ .ring_attr = HIF_RX_DATA,
1604+ .ring_info = "band1 RX data"
1605+ },
1606+ {
1607+ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
1608+ .ring_size = 512,
1609+ .ring_attr = HIF_RX_EVENT,
1610+ .ring_info = "event from WM"
1611+ },
1612+ {
1613+ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
1614+ .ring_size = 512,
1615+ .ring_attr = HIF_RX_EVENT,
1616+ .ring_info = "event from WA"
1617+ },
1618+ {
1619+ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
1620+ .ring_size = 1024,
1621+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001622+ .ring_info = "STS WA band0",
1623+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001624+ },
1625+ {
1626+ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
1627+ .ring_size = 512,
1628+ .ring_attr = HIF_RX_EVENT,
1629+ .ring_info = "STS WA band1"
1630+ },
1631+};
1632+
1633+/* mibinfo related CRs. */
1634+#define BN0_WF_MIB_TOP_BASE 0x820ed000
1635+#define BN1_WF_MIB_TOP_BASE 0x820fd000
1636+
1637+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1638+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
1639+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
1640+
1641+#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
1642+#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
1643+
1644+#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
1645+#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
1646+#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
1647+#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
1648+#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
1649+
1650+#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
1651+#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1652+#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
1653+
1654+#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
1655+
1656+#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
1657+
1658+#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1659+
1660+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1661+
1662+#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
1663+
1664+#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
1665+#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
1666+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1667+
1668+#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
1669+
1670+#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
1671+#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
1672+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1673+#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
1674+#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
1675+#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
1676+
1677+#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
1678+#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
1679+
1680+#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
1681+
1682+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
1683+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
1684+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
1685+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
1686+
1687+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
1688+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
1689+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
1690+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
1691+
1692+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
1693+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
1694+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
1695+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
1696+
1697+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
1698+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
1699+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
1700+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
1701+
1702+#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
1703+
1704+#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
1705+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
1706+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
1707+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
1708+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
1709+#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
1710+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
1711+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
1712+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
1713+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
1714+#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
1715+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
1716+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
1717+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
1718+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
1719+#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
1720+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
1721+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
1722+#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
1723+
1724+
1725+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
1726+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
1727+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
1728+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
1729+
1730+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
1731+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
1732+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
1733+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
1734+
1735+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
1736+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
1737+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
1738+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
1739+
1740+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
1741+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
1742+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
1743+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
1744+
1745+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
1746+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
1747+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
1748+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
1749+
1750+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
1751+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
1752+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
1753+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
1754+
1755+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
1756+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
1757+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
1758+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
1759+
1760+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
1761+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
1762+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
1763+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
1764+
1765+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
1766+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
1767+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
1768+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
1769+
1770+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
1771+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
1772+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
1773+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
1774+
1775+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
1776+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
1777+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
1778+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
1779+/* TXD */
1780+
1781+#define MT_TXD1_ETYP BIT(15)
1782+#define MT_TXD1_VLAN BIT(14)
1783+#define MT_TXD1_RMVL BIT(13)
1784+#define MT_TXD1_AMS BIT(13)
1785+#define MT_TXD1_EOSP BIT(12)
1786+#define MT_TXD1_MRD BIT(11)
1787+
1788+#define MT_TXD7_CTXD BIT(26)
1789+#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
1790+#define MT_TXD7_TAT GENMASK(9, 0)
1791+
1792+#endif
1793+#endif
1794diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
1795new file mode 100644
developerb8853042023-02-17 11:50:45 +08001796index 00000000..530bde1a
developer3fa816c2022-04-19 10:21:20 +08001797--- /dev/null
1798+++ b/mt7915/mtk_debugfs.c
developer79a21a22023-01-09 13:57:39 +08001799@@ -0,0 +1,3003 @@
developer3fa816c2022-04-19 10:21:20 +08001800+#include<linux/inet.h>
1801+#include "mt7915.h"
1802+#include "mt7915_debug.h"
1803+#include "mac.h"
1804+#include "mcu.h"
1805+
1806+#ifdef MTK_DEBUG
1807+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1808+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1809+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1810+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1811+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1812+
1813+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1814+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1815+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1816+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1817+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1818+
1819+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1820+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1821+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1822+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1823+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1824+
1825+enum mt7915_wtbl_type {
1826+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1827+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1828+ WTBL_TYPE_KEY, /* Key Table */
1829+ MAX_NUM_WTBL_TYPE
1830+};
1831+
1832+static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
1833+ enum mt7915_wtbl_type type, u16 start_dw,
1834+ u16 len, void *buf)
1835+{
1836+ u32 *dest_cpy = (u32 *)buf;
1837+ u32 size_dw = len;
1838+ u32 src = 0;
1839+
1840+ if (!buf)
1841+ return 0xFF;
1842+
1843+ if (type == WTBL_TYPE_LMAC) {
1844+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1845+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1846+ src = LWTBL_IDX2BASE(idx, start_dw);
1847+ } else if (type == WTBL_TYPE_UMAC) {
1848+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1849+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1850+ src = UWTBL_IDX2BASE(idx, start_dw);
1851+ } else if (type == WTBL_TYPE_KEY) {
1852+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1853+ MT_UWTBL_TOP_WDUCR_TARGET |
1854+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1855+ src = KEYTBL_IDX2BASE(idx, start_dw);
1856+ }
1857+
1858+ while (size_dw--) {
1859+ *dest_cpy++ = mt76_rr(dev, src);
1860+ src += 4;
1861+ };
1862+
1863+ return 0;
1864+}
1865+
1866+static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
1867+ enum mt7915_wtbl_type type, u16 start_dw,
1868+ u32 val)
1869+{
1870+ u32 addr = 0;
1871+
1872+ if (type == WTBL_TYPE_LMAC) {
1873+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1874+ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1875+ addr = LWTBL_IDX2BASE(idx, start_dw);
1876+ } else if (type == WTBL_TYPE_UMAC) {
1877+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1878+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1879+ addr = UWTBL_IDX2BASE(idx, start_dw);
1880+ } else if (type == WTBL_TYPE_KEY) {
1881+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1882+ MT_UWTBL_TOP_WDUCR_TARGET |
1883+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1884+ addr = KEYTBL_IDX2BASE(idx, start_dw);
1885+ }
1886+
1887+ mt76_wr(dev, addr, val);
1888+
1889+ return 0;
1890+}
1891+
1892+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len)
1893+{
1894+ struct bin_debug_hdr *hdr;
1895+ char *buf;
1896+
1897+ if (len > 1500 - sizeof(*hdr))
1898+ len = 1500 - sizeof(*hdr);
1899+
1900+ buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL);
1901+ if (!buf)
1902+ return;
1903+
1904+ hdr = (struct bin_debug_hdr *)buf;
1905+ hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC);
1906+ hdr->serial_id = cpu_to_le16(dev->dbg.fwlog_seq++);
1907+ hdr->msg_type = cpu_to_le16(type);
1908+ hdr->len = cpu_to_le16(len);
1909+ hdr->des_len = cpu_to_le16(des_len);
1910+
1911+ memcpy(buf + sizeof(*hdr), data, len);
1912+
1913+ mt7915_debugfs_rx_log(dev, buf, sizeof(*hdr) + len);
1914+}
1915+
1916+static int
1917+mt7915_fw_debug_module_set(void *data, u64 module)
1918+{
1919+ struct mt7915_dev *dev = data;
1920+
1921+ dev->dbg.fw_dbg_module = module;
1922+ return 0;
1923+}
1924+
1925+static int
1926+mt7915_fw_debug_module_get(void *data, u64 *module)
1927+{
1928+ struct mt7915_dev *dev = data;
1929+
1930+ *module = dev->dbg.fw_dbg_module;
1931+ return 0;
1932+}
1933+
1934+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
1935+ mt7915_fw_debug_module_set, "%lld\n");
1936+
1937+static int
1938+mt7915_fw_debug_level_set(void *data, u64 level)
1939+{
1940+ struct mt7915_dev *dev = data;
1941+
1942+ dev->dbg.fw_dbg_lv = level;
1943+ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
1944+ return 0;
1945+}
1946+
1947+static int
1948+mt7915_fw_debug_level_get(void *data, u64 *level)
1949+{
1950+ struct mt7915_dev *dev = data;
1951+
1952+ *level = dev->dbg.fw_dbg_lv;
1953+ return 0;
1954+}
1955+
1956+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
1957+ mt7915_fw_debug_level_set, "%lld\n");
1958+
1959+#define MAX_TX_MODE 12
1960+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
1961+ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
1962+ "HE_TRIG", "HE_MU", "N/A"};
1963+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
1964+ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
1965+ "N/A"};
1966+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
1967+ "48M", "54M", "N/A"};
1968+static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
1969+ "20/40/80/160/80+80MHz"};
1970+
1971+static char *hw_rate_ofdm_str(u16 ofdm_idx)
1972+{
1973+ switch (ofdm_idx) {
1974+ case 11: /* 6M */
1975+ return HW_TX_RATE_OFDM_STR[0];
1976+
1977+ case 15: /* 9M */
1978+ return HW_TX_RATE_OFDM_STR[1];
1979+
1980+ case 10: /* 12M */
1981+ return HW_TX_RATE_OFDM_STR[2];
1982+
1983+ case 14: /* 18M */
1984+ return HW_TX_RATE_OFDM_STR[3];
1985+
1986+ case 9: /* 24M */
1987+ return HW_TX_RATE_OFDM_STR[4];
1988+
1989+ case 13: /* 36M */
1990+ return HW_TX_RATE_OFDM_STR[5];
1991+
1992+ case 8: /* 48M */
1993+ return HW_TX_RATE_OFDM_STR[6];
1994+
1995+ case 12: /* 54M */
1996+ return HW_TX_RATE_OFDM_STR[7];
1997+
1998+ default:
1999+ return HW_TX_RATE_OFDM_STR[8];
2000+ }
2001+}
2002+
2003+static char *hw_rate_str(u8 mode, u16 rate_idx)
2004+{
2005+ if (mode == 0)
2006+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
2007+ else if (mode == 1)
2008+ return hw_rate_ofdm_str(rate_idx);
2009+ else
2010+ return "MCS";
2011+}
2012+
2013+static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
2014+{
2015+ u16 txmode, mcs, nss, stbc;
2016+
2017+ txmode = FIELD_GET(GENMASK(9, 6), txrate);
2018+ mcs = FIELD_GET(GENMASK(5, 0), txrate);
2019+ nss = FIELD_GET(GENMASK(12, 10), txrate);
2020+ stbc = FIELD_GET(BIT(13), txrate);
2021+
2022+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
2023+ rate_idx + 1, txrate,
2024+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
2025+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
2026+}
2027+
2028+#define LWTBL_LEN_IN_DW 32
2029+#define UWTBL_LEN_IN_DW 8
2030+#define ONE_KEY_ENTRY_LEN_IN_DW 8
developerf32dabf2022-06-01 10:59:24 +08002031+static int mt7915_sta_info(struct seq_file *s, void *data)
2032+{
2033+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2034+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2035+ u16 i = 0;
2036+
2037+ for (i=0; i < mt7915_wtbl_size(dev); i++) {
2038+ mt7915_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
2039+ LWTBL_LEN_IN_DW, lwtbl);
2040+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1])
2041+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
2042+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2043+ }
2044+
2045+ return 0;
2046+}
2047+
developer3fa816c2022-04-19 10:21:20 +08002048+static int mt7915_wtbl_read(struct seq_file *s, void *data)
2049+{
2050+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2051+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2052+ int x;
2053+ u32 *addr = 0;
2054+ u32 dw_value = 0;
2055+
2056+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
2057+ LWTBL_LEN_IN_DW, lwtbl);
2058+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2059+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2060+ MT_DBG_WTBLON_TOP_WDUCR,
2061+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2062+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
2063+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
2064+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2065+ x,
2066+ lwtbl[x * 4 + 3],
2067+ lwtbl[x * 4 + 2],
2068+ lwtbl[x * 4 + 1],
2069+ lwtbl[x * 4]);
2070+ }
2071+
2072+ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
2073+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2074+
2075+ // DW0, DW1
2076+ seq_printf(s, "LWTBL DW 0/1\n\t");
2077+ addr = (u32 *)&(lwtbl[0]);
2078+ dw_value = *addr;
2079+ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2080+ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
2081+ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
2082+ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
2083+ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2084+ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2085+ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
2086+ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
2087+ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
2088+
2089+ // DW2
2090+ seq_printf(s, "LWTBL DW 2\n\t");
2091+ addr = (u32 *)&(lwtbl[2*4]);
2092+ dw_value = *addr;
2093+ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2094+ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
2095+ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
2096+ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
2097+ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
2098+ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
2099+ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2100+ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
2101+ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
2102+ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2103+ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2104+ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
2105+ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
2106+ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
2107+ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
2108+
2109+ // DW3
2110+ seq_printf(s, "LWTBL DW 3\n\t");
2111+ addr = (u32 *)&(lwtbl[3*4]);
2112+ dw_value = *addr;
2113+ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
2114+ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
2115+ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
2116+ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
2117+ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
2118+ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2119+ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2120+ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
2121+ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
2122+ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
2123+ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
2124+ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
2125+ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
2126+
2127+ // DW4
2128+ seq_printf(s, "LWTBL DW 4\n\t");
2129+ addr = (u32 *)&(lwtbl[4*4]);
2130+ dw_value = *addr;
2131+ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2132+ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
2133+ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
2134+ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
2135+ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2136+ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
2137+ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
2138+ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
2139+ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
2140+ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
2141+ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
2142+ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
2143+ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
2144+ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
2145+ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
2146+ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
2147+
2148+ // DW5
2149+ seq_printf(s, "LWTBL DW 5\n\t");
2150+ addr = (u32 *)&(lwtbl[5*4]);
2151+ dw_value = *addr;
2152+ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2153+ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
2154+ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
2155+ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
2156+ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
2157+ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
2158+ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
2159+ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2160+ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2161+ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2162+ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2163+ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2164+ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
2165+ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
2166+ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
2167+ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
2168+ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
2169+ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
2170+
2171+ // DW6
2172+ seq_printf(s, "LWTBL DW 6\n\t");
2173+ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
2174+ addr = (u32 *)&(lwtbl[6*4]);
2175+ dw_value = *addr;
2176+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
2177+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
2178+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
2179+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
2180+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
2181+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
2182+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
2183+ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
2184+
2185+ // DW7
2186+ seq_printf(s, "LWTBL DW 7\n\t");
2187+ addr = (u32 *)&(lwtbl[7*4]);
2188+ dw_value = *addr;
2189+ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2190+ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
2191+ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
2192+ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
2193+ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
2194+ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
2195+ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
2196+ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
2197+ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
2198+ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2199+ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
2200+ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
2201+ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
2202+ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2203+ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2204+ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 27), dw_value));
2205+ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
2206+ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
2207+
2208+ // DW8
2209+ seq_printf(s, "LWTBL DW 8\n\t");
2210+ addr = (u32 *)&(lwtbl[8*4]);
2211+ dw_value = *addr;
2212+ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
2213+ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
2214+ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
2215+ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
2216+ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
2217+ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
2218+
2219+ // DW9
2220+ seq_printf(s, "LWTBL DW 9\n\t");
2221+ addr = (u32 *)&(lwtbl[9*4]);
2222+ dw_value = *addr;
2223+ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
2224+ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
2225+ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
2226+ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
2227+ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
2228+ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
2229+ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
2230+ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
2231+ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
2232+ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
2233+
2234+ // DW10
2235+ seq_printf(s, "LWTBL DW 10\n");
2236+ addr = (u32 *)&(lwtbl[10*4]);
2237+ dw_value = *addr;
2238+ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
2239+ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
2240+ // DW11
2241+ seq_printf(s, "LWTBL DW 11\n");
2242+ addr = (u32 *)&(lwtbl[11*4]);
2243+ dw_value = *addr;
2244+ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
2245+ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
2246+ // DW12
2247+ seq_printf(s, "LWTBL DW 12\n");
2248+ addr = (u32 *)&(lwtbl[12*4]);
2249+ dw_value = *addr;
2250+ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
2251+ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
2252+ // DW13
2253+ seq_printf(s, "LWTBL DW 13\n");
2254+ addr = (u32 *)&(lwtbl[13*4]);
2255+ dw_value = *addr;
2256+ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
2257+ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
2258+
2259+ //DW28
2260+ seq_printf(s, "LWTBL DW 28\n\t");
2261+ addr = (u32 *)&(lwtbl[28*4]);
2262+ dw_value = *addr;
2263+ seq_printf(s, "OM_INFO:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2264+ seq_printf(s, "OM_RXD_DUP_MODE:%u\n\t", !!(dw_value & BIT(12)) );
2265+
2266+ //DW29
2267+ seq_printf(s, "LWTBL DW 29\n");
2268+ addr = (u32 *)&(lwtbl[29*4]);
2269+ dw_value = *addr;
2270+ seq_printf(s, "USER_RSSI:%lu/ ", FIELD_GET(GENMASK(8, 0), dw_value));
2271+ seq_printf(s, "USER_SNR:%lu/ ", FIELD_GET(GENMASK(14, 9), dw_value));
2272+ seq_printf(s, "RAPID_REACTION_RATE:%lu/ ", FIELD_GET(GENMASK(26, 16), dw_value));
2273+ seq_printf(s, "HT_AMSDU(Read Only):%u/ ", !!(dw_value & BIT(30)) );
2274+ seq_printf(s, "AMSDU_CROSS_LG(Read Only):%u\n\t ", !!(dw_value & BIT(31)));
2275+
2276+ //DW30
2277+ seq_printf(s, "LWTBL DW 30\n\t");
2278+ addr = (u32 *)&(lwtbl[30*4]);
2279+ dw_value = *addr;
2280+ seq_printf(s, "RCPI 0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2281+ seq_printf(s, "RCPI 1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2282+ seq_printf(s, "RCPI 2:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2283+ seq_printf(s, "RCPI 3:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2284+
2285+ //DW31
2286+ seq_printf(s, "LWTBL DW 31\n\t");
2287+ addr = (u32 *)&(lwtbl[31*4]);
2288+ dw_value = *addr;
2289+ seq_printf(s, "RCPI 4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2290+ seq_printf(s, "RCPI 5:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2291+ seq_printf(s, "RCPI 6:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2292+ seq_printf(s, "RCPI 7:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2293+
2294+ return 0;
2295+}
2296+
2297+static int mt7915_uwtbl_read(struct seq_file *s, void *data)
2298+{
2299+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2300+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
2301+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
2302+ int x;
2303+ u32 *addr = 0;
2304+ u32 dw_value = 0;
2305+ u32 amsdu_len = 0;
2306+ u32 u2SN = 0;
2307+ u16 keyloc0, keyloc1;
2308+
2309+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
2310+ UWTBL_LEN_IN_DW, uwtbl);
2311+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2312+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002313+ MT_DBG_UWTBL_TOP_WDUCR,
2314+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002315+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
2316+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
2317+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2318+ x,
2319+ uwtbl[x * 4 + 3],
2320+ uwtbl[x * 4 + 2],
2321+ uwtbl[x * 4 + 1],
2322+ uwtbl[x * 4]);
2323+ }
2324+
2325+ /* UMAC WTBL DW 0 */
2326+ seq_printf(s, "\nUWTBL PN\n\t");
2327+ addr = (u32 *)&(uwtbl[0]);
2328+ dw_value = *addr;
2329+ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2330+ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2331+ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2332+ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
2333+
2334+ addr = (u32 *)&(uwtbl[1 * 4]);
2335+ dw_value = *addr;
2336+ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2337+ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
2338+
2339+ /* UMAC WTBL DW SN part */
2340+ seq_printf(s, "\nUWTBL SN\n");
2341+ addr = (u32 *)&(uwtbl[2 * 4]);
2342+ dw_value = *addr;
2343+ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
2344+ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
2345+
2346+ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
2347+ addr = (u32 *)&(uwtbl[3 * 4]);
2348+ dw_value = *addr;
2349+ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
2350+ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
2351+ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
2352+ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2353+
2354+ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
2355+ addr = (u32 *)&(uwtbl[4 * 4]);
2356+ dw_value = *addr;
2357+ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
2358+ seq_printf(s, "TID5_SN:%u\n", u2SN);
2359+ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
2360+ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
2361+
2362+ addr = (u32 *)&(uwtbl[1 * 4]);
2363+ dw_value = *addr;
2364+ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2365+
2366+ /* UMAC WTBL DW 0 */
2367+ seq_printf(s, "\nUWTBL others\n");
2368+
2369+ addr = (u32 *)&(uwtbl[5 * 4]);
2370+ dw_value = *addr;
2371+ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
2372+ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
2373+ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
2374+ FIELD_GET(GENMASK(10, 0), dw_value),
2375+ FIELD_GET(GENMASK(26, 16), dw_value));
2376+ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
2377+ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
2378+
2379+ addr = (u32 *)&(uwtbl[6*4]);
2380+ dw_value = *addr;
2381+ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
2382+
2383+ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
2384+ if (amsdu_len == 0)
2385+ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
2386+ else if (amsdu_len == 1)
2387+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2388+ 1,
2389+ 255,
2390+ amsdu_len);
2391+ else
2392+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2393+ 256 * (amsdu_len - 1),
2394+ 256 * (amsdu_len - 1) + 255,
2395+ amsdu_len
2396+ );
2397+ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
2398+ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
2399+ FIELD_GET(GENMASK(8, 6), dw_value));
2400+
2401+ /* Parse KEY link */
2402+ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
2403+ if(keyloc0 != GENMASK(10, 0)) {
2404+ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
2405+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2406+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002407+ MT_DBG_UWTBL_TOP_WDUCR,
2408+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002409+ KEYTBL_IDX2BASE(keyloc0, 0));
2410+
2411+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2412+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2413+ x,
2414+ keytbl[x * 4 + 3],
2415+ keytbl[x * 4 + 2],
2416+ keytbl[x * 4 + 1],
2417+ keytbl[x * 4]);
2418+ }
2419+ }
2420+
2421+ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
2422+ if(keyloc1 != GENMASK(26, 16)) {
2423+ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
2424+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2425+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002426+ MT_DBG_UWTBL_TOP_WDUCR,
2427+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002428+ KEYTBL_IDX2BASE(keyloc1, 0));
2429+
2430+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2431+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2432+ x,
2433+ keytbl[x * 4 + 3],
2434+ keytbl[x * 4 + 2],
2435+ keytbl[x * 4 + 1],
2436+ keytbl[x * 4]);
2437+ }
2438+ }
2439+ return 0;
2440+}
2441+
2442+static void
2443+dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2444+{
2445+ u32 base, cnt, cidx, didx, queue_cnt;
2446+
2447+ base= mt76_rr(dev, ring_base);
2448+ cnt = mt76_rr(dev, ring_base + 4);
2449+ cidx = mt76_rr(dev, ring_base + 8);
2450+ didx = mt76_rr(dev, ring_base + 12);
2451+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2452+
2453+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2454+}
2455+
2456+static void
2457+dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2458+{
2459+ u32 base, cnt, cidx, didx, queue_cnt;
2460+
2461+ base= mt76_rr(dev, ring_base);
2462+ cnt = mt76_rr(dev, ring_base + 4);
2463+ cidx = mt76_rr(dev, ring_base + 8);
2464+ didx = mt76_rr(dev, ring_base + 12);
2465+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2466+
2467+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2468+}
2469+
2470+static void
2471+mt7915_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2472+{
2473+ u32 sys_ctrl[10] = {};
2474+
2475+ /* HOST DMA */
2476+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2477+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2478+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2479+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2480+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_INT_SOURCE_CSR);
2481+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_INT_MASK_CSR);
2482+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2483+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_GLO_CFG);
2484+ seq_printf(s, "HOST_DMA Configuration\n");
2485+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2486+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2487+ seq_printf(s, "%10s %10x %10x\n",
2488+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2489+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2490+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2491+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2492+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2493+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2494+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2495+
2496+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2497+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2498+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2499+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2500+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2501+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2502+
2503+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT1_SOURCE_CSR);
2504+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT1_MASK_CSR);
2505+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR);
2506+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR);
2507+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR);
2508+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR);
2509+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_GLO_CFG);
2510+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_GLO_CFG);
2511+ seq_printf(s, "%10s %10x %10x\n",
2512+ "MergeP1", sys_ctrl[0], sys_ctrl[1]);
2513+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2514+ "DMA0P1", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2515+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2516+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2517+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2518+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2519+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2520+ "DMA1P1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2521+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2522+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2523+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2524+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2525+
2526+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2527+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2528+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2529+ dump_dma_rx_ring_info(s, dev, "R0:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2530+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2531+
2532+ seq_printf(s, "HOST_DMA0 PCIe 1 Ring Configuration\n");
2533+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2534+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2535+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_WFDMA0_PCIE1_RX1_CTRL0);
2536+
2537+ seq_printf(s, "HOST_DMA1 Ring Configuration\n");
2538+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2539+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2540+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2541+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002542+ if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2543+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2544+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2545+ } else {
2546+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2547+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2548+ }
developer3fa816c2022-04-19 10:21:20 +08002549+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2550+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_EVENT_RING_CTRL(0));
developer79a21a22023-01-09 13:57:39 +08002551+ if (mtk_wed_device_active(&dev->mt76.mmio.wed))
2552+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2553+ else
2554+ dump_dma_rx_ring_info(s, dev, "R1:Event0(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer3fa816c2022-04-19 10:21:20 +08002555+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2556+
2557+ seq_printf(s, "HOST_DMA1 PCIe 1 Ring Configuration\n");
2558+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2559+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2560+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA1_PCIE1_TX19_CTRL0);
2561+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_WFDMA1_PCIE1_RX2_CTRL0);
2562+}
2563+
2564+static void
2565+mt7915_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2566+{
2567+ u32 sys_ctrl[9] = {};
2568+
2569+ /* MCU DMA information */
2570+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2571+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2572+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2573+
2574+ sys_ctrl[3] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR);
2575+ sys_ctrl[4] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR);
2576+ sys_ctrl[5] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR);
2577+ sys_ctrl[6] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
2578+ sys_ctrl[7] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR);
2579+ sys_ctrl[8] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR);
2580+
2581+ seq_printf(s, "MCU_DMA Configuration\n");
2582+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2583+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2584+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2585+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2586+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2587+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2588+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2589+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2590+
2591+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2592+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[3],
2593+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2594+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2595+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2596+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2597+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2598+ "DMA1P1", sys_ctrl[7], sys_ctrl[8], sys_ctrl[6],
2599+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2600+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2601+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2602+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2603+
2604+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2605+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2606+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2607+ dump_dma_tx_ring_info(s, dev, "T0:TXD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2608+ dump_dma_tx_ring_info(s, dev, "T1:TXCMD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2609+ dump_dma_tx_ring_info(s, dev, "T2:TXD(WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2610+ dump_dma_rx_ring_info(s, dev, "R0:Data(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2611+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2612+ dump_dma_rx_ring_info(s, dev, "R2:SPL(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2613+ dump_dma_rx_ring_info(s, dev, "R3:TxDone(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2614+ dump_dma_rx_ring_info(s, dev, "R4:TXS(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2615+
2616+ seq_printf(s, "MCU_DMA1 Ring Configuration\n");
2617+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2618+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2619+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR);
2620+ dump_dma_tx_ring_info(s, dev, "T1:Event0(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR);
2621+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR);
2622+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
2623+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
2624+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
2625+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR);
2626+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR);
2627+
2628+ seq_printf(s, "MCU_DMA1 PCIe 1 Ring Configuration\n");
2629+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2630+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2631+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR);
2632+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2633+}
2634+
2635+static void
2636+mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2637+{
2638+ u32 sys_ctrl[5] = {};
2639+
2640+ /* HOST DMA */
2641+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2642+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2643+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2644+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2645+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2646+
2647+ seq_printf(s, "HOST_DMA Configuration\n");
2648+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2649+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2650+ seq_printf(s, "%10s %10x %10x\n",
2651+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2652+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2653+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[4],
2654+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK, sys_ctrl[4]),
2655+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK, sys_ctrl[4]),
2656+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK, sys_ctrl[4]),
2657+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK, sys_ctrl[4]));
2658+
2659+
2660+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2661+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2662+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2663+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2664+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002665+
2666+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2667+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2668+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2669+ } else {
2670+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2671+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2672+ }
2673+
developer3fa816c2022-04-19 10:21:20 +08002674+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2675+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2676+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002677+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed))
2678+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2679+ else
2680+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
developer3fa816c2022-04-19 10:21:20 +08002681+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3));
2682+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2683+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2684+}
2685+
2686+static void
2687+mt7986_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2688+{
2689+ u32 sys_ctrl[3] = {};
2690+
2691+ /* MCU DMA information */
2692+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2693+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2694+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2695+
2696+ seq_printf(s, "MCU_DMA Configuration\n");
2697+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2698+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2699+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2700+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2701+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2702+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2703+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2704+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2705+
2706+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2707+ seq_printf(s, "%22s %10s %10s %10s %10s %10s\n",
2708+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2709+ dump_dma_tx_ring_info(s, dev, "T0:Event (WM2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2710+ dump_dma_tx_ring_info(s, dev, "T1:Event (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2711+ dump_dma_tx_ring_info(s, dev, "T2:TxDone (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2712+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1 (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2713+ dump_dma_tx_ring_info(s, dev, "T4:TXD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2714+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2715+ dump_dma_tx_ring_info(s, dev, "T6:TXD (WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2716+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2717+ dump_dma_rx_ring_info(s, dev, "R1:Cmd (H2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2718+ dump_dma_rx_ring_info(s, dev, "R2:TXD (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2719+ dump_dma_rx_ring_info(s, dev, "R3:TXD1 (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2720+ dump_dma_rx_ring_info(s, dev, "R4:Cmd (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2721+ dump_dma_rx_ring_info(s, dev, "R5:Data (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2722+ dump_dma_rx_ring_info(s, dev, "R6:TxDone/STS (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2723+ dump_dma_rx_ring_info(s, dev, "R7:RPT (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2724+ dump_dma_rx_ring_info(s, dev, "R8:TxDone/STS (MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2725+ dump_dma_rx_ring_info(s, dev, "R9:Data1 (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2726+
2727+}
2728+
2729+static void
2730+mt7915_show_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2731+{
2732+ u32 sys_ctrl[10] = {};
2733+
2734+ if(is_mt7915(&dev->mt76)) {
2735+ mt7915_show_host_dma_info(s, dev);
2736+ mt7915_show_mcu_dma_info(s, dev);
2737+ } else {
2738+ mt7986_show_host_dma_info(s, dev);
2739+ mt7986_show_mcu_dma_info(s, dev);
2740+ }
2741+
2742+ /* MEM DMA information */
2743+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
2744+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
2745+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
2746+
2747+ seq_printf(s, "MEM_DMA Configuration\n");
2748+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2749+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2750+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2751+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2752+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2753+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2754+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2755+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2756+
2757+ seq_printf(s, "MEM_DMA Ring Configuration\n");
2758+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2759+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2760+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
2761+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
2762+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
2763+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
2764+}
2765+
2766+static int mt7915_trinfo_read(struct seq_file *s, void *data)
2767+{
2768+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2769+ const struct hif_pci_tx_ring_desc *tx_ring_layout;
2770+ const struct hif_pci_rx_ring_desc *rx_ring_layout;
developer79a21a22023-01-09 13:57:39 +08002771+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
developer3fa816c2022-04-19 10:21:20 +08002772+ u32 tx_ring_num, rx_ring_num;
2773+ u32 tbase[5], tcnt[5];
2774+ u32 tcidx[5], tdidx[5];
2775+ u32 rbase[6], rcnt[6];
2776+ u32 rcidx[6], rdidx[6];
2777+ int idx;
developer79a21a22023-01-09 13:57:39 +08002778+ bool flags = false;
developer3fa816c2022-04-19 10:21:20 +08002779+
2780+ if(is_mt7915(&dev->mt76)) {
2781+ tx_ring_layout = &mt7915_tx_ring_layout[0];
2782+ rx_ring_layout = &mt7915_rx_ring_layout[0];
2783+ tx_ring_num = ARRAY_SIZE(mt7915_tx_ring_layout);
2784+ rx_ring_num = ARRAY_SIZE(mt7915_rx_ring_layout);
2785+ } else {
2786+ tx_ring_layout = &mt7986_tx_ring_layout[0];
2787+ rx_ring_layout = &mt7986_rx_ring_layout[0];
2788+ tx_ring_num = ARRAY_SIZE(mt7986_tx_ring_layout);
2789+ rx_ring_num = ARRAY_SIZE(mt7986_rx_ring_layout);
2790+ }
2791+
2792+ for (idx = 0; idx < tx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002793+ if (mtk_wed_device_active(wed) &&
2794+ (tx_ring_layout[idx].ring_attr == HIF_TX_DATA)) {
2795+ struct mt76_phy *phy = dev->mt76.phys[MT_BAND0];
2796+ struct mt76_phy *ext_phy = dev->mt76.phys[MT_BAND1];
2797+ struct mt76_queue *q;
2798+
2799+ tbase[idx] = tcnt[idx] = tcidx[idx] = tdidx[idx] = 0;
2800+
2801+ if (!phy)
2802+ continue;
2803+
2804+ if (flags && !ext_phy)
2805+ continue;
2806+
2807+ if (flags && ext_phy)
2808+ phy = ext_phy;
2809+
2810+ q = phy->q_tx[0];
2811+
2812+ if (q->wed_regs) {
2813+ tbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2814+ tcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2815+ tcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2816+ tdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2817+ }
2818+
2819+ flags = true;
2820+ } else {
2821+ tbase[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx));
2822+ tcnt[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x04);
2823+ tcidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x08);
2824+ tdidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x0c);}
developer3fa816c2022-04-19 10:21:20 +08002825+ }
2826+
2827+ for (idx = 0; idx < rx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002828+ if (rx_ring_layout[idx].ring_attr == HIF_RX_DATA) {
2829+ if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
2830+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN];
2831+
2832+ rbase[idx] = rcnt[idx] = rcidx[idx] = rdidx[idx] = 0;
2833+
2834+ if (idx == 1)
2835+ q = &dev->mt76.q_rx[MT_RXQ_BAND1];
2836+
2837+ if (q->wed_regs) {
2838+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2839+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2840+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2841+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2842+ }
2843+ } else {
2844+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx));
2845+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x04);
2846+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x08);
2847+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x0c);
2848+ }
developer3fa816c2022-04-19 10:21:20 +08002849+ } else {
developer79a21a22023-01-09 13:57:39 +08002850+ if (mtk_wed_device_active(wed) && rx_ring_layout[idx].flags) {
2851+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN_WA];
2852+
2853+ if (is_mt7915(&dev->mt76))
2854+ q = &dev->mt76.q_rx[MT_RXQ_MCU_WA];
2855+
2856+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2857+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2858+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2859+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2860+
2861+ } else {
2862+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2));
2863+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x04);
2864+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x08);
2865+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x0c);
2866+ }
developer3fa816c2022-04-19 10:21:20 +08002867+ }
2868+ }
2869+
2870+ seq_printf(s, "=================================================\n");
2871+ seq_printf(s, "TxRing Configuration\n");
2872+ seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n",
2873+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2874+ "QCnt");
2875+ for (idx = 0; idx < tx_ring_num; idx++) {
2876+ u32 queue_cnt;
2877+
2878+ queue_cnt = (tcidx[idx] >= tdidx[idx]) ?
2879+ (tcidx[idx] - tdidx[idx]) :
2880+ (tcidx[idx] - tdidx[idx] + tcnt[idx]);
2881+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2882+ idx, tx_ring_layout[idx].ring_info,
2883+ MT_DBG_TX_RING_CTRL(idx), tbase[idx],
2884+ tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt);
2885+ }
2886+
2887+ seq_printf(s, "RxRing Configuration\n");
2888+ seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n",
2889+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2890+ "QCnt");
2891+
2892+ for (idx = 0; idx < rx_ring_num; idx++) {
2893+ u32 queue_cnt;
2894+
2895+ queue_cnt = (rdidx[idx] > rcidx[idx]) ?
2896+ (rdidx[idx] - rcidx[idx] - 1) :
2897+ (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1);
2898+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2899+ idx, rx_ring_layout[idx].ring_info,
2900+ (idx < 2) ? MT_DBG_RX_DATA_RING_CTRL(idx): MT_DBG_RX_EVENT_RING_CTRL(idx - 2),
2901+ rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt);
2902+ }
2903+
2904+ mt7915_show_dma_info(s, dev);
2905+ return 0;
2906+}
2907+
2908+static int mt7915_drr_info(struct seq_file *s, void *data)
2909+{
2910+#define DL_AC_START 0x00
2911+#define DL_AC_END 0x0F
2912+#define UL_AC_START 0x10
2913+#define UL_AC_END 0x1F
2914+
2915+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2916+ u32 drr_sta_status[16];
2917+ u32 drr_ctrl_def_val = 0x80220000, drr_ctrl_val = 0;
2918+ bool is_show = false;
2919+ int idx, sta_line = 0, sta_no = 0, max_sta_line = (mt7915_wtbl_size(dev) + 31) / 32;
2920+ seq_printf(s, "DRR Table STA Info:\n");
2921+
2922+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2923+ is_show = true;
2924+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2925+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2926+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2927+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2928+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2929+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2930+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2931+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2932+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2933+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2934+
2935+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2936+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2937+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2938+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2939+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2940+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2941+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2942+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2943+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2944+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2945+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2946+ }
2947+ if (!is_mt7915(&dev->mt76))
2948+ max_sta_line = 8;
2949+
2950+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2951+ if (drr_sta_status[sta_line] > 0) {
2952+ for (sta_no = 0; sta_no < 32; sta_no++) {
2953+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2954+ if (is_show) {
2955+ seq_printf(s, "\n DL AC%02d Queue Non-Empty STA:\n", idx);
2956+ is_show = false;
2957+ }
2958+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2959+ }
2960+ }
2961+ }
2962+ }
2963+ }
2964+
2965+ for (idx = UL_AC_START; idx <= UL_AC_END; idx++) {
2966+ is_show = true;
2967+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2968+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2969+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2970+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2971+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2972+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2973+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2974+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2975+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2976+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2977+
2978+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2979+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2980+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2981+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2982+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2983+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2984+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2985+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2986+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2987+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2988+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2989+ }
2990+
2991+ if (!is_mt7915(&dev->mt76))
2992+ max_sta_line = 8;
2993+
2994+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2995+ if (drr_sta_status[sta_line] > 0) {
2996+ for (sta_no = 0; sta_no < 32; sta_no++) {
2997+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2998+ if (is_show) {
2999+ seq_printf(s, "\n UL AC%02d Queue Non-Empty STA:\n", idx);
3000+ is_show = false;
3001+ }
3002+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
3003+ }
3004+ }
3005+ }
3006+ }
3007+ }
3008+
3009+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
3010+ drr_ctrl_def_val = 0x80420000;
3011+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3012+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3013+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3014+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3015+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3016+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3017+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3018+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3019+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3020+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3021+
3022+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3023+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
3024+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3025+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3026+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3027+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3028+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3029+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3030+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3031+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3032+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3033+ }
3034+
3035+ seq_printf(s, "\nBSSGrp[%d]:\n", idx);
3036+ if (!is_mt7915(&dev->mt76))
3037+ max_sta_line = 8;
3038+
3039+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3040+ seq_printf(s, "0x%08x ", drr_sta_status[sta_line]);
3041+
3042+ if ((sta_line % 4) == 3)
3043+ seq_printf(s, "\n");
3044+ }
3045+ }
3046+
3047+ return 0;
3048+}
3049+
developerf32dabf2022-06-01 10:59:24 +08003050+#define CR_NUM_OF_AC 17
developer3fa816c2022-04-19 10:21:20 +08003051+
3052+typedef enum _ENUM_UMAC_PORT_T {
3053+ ENUM_UMAC_HIF_PORT_0 = 0,
3054+ ENUM_UMAC_CPU_PORT_1 = 1,
3055+ ENUM_UMAC_LMAC_PORT_2 = 2,
3056+ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
3057+ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
3058+} ENUM_UMAC_PORT_T, *P_ENUM_UMAC_PORT_T;
3059+
3060+/* N9 MCU QUEUE LIST */
3061+typedef enum _ENUM_UMAC_CPU_P_QUEUE_T {
3062+ ENUM_UMAC_CTX_Q_0 = 0,
3063+ ENUM_UMAC_CTX_Q_1 = 1,
3064+ ENUM_UMAC_CTX_Q_2 = 2,
3065+ ENUM_UMAC_CTX_Q_3 = 3,
3066+ ENUM_UMAC_CRX = 0,
3067+ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
3068+} ENUM_UMAC_CPU_P_QUEUE_T, *P_ENUM_UMAC_CPU_P_QUEUE_T;
3069+
3070+/* LMAC PLE TX QUEUE LIST */
3071+typedef enum _ENUM_UMAC_LMAC_PLE_TX_P_QUEUE_T {
3072+ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
3073+ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
3074+ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
3075+ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
3076+
3077+ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
3078+ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
3079+ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
3080+ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
3081+
3082+ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
3083+ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
3084+ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
3085+ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
3086+
3087+ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
3088+ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
3089+ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
3090+ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
3091+
3092+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
3093+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
3094+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
3095+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
3096+
3097+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
3098+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
3099+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
3100+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
3101+ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
3102+ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
3103+ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, /* DE suggests not to use 0x1f, it's only for hw free queue */
3104+ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
3105+
3106+} ENUM_UMAC_LMAC_TX_P_QUEUE_T, *P_ENUM_UMAC_LMAC_TX_P_QUEUE_T;
3107+
3108+typedef struct _EMPTY_QUEUE_INFO_T {
3109+ char *QueueName;
3110+ u32 Portid;
3111+ u32 Queueid;
3112+} EMPTY_QUEUE_INFO_T, *P_EMPTY_QUEUE_INFO_T;
3113+
3114+static EMPTY_QUEUE_INFO_T ple_queue_empty_info[] = {
3115+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3116+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3117+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3118+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3119+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3120+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0}, /* Q16 */
3121+ {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0},
3122+ {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0},
3123+ {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0},
3124+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1},
3125+ {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1},
3126+ {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1},
3127+ {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1},
3128+ {"NAF Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NAF},
3129+ {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NBCN},
3130+ {NULL, 0, 0}, {NULL, 0, 0}, /* 18, 19 not defined */
3131+ {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a},
3132+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3133+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 21~29 not defined */
3134+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e},
3135+ {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f}
3136+};
3137+
3138+static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = {
3139+ {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40},
3140+ {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41},
3141+ {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42},
3142+ {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43},
3143+ {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44},
3144+ {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45},
3145+ {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46},
3146+ {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47},
3147+ {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48},
3148+ {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49},
3149+ {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a},
3150+ {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b},
3151+ {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c},
3152+ {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d},
3153+ {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e},
3154+ {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f},
3155+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50},
3156+ {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51},
3157+ {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52},
3158+ {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53},
3159+ {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54},
3160+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x55},
3161+ {"TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x56},
3162+ {"TWT TSF-TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x57},
3163+ {"TWT DL Q1", ENUM_UMAC_LMAC_PORT_2, 0x58},
3164+ {"TWT UL Q1", ENUM_UMAC_LMAC_PORT_2, 0x59},
3165+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3166+};
3167+
3168+
3169+
3170+static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"};
3171+static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat,
3172+ u32 *sta_pause, u32 *dis_sta_map,
3173+ u32 dumptxd)
3174+{
3175+ int i, j;
3176+ u32 total_nonempty_cnt = 0;
3177+ u32 ac_num = 9, all_ac_num;
3178+
3179+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003180+ if (!is_mt7915(&dev->mt76))
3181+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003182+
3183+ all_ac_num = ac_num * 4;
3184+
3185+ for (j = 0; j < all_ac_num; j++) { /* show AC Q info */
3186+ for (i = 0; i < 32; i++) {
3187+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
developerf32dabf2022-06-01 10:59:24 +08003188+ u32 hfid, tfid, pktcnt, ac_n = j / ac_num, ctrl = 0;
developer3fa816c2022-04-19 10:21:20 +08003189+ u32 sta_num = i + (j % ac_num) * 32, fl_que_ctrl[3] = {0};
3190+ //struct wifi_dev *wdev = wdev_search_by_wcid(pAd, sta_num);
3191+ u32 wmmidx = 0;
3192+ struct mt7915_sta *msta;
3193+ struct mt76_wcid *wcid;
3194+ struct ieee80211_sta *sta = NULL;
3195+
3196+ wcid = rcu_dereference(dev->mt76.wcid[sta_num]);
3197+ sta = wcid_to_sta(wcid);
3198+ if (!sta) {
3199+ printk("ERROR!! no found STA wcid=%d\n", sta_num);
developerf32dabf2022-06-01 10:59:24 +08003200+ continue;
developer3fa816c2022-04-19 10:21:20 +08003201+ }
3202+ msta = container_of(wcid, struct mt7915_sta, wcid);
3203+ wmmidx = msta->vif->mt76.wmm_idx;
3204+
developerf32dabf2022-06-01 10:59:24 +08003205+ seq_printf(s, "\tSTA%d AC%d: ", sta_num, ac_n);
developer3fa816c2022-04-19 10:21:20 +08003206+
3207+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3208+ fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
developerf32dabf2022-06-01 10:59:24 +08003209+ fl_que_ctrl[0] |= (ac_n << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
developer3fa816c2022-04-19 10:21:20 +08003210+ fl_que_ctrl[0] |= sta_num;
3211+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3212+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3213+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3214+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3215+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3216+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3217+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x",
3218+ tfid, hfid, pktcnt);
3219+
3220+ if (((sta_pause[j % 6] & 0x1 << i) >> i) == 1)
3221+ ctrl = 2;
3222+
3223+ if (((dis_sta_map[j % 6] & 0x1 << i) >> i) == 1)
3224+ ctrl = 1;
3225+
3226+ seq_printf(s, " ctrl = %s", sta_ctrl_reg[ctrl]);
3227+ seq_printf(s, " (wmmidx=%d)\n", wmmidx);
3228+
3229+ total_nonempty_cnt++;
3230+
3231+ // TODO
3232+ //if (pktcnt > 0 && dumptxd > 0)
3233+ // ShowTXDInfo(pAd, hfid);
3234+ }
3235+ }
3236+ }
3237+
3238+ return total_nonempty_cnt;
3239+}
3240+
3241+static void chip_show_txcmdq_info(struct seq_file *s, struct mt7915_dev *dev, u32 ple_txcmd_stat)
3242+{
3243+ int i;
3244+
3245+ seq_printf(s, "Nonempty TXCMD Q info:\n");
developerf32dabf2022-06-01 10:59:24 +08003246+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003247+ if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) {
3248+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3249+
3250+ if (ple_txcmd_queue_empty_info[i].QueueName != NULL) {
3251+ seq_printf(s, "\t%s: ", ple_txcmd_queue_empty_info[i].QueueName);
3252+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3253+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid <<
3254+ MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3255+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid <<
3256+ MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3257+ } else
3258+ continue;
3259+
3260+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3261+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3262+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3263+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3264+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3265+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3266+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3267+ tfid, hfid, pktcnt);
3268+ }
3269+ }
3270+}
3271+
3272+static void chip_get_ple_acq_stat(struct mt7915_dev *dev, u32 *ple_stat)
3273+{
3274+ int i;
3275+ int cr_num = 9, all_cr_num;
3276+ u32 ac , index;
3277+
3278+ /* TDO: cr_num = 16 for mt7986 */
developer3fa816c2022-04-19 10:21:20 +08003279+ if(!is_mt7915(&dev->mt76))
developerf32dabf2022-06-01 10:59:24 +08003280+ cr_num = 17;
3281+
developer3fa816c2022-04-19 10:21:20 +08003282+ all_cr_num = cr_num * 4;
3283+
3284+ ple_stat[0] = mt76_rr(dev, MT_DBG_PLE_QUEUE_EMPTY);
3285+
3286+ for(i = 0; i < all_cr_num; i++) {
3287+ ac = i / cr_num;
3288+ index = i % cr_num;
3289+ ple_stat[i + 1] =
3290+ mt76_rr(dev, MT_DBG_PLE_AC_QEMPTY(ac, index));
3291+
3292+ }
3293+}
3294+
3295+static void chip_get_dis_sta_map(struct mt7915_dev *dev, u32 *dis_sta_map)
3296+{
3297+ int i;
developerf32dabf2022-06-01 10:59:24 +08003298+ u32 ac_num = 9;
3299+
3300+ /* TDO: ac_num = 16 for mt7986 */
3301+ if (!is_mt7915(&dev->mt76))
3302+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003303+
developerf32dabf2022-06-01 10:59:24 +08003304+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003305+ dis_sta_map[i] = mt76_rr(dev, MT_DBG_PLE_DIS_STA_MAP(i));
3306+ }
3307+}
3308+
3309+static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause)
3310+{
3311+ int i;
developerf32dabf2022-06-01 10:59:24 +08003312+ u32 ac_num = 9;
developer3fa816c2022-04-19 10:21:20 +08003313+
developerf32dabf2022-06-01 10:59:24 +08003314+ /* TDO: ac_num = 16 for mt7986 */
3315+ if (!is_mt7915(&dev->mt76))
3316+ ac_num = 17;
3317+
3318+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003319+ sta_pause[i] = mt76_rr(dev, MT_DBG_PLE_STATION_PAUSE(i));
3320+ }
3321+}
3322+
3323+static int mt7915_pleinfo_read(struct seq_file *s, void *data)
3324+{
3325+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3326+ u32 ple_buf_ctrl, pg_sz, pg_num;
developerf32dabf2022-06-01 10:59:24 +08003327+ u32 ple_stat[70] = {0}, pg_flow_ctrl[8] = {0};
developer3fa816c2022-04-19 10:21:20 +08003328+ u32 ple_native_txcmd_stat;
3329+ u32 ple_txcmd_stat;
3330+ u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0};
3331+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q;
3332+ u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu;
3333+ int i, j;
3334+ u32 ac_num = 9, all_ac_num;
3335+
3336+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003337+ if (!is_mt7915(&dev->mt76))
3338+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003339+
3340+ all_ac_num = ac_num * 4;
3341+
3342+ ple_buf_ctrl = mt76_rr(dev, MT_DBG_PLE_PBUF_CTRL_ADDR);
3343+ chip_get_ple_acq_stat(dev, ple_stat);
3344+ ple_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_TXCMD_Q_EMPTY);
3345+ ple_native_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY);
3346+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PLE_FREEPG_CNT);
3347+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FREEPG_HEAD_TAIL);
3348+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_GROUP);
3349+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PLE_HIF_PG_INFO);
3350+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PLE_PG_CPU_GROUP);
3351+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PLE_CPU_PG_INFO);
3352+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_TXCMD_GROUP);
3353+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PLE_HIF_TXCMD_PG_INFO);
3354+ chip_get_dis_sta_map(dev, dis_sta_map);
3355+ chip_get_sta_pause(dev, sta_pause);
3356+
3357+ seq_printf(s, "PLE Configuration Info:\n");
3358+ seq_printf(s, "\tPacket Buffer Control(0x%x): 0x%08x\n",
3359+ MT_DBG_PLE_PBUF_CTRL_ADDR, ple_buf_ctrl);
3360+
3361+ pg_sz = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK, ple_buf_ctrl);
3362+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n",
3363+ pg_sz, (pg_sz == 1 ? 128 : 64));
3364+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 2KB)\n",
3365+ FIELD_GET(MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK, ple_buf_ctrl));
3366+
3367+ pg_num = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, ple_buf_ctrl);
3368+ seq_printf(s, "\t\tTotal Page=%d pages\n", pg_num);
3369+
3370+ /* Page Flow Control */
3371+ seq_printf(s, "PLE Page Flow Control:\n");
3372+ seq_printf(s, "\tFree page counter(0x%x): 0x%08x\n",
3373+ MT_DBG_PLE_FREEPG_CNT, pg_flow_ctrl[0]);
3374+ fpg_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3375+
3376+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3377+ ffa_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3378+
3379+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3380+ seq_printf(s, "\tFree page head and tail(0x%x): 0x%08x\n",
3381+ MT_DBG_PLE_FREEPG_HEAD_TAIL, pg_flow_ctrl[1]);
3382+
3383+ fpg_head = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3384+ fpg_tail = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3385+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3386+ seq_printf(s, "\tReserved page counter of HIF group(0x%x): 0x%08x\n",
3387+ MT_DBG_PLE_PG_HIF_GROUP, pg_flow_ctrl[2]);
3388+ seq_printf(s, "\tHIF group page status(0x%x): 0x%08x\n",
3389+ MT_DBG_PLE_HIF_PG_INFO, pg_flow_ctrl[3]);
3390+
3391+ hif_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3392+ hif_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3393+ seq_printf(s, "\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q);
3394+
3395+ rpg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK, pg_flow_ctrl[3]);
3396+ upg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK, pg_flow_ctrl[3]);
3397+ seq_printf(s, "\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif);
3398+
3399+ seq_printf(s, "\tReserved page counter of HIF_TXCMD group(0x%x): 0x%08x\n",
3400+ MT_DBG_PLE_PG_HIF_TXCMD_GROUP, pg_flow_ctrl[6]);
3401+ seq_printf(s, "\tHIF_TXCMD group page status(0x%x): 0x%08x\n",
3402+ MT_DBG_PLE_HIF_TXCMD_PG_INFO, pg_flow_ctrl[7]);
3403+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
developerf32dabf2022-06-01 10:59:24 +08003404+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
developer3fa816c2022-04-19 10:21:20 +08003405+ seq_printf(s, "\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3406+
3407+ rpg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK, pg_flow_ctrl[7]);
3408+ upg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK, pg_flow_ctrl[7]);
3409+ seq_printf(s, "\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3410+
developerf32dabf2022-06-01 10:59:24 +08003411+ seq_printf(s, "\tReserved page counter of CPU group(0x%x): 0x%08x\n",
3412+ MT_DBG_PLE_PG_CPU_GROUP, pg_flow_ctrl[4]);
3413+ seq_printf(s, "\tCPU group page status(0x%x): 0x%08x\n",
3414+ MT_DBG_PLE_CPU_PG_INFO, pg_flow_ctrl[5]);
developer3fa816c2022-04-19 10:21:20 +08003415+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3416+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3417+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3418+
3419+ rpg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[5]);
3420+ upg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[5]);
3421+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3422+
3423+ if ((ple_stat[0] & MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK) == 0) {
3424+ for (j = 0; j < all_ac_num; j++) {
3425+ if (j % ac_num == 0) {
3426+ seq_printf(s, "\n\tNonempty AC%d Q of STA#: ", j / ac_num);
3427+ }
3428+
developerf32dabf2022-06-01 10:59:24 +08003429+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003430+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
3431+ seq_printf(s, "%d ", i + (j % ac_num) * 32);
3432+ }
3433+ }
3434+ }
3435+
3436+ seq_printf(s, "\n");
3437+ }
3438+
3439+ seq_printf(s, "non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat);
3440+
3441+ seq_printf(s, "Nonempty Q info:\n");
3442+
developerf32dabf2022-06-01 10:59:24 +08003443+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003444+ if (((ple_stat[0] & (0x1 << i)) >> i) == 0) {
3445+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3446+
3447+ if (ple_queue_empty_info[i].QueueName != NULL) {
3448+ seq_printf(s, "\t%s: ", ple_queue_empty_info[i].QueueName);
3449+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3450+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3451+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3452+ } else
3453+ continue;
3454+
3455+ if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 &&
3456+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0)
3457+ /* band0 set TGID 0, bit31 = 0 */
3458+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x0);
3459+ else if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 &&
3460+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1)
3461+ /* band1 set TGID 1, bit31 = 1 */
3462+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x80000000);
3463+
3464+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3465+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3466+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3467+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3468+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3469+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3470+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3471+ tfid, hfid, pktcnt);
3472+
3473+ /* TODO */
3474+ //if (pktcnt > 0 && dumptxd > 0)
3475+ // ShowTXDInfo(pAd, hfid);
3476+ }
3477+ }
3478+
3479+ chip_show_sta_acq_info(s, dev, ple_stat, sta_pause, dis_sta_map, 0/*dumptxd*/);
3480+ chip_show_txcmdq_info(s, dev, ple_native_txcmd_stat);
3481+
3482+ return 0;
3483+}
3484+
3485+typedef enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE_T {
3486+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
3487+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
3488+ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
3489+} ENUM_UMAC_PLE_CTRL_P3_QUEUE_T, *P_ENUM_UMAC_PLE_CTRL_P3_QUEUE_T;
3490+
3491+static EMPTY_QUEUE_INFO_T pse_queue_empty_info[] = {
3492+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3493+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3494+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3495+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3496+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3497+ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
3498+ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
3499+ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
3500+ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
3501+ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
3502+ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
3503+ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
3504+ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
3505+ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
3506+ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
3507+ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
3508+ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
3509+ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
3510+ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
3511+ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
3512+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
3513+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
3514+};
3515+
3516+static int mt7915_pseinfo_read(struct seq_file *s, void *data)
3517+{
3518+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3519+ u32 pse_buf_ctrl, pg_sz, pg_num;
3520+ u32 pse_stat, pg_flow_ctrl[22] = {0};
3521+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
3522+ u32 max_q, min_q, rsv_pg, used_pg;
3523+ int i;
3524+
3525+ pse_buf_ctrl = mt76_rr(dev, MT_DBG_PSE_PBUF_CTRL);
3526+ pse_stat = mt76_rr(dev, MT_DBG_PSE_QUEUE_EMPTY);
3527+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PSE_FREEPG_CNT);
3528+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FREEPG_HEAD_TAIL);
3529+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_PG_HIF0_GROUP);
3530+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PSE_HIF0_PG_INFO);
3531+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PSE_PG_HIF1_GROUP);
3532+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PSE_HIF1_PG_INFO);
3533+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PSE_PG_CPU_GROUP);
3534+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PSE_CPU_PG_INFO);
3535+ pg_flow_ctrl[8] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC0_GROUP);
3536+ pg_flow_ctrl[9] = mt76_rr(dev, MT_DBG_PSE_LMAC0_PG_INFO);
3537+ pg_flow_ctrl[10] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC1_GROUP);
3538+ pg_flow_ctrl[11] = mt76_rr(dev, MT_DBG_PSE_LMAC1_PG_INFO);
3539+ pg_flow_ctrl[12] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC2_GROUP);
3540+ pg_flow_ctrl[13] = mt76_rr(dev, MT_DBG_PSE_LMAC2_PG_INFO);
3541+ pg_flow_ctrl[14] = mt76_rr(dev, MT_DBG_PSE_PG_PLE_GROUP);
3542+ pg_flow_ctrl[15] = mt76_rr(dev, MT_DBG_PSE_PLE_PG_INFO);
3543+ pg_flow_ctrl[16] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC3_GROUP);
3544+ pg_flow_ctrl[17] = mt76_rr(dev, MT_DBG_PSE_LMAC3_PG_INFO);
3545+ pg_flow_ctrl[18] = mt76_rr(dev, MT_DBG_PSE_PG_MDP_GROUP);
3546+ pg_flow_ctrl[19] = mt76_rr(dev, MT_DBG_PSE_MDP_PG_INFO);
3547+ pg_flow_ctrl[20] = mt76_rr(dev, MT_DBG_PSE_PG_PLE1_GROUP);
3548+ pg_flow_ctrl[21] = mt76_rr(dev,MT_DBG_PSE_PLE1_PG_INFO);
3549+
3550+ /* Configuration Info */
3551+ seq_printf(s, "PSE Configuration Info:\n");
3552+ seq_printf(s, "\tPacket Buffer Control(0x82068014): 0x%08x\n", pse_buf_ctrl);
3553+ pg_sz = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK, pse_buf_ctrl);
3554+
3555+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128));
3556+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 64KB)\n",
3557+ FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK, pse_buf_ctrl));
3558+ pg_num = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, pse_buf_ctrl);
3559+
3560+ seq_printf(s, "\t\tTotal page numbers=%d pages\n", pg_num);
3561+
3562+ /* Page Flow Control */
3563+ seq_printf(s, "PSE Page Flow Control:\n");
3564+ seq_printf(s, "\tFree page counter(0x82068100): 0x%08x\n", pg_flow_ctrl[0]);
3565+ fpg_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3566+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3567+
3568+ ffa_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3569+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3570+
3571+ seq_printf(s, "\tFree page head and tail(0x82068104): 0x%08x\n", pg_flow_ctrl[1]);
3572+ fpg_head = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3573+
3574+ fpg_tail = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3575+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3576+ seq_printf(s, "\tReserved page counter of HIF0 group(0x82068110): 0x%08x\n", pg_flow_ctrl[2]);
3577+ seq_printf(s, "\tHIF0 group page status(0x82068114): 0x%08x\n", pg_flow_ctrl[3]);
3578+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3579+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3580+ seq_printf(s, "\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q);
3581+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK, pg_flow_ctrl[3]);;
3582+ used_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK, pg_flow_ctrl[3]);
3583+ seq_printf(s, "\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3584+ seq_printf(s, "\tReserved page counter of HIF1 group(0x82068118): 0x%08x\n", pg_flow_ctrl[4]);
3585+ seq_printf(s, "\tHIF1 group page status(0x8206811c): 0x%08x\n", pg_flow_ctrl[5]);
3586+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3587+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3588+ seq_printf(s, "\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q);
3589+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK, pg_flow_ctrl[5]);
3590+ used_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK, pg_flow_ctrl[5]);
3591+
3592+ seq_printf(s, "\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3593+ seq_printf(s, "\tReserved page counter of CPU group(0x82068150): 0x%08x\n", pg_flow_ctrl[6]);
3594+ seq_printf(s, "\tCPU group page status(0x82068154): 0x%08x\n", pg_flow_ctrl[7]);
3595+ min_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3596+ max_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
3597+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q);
3598+ rsv_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[7]);
3599+ used_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[7]);
3600+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3601+ seq_printf(s, "\tReserved page counter of LMAC0 group(0x82068170): 0x%08x\n", pg_flow_ctrl[8]);
3602+ seq_printf(s, "\tLMAC0 group page status(0x82068174): 0x%08x\n", pg_flow_ctrl[9]);
3603+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK, pg_flow_ctrl[8]);
3604+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK, pg_flow_ctrl[8]);
3605+ seq_printf(s, "\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q);
3606+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK, pg_flow_ctrl[9]);
3607+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK, pg_flow_ctrl[9]);
3608+ seq_printf(s, "\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3609+ seq_printf(s, "\tReserved page counter of LMAC1 group(0x82068178): 0x%08x\n", pg_flow_ctrl[10]);
3610+ seq_printf(s, "\tLMAC1 group page status(0x8206817c): 0x%08x\n", pg_flow_ctrl[11]);
3611+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK, pg_flow_ctrl[10]);
3612+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK, pg_flow_ctrl[10]);
3613+ seq_printf(s, "\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q);
3614+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK, pg_flow_ctrl[11]);
3615+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK, pg_flow_ctrl[11]);
3616+ seq_printf(s, "\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3617+ seq_printf(s, "\tReserved page counter of LMAC2 group(0x82068180): 0x%08x\n", pg_flow_ctrl[11]);
3618+ seq_printf(s, "\tLMAC2 group page status(0x82068184): 0x%08x\n", pg_flow_ctrl[12]);
3619+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK, pg_flow_ctrl[12]);
3620+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK, pg_flow_ctrl[12]);
3621+ seq_printf(s, "\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q);
3622+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK, pg_flow_ctrl[13]);
3623+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK, pg_flow_ctrl[13]);
3624+ seq_printf(s, "\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3625+
3626+ seq_printf(s, "\tReserved page counter of LMAC3 group(0x82068188): 0x%08x\n", pg_flow_ctrl[16]);
3627+ seq_printf(s, "\tLMAC3 group page status(0x8206818c): 0x%08x\n", pg_flow_ctrl[17]);
3628+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK, pg_flow_ctrl[16]);
3629+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK, pg_flow_ctrl[16]);
3630+ seq_printf(s, "\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q);
3631+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK, pg_flow_ctrl[17]);
3632+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK, pg_flow_ctrl[17]);
3633+ seq_printf(s, "\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3634+
3635+ seq_printf(s, "\tReserved page counter of PLE group(0x82068160): 0x%08x\n", pg_flow_ctrl[14]);
3636+ seq_printf(s, "\tPLE group page status(0x82068164): 0x%08x\n", pg_flow_ctrl[15]);
3637+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[14]);
3638+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[14]);
3639+ seq_printf(s, "\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q);
3640+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[15]);
3641+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[15]);
3642+ seq_printf(s, "\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3643+
3644+ seq_printf(s, "\tReserved page counter of PLE1 group(0x82068168): 0x%08x\n", pg_flow_ctrl[14]);
3645+ seq_printf(s, "\tPLE1 group page status(0x8206816c): 0x%08x\n", pg_flow_ctrl[15]);
3646+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[20]);
3647+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[20]);
3648+ seq_printf(s, "\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q);
3649+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[21]);
3650+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[21]);
3651+ seq_printf(s, "\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3652+
3653+ seq_printf(s, "\tReserved page counter of MDP group(0x82068198): 0x%08x\n", pg_flow_ctrl[18]);
3654+ seq_printf(s, "\tMDP group page status(0x8206819c): 0x%08x\n", pg_flow_ctrl[19]);
3655+ min_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK, pg_flow_ctrl[18]);
3656+ max_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK, pg_flow_ctrl[18]);
3657+ seq_printf(s, "\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q);
3658+ rsv_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK, pg_flow_ctrl[19]);
3659+ used_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK, pg_flow_ctrl[19]);
3660+ seq_printf(s, "\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3661+
3662+ /* Queue Empty Status */
3663+ seq_printf(s, "PSE Queue Empty Status:\n");
3664+ seq_printf(s, "\tQUEUE_EMPTY(0x820680b0): 0x%08x\n", pse_stat);
3665+ seq_printf(s, "\t\tCPU Q0/1/2/3 empty=%ld/%ld/%ld/%ld\n",
3666+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK, pse_stat),
3667+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK, pse_stat),
3668+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK, pse_stat),
3669+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK, pse_stat));
3670+
3671+ seq_printf(s, "\t\tHIF Q0/1/2/3/4/5 empty=%ld/%ld/%ld/%ld/%ld/%ld\n",
3672+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK, pse_stat),
3673+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK, pse_stat),
3674+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK, pse_stat),
3675+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK, pse_stat),
3676+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK, pse_stat),
3677+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK, pse_stat));
3678+
3679+ seq_printf(s, "\t\tLMAC TX Q empty=%ld\n",
3680+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK, pse_stat));
3681+ seq_printf(s, "\t\tMDP TX Q/RX Q empty=%ld/%ld\n",
3682+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK, pse_stat),
3683+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK, pse_stat));
3684+ seq_printf(s, "\t\tSEC TX Q/RX Q empty=%ld/%ld\n",
3685+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK, pse_stat),
3686+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT, pse_stat));
3687+ seq_printf(s, "\t\tSFD PARK Q empty=%ld\n",
3688+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK, pse_stat));
3689+ seq_printf(s, "\t\tMDP TXIOC Q/RXIOC Q empty=%ld/%ld\n",
3690+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK, pse_stat),
3691+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK, pse_stat));
3692+ seq_printf(s, "\t\tRLS Q empty=%ld\n",
3693+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK, pse_stat));
3694+ seq_printf(s, "Nonempty Q info:\n");
3695+
3696+ for (i = 0; i < 31; i++) {
3697+ if (((pse_stat & (0x1 << i)) >> i) == 0) {
3698+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3699+
3700+ if (pse_queue_empty_info[i].QueueName != NULL) {
3701+ seq_printf(s, "\t%s: ", pse_queue_empty_info[i].QueueName);
3702+ fl_que_ctrl[0] |= MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK;
3703+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Portid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
3704+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
3705+ } else
3706+ continue;
3707+
3708+ fl_que_ctrl[0] |= (0x1 << 31);
3709+
3710+ mt76_wr(dev, MT_DBG_PSE_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
3711+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_2_ADDR);
3712+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_3_ADDR);
3713+
3714+ hfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK, fl_que_ctrl[1]);
3715+ tfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK, fl_que_ctrl[1]);
3716+ pktcnt = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK, fl_que_ctrl[2]);
3717+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3718+ tfid, hfid, pktcnt);
3719+ }
3720+ }
3721+
3722+ return 0;
3723+}
3724+
3725+static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3726+{
3727+#define BSS_NUM 4
3728+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3729+ u32 mac_val0, mac_val, mac_val1, idx, band_offset = 0;
3730+ u32 msdr6, msdr7, msdr8, msdr9, msdr10, msdr16, msdr17, msdr18, msdr19, msdr20, msdr21;
3731+ u32 mbxsdr[BSS_NUM][7];
3732+ u32 mbtcr[16], mbtbcr[16], mbrcr[16], mbrbcr[16];
3733+ u32 btcr[BSS_NUM], btbcr[BSS_NUM], brcr[BSS_NUM], brbcr[BSS_NUM], btdcr[BSS_NUM], brdcr[BSS_NUM];
3734+ u32 mu_cnt[5];
3735+ u32 ampdu_cnt[3];
3736+ unsigned long per;
3737+
3738+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3739+ seq_printf(s, "===============================\n");
3740+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SCR0(band_idx));
3741+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3742+ if (is_mt7915(&dev->mt76)) {
3743+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0PBSCR(band_idx));
3744+ seq_printf(s, "MIB Per-BSS Status Control=0x%x\n", mac_val);
3745+ }
3746+
3747+ msdr6 = mt76_rr(dev, MT_DBG_MIB_M0SDR6(band_idx));
3748+ msdr7 = mt76_rr(dev, MT_DBG_MIB_M0SDR7(band_idx));
3749+ msdr8 = mt76_rr(dev, MT_DBG_MIB_M0SDR8(band_idx));
3750+ msdr9 = mt76_rr(dev, MT_DBG_MIB_M0SDR9(band_idx));
3751+ msdr10 = mt76_rr(dev, MT_DBG_MIB_M0SDR10(band_idx));
3752+ msdr16 = mt76_rr(dev, MT_DBG_MIB_M0SDR16(band_idx));
3753+ msdr17 = mt76_rr(dev, MT_DBG_MIB_M0SDR17(band_idx));
3754+ msdr18 = mt76_rr(dev, MT_DBG_MIB_M0SDR18(band_idx));
3755+ msdr19 = mt76_rr(dev, MT_DBG_MIB_M0SDR19(band_idx));
3756+ msdr20 = mt76_rr(dev, MT_DBG_MIB_M0SDR20(band_idx));
3757+ msdr21 = mt76_rr(dev, MT_DBG_MIB_M0SDR21(band_idx));
3758+ ampdu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_M0SDR12(band_idx));
3759+ ampdu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0SDR14(band_idx));
3760+ ampdu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0SDR15(band_idx));
3761+ ampdu_cnt[1] &= MT_DBG_MIB_M0SDR14_AMPDU_MASK;
3762+ ampdu_cnt[2] &= MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK;
3763+
3764+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3765+ seq_printf(s, "\tChannelIdleCnt=0x%x\n", msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3766+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3767+ seq_printf(s, "\tRx_MDRDY_CNT=0x%lx\n", msdr10 & MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK);
3768+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x, OFDM_GREEN_MDRDY_TIME=0x%x\n",
3769+ msdr19 & BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK,
3770+ msdr20 & BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK,
3771+ msdr21 & BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK);
3772+ seq_printf(s, "\tPrim CCA Time=0x%x\n", msdr16 & BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK);
3773+ seq_printf(s, "\tSec CCA Time=0x%x\n", msdr17 & BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK);
3774+ seq_printf(s, "\tPrim ED Time=0x%x\n", msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3775+
3776+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3777+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR0(band_idx));
3778+ dev->dbg.bcn_total_cnt[band_idx] += (mac_val & BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK);
3779+ seq_printf(s, "\tBeaconTxCnt=0x%x\n",dev->dbg.bcn_total_cnt[band_idx]);
3780+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3781+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR0(band_idx));
3782+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK);
3783+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT);
3784+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR1(band_idx));
3785+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK);
3786+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT);
3787+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3788+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3789+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3790+ per = (ampdu_cnt[2] == 0 ? 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3791+ seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10);
3792+
3793+ seq_printf(s, "===MU Related Counters===\n");
3794+ mu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_MUBF(band_idx));
3795+ mu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0DR8(band_idx));
3796+ mu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0DR9(band_idx));
3797+ mu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR10(band_idx));
3798+ mu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3799+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", mu_cnt[0] & BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK);
3800+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3801+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3802+ seq_printf(s, "\tMU_TO_SU_PPDU_COUNT=0x%x\n", mu_cnt[3] & BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK);
3803+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3804+
3805+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3806+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", msdr7 & BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK);
3807+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", msdr8 & BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK);
3808+
3809+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR3(band_idx));
3810+ seq_printf(s, "\tRxFCSErrCnt=0x%lx\n", __DBG_FIELD_GET(DBG_MIB_RX_FCS_ERROR_COUNT, mac_val));
3811+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR4(band_idx));
3812+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK));
3813+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR11(band_idx));
3814+ seq_printf(s, "\tRxLenMismatch=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK));
3815+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR5(band_idx));
3816+ seq_printf(s, "\tRxMPDUCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK));
3817+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR22(band_idx));
3818+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3819+ /* TODO: shiang-MT7615, is MIB_M0SDR23 used for Rx total byte count for all or just AMPDU only??? */
3820+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR23(band_idx));
3821+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3822+
3823+ if (is_mt7915(&dev->mt76)) {
3824+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;//check
3825+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3826+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3827+
3828+ for (idx = 0; idx < BSS_NUM; idx++) {
3829+ btcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTCRn_ADDR + band_offset + idx * 4);
3830+ btbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTBCRn_ADDR + band_offset + idx * 4);
3831+ brcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRCRn_ADDR + band_offset + idx * 4);
3832+ brbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRBCRn_ADDR + band_offset + idx * 4);
3833+ btdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTDCRn_ADDR + band_offset + idx * 4);
3834+ brdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRDCRn_ADDR + band_offset + idx * 4);
3835+ }
3836+
3837+ for (idx = 0; idx < BSS_NUM; idx++) {
3838+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3839+ idx, btcr[idx], btdcr[idx], btbcr[idx],
3840+ brcr[idx], brdcr[idx], brbcr[idx]);
3841+ }
3842+
3843+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3844+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3845+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3846+
3847+ for (idx = 0; idx < BSS_NUM; idx++) {
3848+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR0_ADDR + band_offset + idx * 0x10);
3849+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR1_ADDR + band_offset + idx * 0x10);
3850+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR2_ADDR + band_offset + idx * 0x10);
3851+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR3_ADDR + band_offset + idx * 0x10);
3852+ }
3853+
3854+ for (idx = 0; idx < BSS_NUM; idx++) {
3855+ seq_printf(s, "%d:\t0x%08x/0x%08x 0x%08x \t 0x%08x \t 0x%08x/0x%08x/0x%08x\n",
3856+ idx, (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK),
3857+ (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT,
3858+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK),
3859+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT,
3860+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK),
3861+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT,
3862+ (mbxsdr[idx][3] & BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK));
3863+ }
3864+
3865+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
3866+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3867+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3868+
3869+ for (idx = 0; idx < 16; idx++) {
3870+ mbtcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTCRn_ADDR + band_offset + idx * 4);
3871+ mbtbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTBCRn_ADDR + band_offset + idx * 4);
3872+ mbrcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRCRn_ADDR + band_offset + idx * 4);
3873+ mbrbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRBCRn_ADDR + band_offset + idx * 4);
3874+ }
3875+
3876+ for (idx = 0; idx < 16; idx++) {
3877+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3878+ idx, mbtcr[idx], mbtbcr[idx], mbrcr[idx], mbrbcr[idx]);
3879+ }
3880+ return 0;
3881+ } else {
3882+ u32 btocr[BSS_NUM], mbtocr[16],mbrocr[16], brocr[BSS_NUM];
3883+ u8 bss_nums = BSS_NUM;
3884+
3885+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3886+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3887+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3888+
3889+ for (idx = 0; idx < BSS_NUM; idx++) {
3890+ btocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (idx >> 1) * 4));
3891+ btdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + (idx >> 1) * 4));
3892+ btbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (idx * 4)));
3893+ brocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (idx >> 1) * 4));
3894+ brdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRDCR_ADDR + band_offset + (idx >> 1) * 4));
3895+ brbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (idx * 4)));
3896+
3897+ if ((idx % 2) == 0) {
3898+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3899+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT);
3900+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3901+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT);
3902+ } else {
3903+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3904+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT);
3905+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3906+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT);
3907+ }
3908+ }
3909+
3910+ for (idx = 0; idx < BSS_NUM; idx++) {
3911+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3912+ idx, btocr[idx], btdcr[idx], btbcr[idx], brocr[idx], brdcr[idx], brbcr[idx]);
3913+ }
3914+
3915+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3916+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3917+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3918+
3919+ for (idx = 0; idx < BSS_NUM; idx++) {
3920+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR0_ADDR + band_offset + ((idx >> 1) * 4));
3921+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR1_ADDR + band_offset + ((idx >> 1) * 4));
3922+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR2_ADDR + band_offset + ((idx >> 1) * 4));
3923+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR3_ADDR + band_offset + ((idx >> 1) * 4));
3924+ mbxsdr[idx][4] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR4_ADDR + band_offset + ((idx >> 1) * 4));
3925+ mbxsdr[idx][5] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR5_ADDR + band_offset + ((idx >> 1) * 4));
3926+ mbxsdr[idx][6] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR6_ADDR + band_offset + ((idx >> 1) * 4));
3927+
3928+ if ((idx % 2) == 0) {
3929+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT);
3930+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT);
3931+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT);
3932+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT);
3933+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT);
3934+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT);
3935+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT);
3936+ } else {
3937+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT);
3938+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT);
3939+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT);
3940+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT);
3941+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT);
3942+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT);
3943+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT);
3944+ }
3945+ }
3946+
3947+ for (idx = 0; idx < BSS_NUM; idx++) {
3948+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
3949+ idx,
3950+ mbxsdr[idx][0], mbxsdr[idx][1], mbxsdr[idx][2], mbxsdr[idx][3],
3951+ mbxsdr[idx][4], mbxsdr[idx][5], mbxsdr[idx][6]);
3952+ }
3953+
3954+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3955+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3956+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3957+
3958+ for (idx = 0; idx < 16; idx++) {
3959+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3960+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3961+ mbrocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3962+ mbrbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3963+
3964+ if ((idx % 2) == 0) {
3965+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3966+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3967+ } else {
3968+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3969+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3970+ }
3971+ }
3972+
3973+ for (idx = 0; idx < 16; idx++) {
3974+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3975+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
3976+ }
3977+ }
3978+
3979+ seq_printf(s, "===Dummy delimiter insertion result===\n");
3980+ mac_val0 = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3981+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR6(band_idx));
3982+ mac_val1 = mt76_rr(dev, MT_DBG_MIB_M0DR7(band_idx));
3983+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
3984+ (mac_val0 & BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK),
3985+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK),
3986+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT,
3987+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK),
3988+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT);
3989+
3990+ return 0;
3991+}
3992+
3993+static int mt7915_mibinfo_band0(struct seq_file *s, void *data)
3994+{
3995+ mt7915_mibinfo_read_per_band(s, 0);
3996+ return 0;
3997+}
3998+
3999+static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
4000+{
4001+ mt7915_mibinfo_read_per_band(s, 1);
4002+ return 0;
4003+}
4004+
4005+static int mt7915_token_read(struct seq_file *s, void *data)
4006+{
4007+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4008+ int id, count = 0;
4009+ struct mt76_txwi_cache *txwi;
4010+
4011+ seq_printf(s, "Cut through token:\n");
4012+ spin_lock_bh(&dev->mt76.token_lock);
4013+ idr_for_each_entry(&dev->mt76.token, txwi, id) {
4014+ seq_printf(s, "%4d ", id);
4015+ count++;
4016+ if (count % 8 == 0)
4017+ seq_printf(s, "\n");
4018+ }
4019+ spin_unlock_bh(&dev->mt76.token_lock);
4020+ seq_printf(s, "\n");
4021+
4022+ return 0;
4023+}
4024+
4025+struct txd_l {
4026+ u32 txd_0;
4027+ u32 txd_1;
4028+ u32 txd_2;
4029+ u32 txd_3;
4030+ u32 txd_4;
4031+ u32 txd_5;
4032+ u32 txd_6;
4033+ u32 txd_7;
4034+} __packed;
4035+
4036+char *pkt_ft_str[] = {"cut_through", "store_forward", "cmd", "PDA_FW_Download"};
4037+char *hdr_fmt_str[] = {
4038+ "Non-80211-Frame",
4039+ "Command-Frame",
4040+ "Normal-80211-Frame",
4041+ "enhanced-80211-Frame",
4042+};
4043+/* TMAC_TXD_1.hdr_format */
4044+#define TMI_HDR_FT_NON_80211 0x0
4045+#define TMI_HDR_FT_CMD 0x1
4046+#define TMI_HDR_FT_NOR_80211 0x2
4047+#define TMI_HDR_FT_ENH_80211 0x3
4048+
4049+void mt7915_dump_tmac_info(u8 *tmac_info)
4050+{
4051+ struct txd_l *txd = (struct txd_l *)tmac_info;
4052+
4053+ printk("txd raw data: size=%d\n", MT_TXD_SIZE);
4054+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, tmac_info, MT_TXD_SIZE, false);
4055+
4056+ printk("TMAC_TXD Fields:\n");
4057+ printk("\tTMAC_TXD_0:\n");
4058+
4059+ /* DW0 */
4060+ /* TX Byte Count [15:0] */
4061+ printk("\t\tTxByteCnt = %ld\n", FIELD_GET(MT_TXD0_TX_BYTES, txd->txd_0));
4062+
4063+ /* PKT_FT: Packet Format [24:23] */
4064+ printk("\t\tpkt_ft = %ld(%s)\n",
4065+ FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0),
4066+ pkt_ft_str[FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0)]);
4067+
4068+ /* Q_IDX [31:25] */
4069+ printk("\t\tQueID =0x%lx\n", FIELD_GET(MT_TXD0_Q_IDX, txd->txd_0));
4070+
4071+ printk("\tTMAC_TXD_1:\n");
4072+
4073+ /* DW1 */
4074+ /* WLAN Indec [9:0] */
4075+ printk("\t\tWlan Index = %ld\n", FIELD_GET(MT_TXD1_WLAN_IDX, txd->txd_1));
4076+
4077+ /* VTA [10] */
4078+ printk("\t\tVTA = %d\n", ((txd->txd_1 & MT_TXD1_VTA) ? 1 : 0));
4079+
4080+ /* HF: Header Format [17:16] */
4081+ printk("\t\tHdrFmt = %ld(%s)\n",
4082+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1),
4083+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1) < 4 ?
4084+ hdr_fmt_str[FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)] : "N/A");
4085+
4086+ switch (FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)) {
4087+ case TMI_HDR_FT_NON_80211:
4088+ /* MRD [11], EOSP [12], RMVL [13], VLAN [14], ETYPE [15] */
4089+ printk("\t\t\tMRD = %d, EOSP = %d,\
4090+ RMVL = %d, VLAN = %d, ETYP = %d\n",
4091+ (txd->txd_1 & MT_TXD1_MRD) ? 1 : 0,
4092+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4093+ (txd->txd_1 & MT_TXD1_RMVL) ? 1 : 0,
4094+ (txd->txd_1 & MT_TXD1_VLAN) ? 1 : 0,
4095+ (txd->txd_1 & MT_TXD1_ETYP) ? 1 : 0);
4096+ break;
4097+ case TMI_HDR_FT_NOR_80211:
4098+ /* HEADER_LENGTH [15:11] */
4099+ printk("\t\t\tHeader Len = %ld(WORD)\n", FIELD_GET(MT_TXD1_HDR_INFO, txd->txd_1));
4100+ break;
4101+
4102+ case TMI_HDR_FT_ENH_80211:
4103+ /* EOSP [12], AMS [13] */
4104+ printk("\t\t\tEOSP = %d, AMS = %d\n",
4105+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4106+ (txd->txd_1 & MT_TXD1_AMS) ? 1 : 0);
4107+ break;
4108+ }
4109+
4110+ /* Header Padding [19:18] */
4111+ printk("\t\tHdrPad = %ld\n", FIELD_GET(MT_TXD1_HDR_PAD, txd->txd_1));
4112+
4113+ /* TID [22:20] */
4114+ printk("\t\tTID = %ld\n", FIELD_GET(MT_TXD1_TID, txd->txd_1));
4115+
4116+
4117+ /* UtxB/AMSDU_C/AMSDU [23] */
4118+ printk("\t\tamsdu = %d\n", ((txd->txd_1 & MT_TXD1_AMSDU) ? 1 : 0));
4119+
4120+ /* OM [29:24] */
4121+ printk("\t\town_mac = %ld\n", FIELD_GET(MT_TXD1_OWN_MAC, txd->txd_1));
4122+
4123+
4124+ /* TGID [30] */
4125+ printk("\t\tTGID = %d\n", ((txd->txd_1 & MT_TXD1_TGID) ? 1 : 0));
4126+
4127+
4128+ /* FT [31] */
4129+ printk("\t\tTxDFormatType = %d\n", (txd->txd_1 & MT_TXD1_LONG_FORMAT) ? 1 : 0);
4130+
4131+ printk("\tTMAC_TXD_2:\n");
4132+ /* DW2 */
4133+ /* Subtype [3:0] */
4134+ printk("\t\tsub_type = %ld\n", FIELD_GET(MT_TXD2_SUB_TYPE, txd->txd_2));
4135+
4136+ /* Type[5:4] */
4137+ printk("\t\tfrm_type = %ld\n", FIELD_GET(MT_TXD2_FRAME_TYPE, txd->txd_2));
4138+
4139+ /* NDP [6] */
4140+ printk("\t\tNDP = %d\n", ((txd->txd_2 & MT_TXD2_NDP) ? 1 : 0));
4141+
4142+ /* NDPA [7] */
4143+ printk("\t\tNDPA = %d\n", ((txd->txd_2 & MT_TXD2_NDPA) ? 1 : 0));
4144+
4145+ /* SD [8] */
4146+ printk("\t\tSounding = %d\n", ((txd->txd_2 & MT_TXD2_SOUNDING) ? 1 : 0));
4147+
4148+ /* RTS [9] */
4149+ printk("\t\tRTS = %d\n", ((txd->txd_2 & MT_TXD2_RTS) ? 1 : 0));
4150+
4151+ /* BM [10] */
4152+ printk("\t\tbc_mc_pkt = %d\n", ((txd->txd_2 & MT_TXD2_MULTICAST) ? 1 : 0));
4153+
4154+ /* B [11] */
4155+ printk("\t\tBIP = %d\n", ((txd->txd_2 & MT_TXD2_BIP) ? 1 : 0));
4156+
4157+ /* DU [12] */
4158+ printk("\t\tDuration = %d\n", ((txd->txd_2 & MT_TXD2_DURATION) ? 1 : 0));
4159+
4160+ /* HE [13] */
4161+ printk("\t\tHE(HTC Exist) = %d\n", ((txd->txd_2 & MT_TXD2_HTC_VLD) ? 1 : 0));
4162+
4163+ /* FRAG [15:14] */
4164+ printk("\t\tFRAG = %ld\n", FIELD_GET(MT_TXD2_FRAG, txd->txd_2));
4165+
4166+
4167+ /* Remaining Life Time [23:16]*/
4168+ printk("\t\tReamingLife/MaxTx time = %ld (unit: 64TU)\n",
4169+ FIELD_GET(MT_TXD2_MAX_TX_TIME, txd->txd_2));
4170+
4171+ /* Power Offset [29:24] */
4172+ printk("\t\tpwr_offset = %ld\n", FIELD_GET(MT_TXD2_POWER_OFFSET, txd->txd_2));
4173+
4174+ /* FRM [30] */
4175+ printk("\t\tfix rate mode = %d\n", (txd->txd_2 & MT_TXD2_FIXED_RATE) ? 1 : 0);
4176+
4177+ /* FR[31] */
4178+ printk("\t\tfix rate = %d\n", (txd->txd_2 & MT_TXD2_FIX_RATE) ? 1 : 0);
4179+
4180+
4181+ printk("\tTMAC_TXD_3:\n");
4182+
4183+ /* DW3 */
4184+ /* NA [0] */
4185+ printk("\t\tNoAck = %d\n", (txd->txd_3 & MT_TXD3_NO_ACK) ? 1 : 0);
4186+
4187+ /* PF [1] */
4188+ printk("\t\tPF = %d\n", (txd->txd_3 & MT_TXD3_PROTECT_FRAME) ? 1 : 0);
4189+
4190+ /* EMRD [2] */
4191+ printk("\t\tEMRD = %d\n", (txd->txd_3 & MT_TXD3_EMRD) ? 1 : 0);
4192+
4193+ /* EEOSP [3] */
4194+ printk("\t\tEEOSP = %d\n", (txd->txd_3 & MT_TXD3_EEOSP) ? 1 : 0);
4195+
4196+ /* DAS [4] */
4197+ printk("\t\tda_select = %d\n", (txd->txd_3 & MT_TXD3_DAS) ? 1 : 0);
4198+
4199+ /* TM [5] */
4200+ printk("\t\ttm = %d\n", (txd->txd_3 & MT_TXD3_TIMING_MEASURE) ? 1 : 0);
4201+
4202+ /* TX Count [10:6] */
4203+ printk("\t\ttx_cnt = %ld\n", FIELD_GET(MT_TXD3_TX_COUNT, txd->txd_3));
4204+
4205+ /* Remaining TX Count [15:11] */
4206+ printk("\t\tremain_tx_cnt = %ld\n", FIELD_GET(MT_TXD3_REM_TX_COUNT, txd->txd_3));
4207+
4208+ /* SN [27:16] */
4209+ printk("\t\tsn = %ld\n", FIELD_GET(MT_TXD3_SEQ, txd->txd_3));
4210+
4211+ /* BA_DIS [28] */
4212+ printk("\t\tba dis = %d\n", (txd->txd_3 & MT_TXD3_BA_DISABLE) ? 1 : 0);
4213+
4214+ /* Power Management [29] */
4215+ printk("\t\tpwr_mgmt = 0x%x\n", (txd->txd_3 & MT_TXD3_SW_POWER_MGMT) ? 1 : 0);
4216+
4217+ /* PN_VLD [30] */
4218+ printk("\t\tpn_vld = %d\n", (txd->txd_3 & MT_TXD3_PN_VALID) ? 1 : 0);
4219+
4220+ /* SN_VLD [31] */
4221+ printk("\t\tsn_vld = %d\n", (txd->txd_3 & MT_TXD3_SN_VALID) ? 1 : 0);
4222+
4223+
4224+ /* DW4 */
4225+ printk("\tTMAC_TXD_4:\n");
4226+
4227+ /* PN_LOW [31:0] */
4228+ printk("\t\tpn_low = 0x%lx\n", FIELD_GET(MT_TXD4_PN_LOW, txd->txd_4));
4229+
4230+
4231+ /* DW5 */
4232+ printk("\tTMAC_TXD_5:\n");
4233+
4234+ /* PID [7:0] */
4235+ printk("\t\tpid = %ld\n", FIELD_GET(MT_TXD5_PID, txd->txd_5));
4236+
4237+ /* TXSFM [8] */
4238+ printk("\t\ttx_status_fmt = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_FMT) ? 1 : 0);
4239+
4240+ /* TXS2M [9] */
4241+ printk("\t\ttx_status_2_mcu = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_MCU) ? 1 : 0);
4242+
4243+ /* TXS2H [10] */
4244+ printk("\t\ttx_status_2_host = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_HOST) ? 1 : 0);
4245+
4246+ /* ADD_BA [14] */
4247+ printk("\t\tADD_BA = %d\n", (txd->txd_5 & MT_TXD5_ADD_BA) ? 1 : 0);
4248+
4249+ /* MD [15] */
4250+ printk("\t\tMD = %d\n", (txd->txd_5 & MT_TXD5_MD) ? 1 : 0);
4251+
4252+ /* PN_HIGH [31:16] */
4253+ printk("\t\tpn_high = 0x%lx\n", FIELD_GET(MT_TXD5_PN_HIGH, txd->txd_5));
4254+
4255+ /* DW6 */
4256+ printk("\tTMAC_TXD_6:\n");
4257+
4258+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4259+ /* Fixed BandWidth mode [2:0] */
developer2aa1e642022-12-19 11:33:22 +08004260+ printk("\t\tbw = %ld\n",
4261+ FIELD_GET(MT_TXD6_BW, txd->txd_6) | (txd->txd_6 & MT_TXD6_FIXED_BW));
developer3fa816c2022-04-19 10:21:20 +08004262+
4263+ /* DYN_BW [3] */
4264+ printk("\t\tdyn_bw = %d\n", (txd->txd_6 & MT_TXD6_DYN_BW) ? 1 : 0);
4265+
4266+ /* ANT_ID [7:4] */
4267+ printk("\t\tant_id = %ld\n", FIELD_GET(MT_TXD6_ANT_ID, txd->txd_6));
4268+
4269+ /* SPE_IDX_SEL [10] */
4270+ printk("\t\tspe_idx_sel = %d\n", (txd->txd_6 & MT_TXD6_SPE_ID_IDX) ? 1 : 0);
4271+
4272+ /* LDPC [11] */
4273+ printk("\t\tldpc = %d\n", (txd->txd_6 & MT_TXD6_LDPC) ? 1 : 0);
4274+
4275+ /* HELTF Type[13:12] */
4276+ printk("\t\tHELTF Type = %ld\n", FIELD_GET(MT_TXD6_HELTF, txd->txd_6));
4277+
4278+ /* GI Type [15:14] */
4279+ printk("\t\tGI = %ld\n", FIELD_GET(MT_TXD6_SGI, txd->txd_6));
4280+
4281+ /* Rate to be Fixed [29:16] */
4282+ printk("\t\ttx_rate = 0x%lx\n", FIELD_GET(MT_TXD6_TX_RATE, txd->txd_6));
4283+ }
4284+
4285+ /* TXEBF [30] */
4286+ printk("\t\ttxebf = %d\n", (txd->txd_6 & MT_TXD6_TX_EBF) ? 1 : 0);
4287+
4288+ /* TXIBF [31] */
4289+ printk("\t\ttxibf = %d\n", (txd->txd_6 & MT_TXD6_TX_IBF) ? 1 : 0);
4290+
4291+ /* DW7 */
4292+ printk("\tTMAC_TXD_7:\n");
4293+
4294+ if ((txd->txd_1 & MT_TXD1_VTA) == 0) {
4295+ /* SW Tx Time [9:0] */
4296+ printk("\t\tsw_tx_time = %ld\n", FIELD_GET(MT_TXD7_TX_TIME, txd->txd_7));
4297+ } else {
4298+ /* TXD Arrival Time [9:0] */
4299+ printk("\t\tat = %ld\n", FIELD_GET(MT_TXD7_TAT, txd->txd_7));
4300+ }
4301+
4302+ /* HW_AMSDU_CAP [10] */
4303+ printk("\t\thw amsdu cap = %d\n",(txd->txd_7 & MT_TXD7_HW_AMSDU) ? 1 : 0);
4304+
4305+ /* SPE_IDX [15:11] */
4306+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4307+ printk("\t\tspe_idx = 0x%lx\n", FIELD_GET(MT_TXD7_SPE_IDX, txd->txd_7));
4308+ }
4309+
4310+ /* PSE_FID [27:16] */
4311+ printk("\t\tpse_fid = 0x%lx\n", FIELD_GET(MT_TXD7_PSE_FID, txd->txd_7));
4312+
4313+ /* Subtype [19:16] */
4314+ printk("\t\tpp_sub_type=%ld\n", FIELD_GET(MT_TXD7_SUB_TYPE, txd->txd_7));
4315+
4316+ /* Type [21:20] */
4317+ printk("\t\tpp_type=%ld\n", FIELD_GET(MT_TXD7_TYPE, txd->txd_7));
4318+
4319+ /* CTXD_CNT [25:23] */
4320+ printk("\t\tctxd cnt=0x%lx\n", FIELD_GET(MT_TXD7_CTXD_CNT, txd->txd_7));
4321+
4322+ /* CTXD [26] */
4323+ printk("\t\tctxd = %d\n", (txd->txd_7 & MT_TXD7_CTXD) ? 1 : 0);
4324+
4325+ /* I [28] */
4326+ printk("\t\ti = %d\n", (txd->txd_7 & MT_TXD7_IP_SUM) ? 1 : 0);
4327+
4328+ /* UT [29] */
4329+ printk("\t\tUT = %d\n", (txd->txd_7 & MT_TXD7_UDP_TCP_SUM) ? 1 : 0);
4330+
4331+ /* TXDLEN [31:30] */
4332+ printk("\t\t txd len= %ld\n", FIELD_GET(MT_TXD7_TXD_LEN, txd->txd_7));
4333+}
4334+
4335+
4336+static int mt7915_token_txd_read(struct seq_file *s, void *data)
4337+{
4338+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4339+ struct mt76_txwi_cache *t;
4340+ u8* txwi;
4341+
4342+ seq_printf(s, "\n");
4343+ spin_lock_bh(&dev->mt76.token_lock);
4344+
4345+ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
4346+
4347+ spin_unlock_bh(&dev->mt76.token_lock);
4348+ if (t != NULL) {
4349+ struct mt76_dev *mdev = &dev->mt76;
4350+ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
4351+ mt7915_dump_tmac_info((u8*) txwi);
4352+ seq_printf(s, "\n");
4353+ printk("[SKB]\n");
4354+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
4355+ seq_printf(s, "\n");
4356+ }
4357+ return 0;
4358+}
4359+
4360+static int mt7915_amsduinfo_read(struct seq_file *s, void *data)
4361+{
4362+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4363+ u32 ple_stat[8] = {0}, total_amsdu = 0;
4364+ u8 i;
4365+
4366+ for (i = 0; i < 8; i++)
4367+ ple_stat[i] = mt76_rr(dev, MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(i));
4368+
4369+ seq_printf(s, "TXD counter status of MSDU:\n");
4370+
4371+ for (i = 0; i < 8; i++)
4372+ total_amsdu += ple_stat[i];
4373+
4374+ for (i = 0; i < 8; i++) {
4375+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i + 1, ple_stat[i]);
4376+ if (total_amsdu != 0)
4377+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
4378+ else
4379+ seq_printf(s, "\n");
4380+ }
4381+
4382+ return 0;
4383+
4384+}
4385+
4386+static int mt7915_agginfo_read_per_band(struct seq_file *s, int band_idx)
4387+{
4388+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4389+ u32 value, idx, agg_rang_sel[15], ampdu_cnt[11], total_ampdu = 0;
4390+
4391+ seq_printf(s, "Band %d AGG Status\n", band_idx);
4392+ seq_printf(s, "===============================\n");
4393+ value = mt76_rr(dev, MT_DBG_AGG_AALCR0(band_idx));
4394+ seq_printf(s, "AC00 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4395+ seq_printf(s, "AC01 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4396+ seq_printf(s, "AC02 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4397+ seq_printf(s, "AC03 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4398+
4399+ value = mt76_rr(dev, MT_DBG_AGG_AALCR1(band_idx));
4400+ seq_printf(s, "AC10 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4401+ seq_printf(s, "AC11 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4402+ seq_printf(s, "AC12 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4403+ seq_printf(s, "AC13 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4404+
4405+ value = mt76_rr(dev, MT_DBG_AGG_AALCR2(band_idx));
4406+ seq_printf(s, "AC20 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4407+ seq_printf(s, "AC21 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4408+ seq_printf(s, "AC22 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4409+ seq_printf(s, "AC23 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4410+
4411+ value = mt76_rr(dev, MT_DBG_AGG_AALCR3(band_idx));
4412+ seq_printf(s, "AC30 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4413+ seq_printf(s, "AC31 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4414+ seq_printf(s, "AC32 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4415+ seq_printf(s, "AC33 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4416+
4417+ value = mt76_rr(dev, MT_DBG_AGG_AALCR4(band_idx));
4418+ seq_printf(s, "ALTX Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK, value));
4419+
4420+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 0));
4421+ seq_printf(s, "Winsize0 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE0_MASK, value));
4422+ seq_printf(s, "Winsize1 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE1_MASK, value));
4423+ seq_printf(s, "Winsize2 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE2_MASK, value));
4424+ seq_printf(s, "Winsize3 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE3_MASK, value));
4425+
4426+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 1));
4427+ seq_printf(s, "Winsize4 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE4_MASK, value));
4428+ seq_printf(s, "Winsize5 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE5_MASK, value));
4429+ seq_printf(s, "Winsize6 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE6_MASK, value));
4430+ seq_printf(s, "Winsize7 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE7_MASK, value));
4431+
4432+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 2));
4433+ seq_printf(s, "Winsize8 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE8_MASK, value));
4434+ seq_printf(s, "Winsize9 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE9_MASK, value));
4435+ seq_printf(s, "WinsizeA limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEA_MASK, value));
4436+ seq_printf(s, "WinsizeB limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEB_MASK, value));
4437+
4438+
4439+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 3));
4440+ seq_printf(s, "WinsizeC limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEC_MASK, value));
4441+ seq_printf(s, "WinsizeD limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZED_MASK, value));
4442+ seq_printf(s, "WinsizeE limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEE_MASK, value));
4443+
4444+ seq_printf(s, "===AMPDU Related Counters===\n");
4445+
4446+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 0));
4447+ agg_rang_sel[0] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK, value);
4448+ agg_rang_sel[1] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK, value);
4449+ agg_rang_sel[2] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK, value);
4450+ agg_rang_sel[3] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK, value);
4451+
4452+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 1));
4453+ agg_rang_sel[4] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK, value);
4454+ agg_rang_sel[5] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK, value);
4455+ agg_rang_sel[6] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK, value);
4456+ agg_rang_sel[7] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK, value);
4457+
4458+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 2));
4459+ agg_rang_sel[8] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK, value);
4460+ agg_rang_sel[9] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK, value);
4461+ agg_rang_sel[10] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK, value);
4462+ agg_rang_sel[11] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK, value);
4463+
4464+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 3));
4465+ agg_rang_sel[12] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK, value);
4466+ agg_rang_sel[13] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK, value);
4467+ agg_rang_sel[14] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK, value);
4468+
4469+ /* Need to add 1 after read from AGG_RANG_SEL CR */
4470+ for (idx = 0; idx < 15; idx++)
4471+ agg_rang_sel[idx]++;
4472+
4473+ ampdu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 0));
4474+ ampdu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 1));
4475+ ampdu_cnt[5] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 2));
4476+ ampdu_cnt[6] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 3));
4477+ ampdu_cnt[7] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 0));
4478+ ampdu_cnt[8] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 1));
4479+ ampdu_cnt[9] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 2));
4480+ ampdu_cnt[10] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 3));
4481+
4482+ seq_printf(s, "\tTx Agg Range: \t%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d\n",
4483+ agg_rang_sel[0],
4484+ agg_rang_sel[0] + 1, agg_rang_sel[1],
4485+ agg_rang_sel[1] + 1, agg_rang_sel[2],
4486+ agg_rang_sel[2] + 1, agg_rang_sel[3],
4487+ agg_rang_sel[3] + 1, agg_rang_sel[4],
4488+ agg_rang_sel[4] + 1, agg_rang_sel[5],
4489+ agg_rang_sel[5] + 1, agg_rang_sel[6],
4490+ agg_rang_sel[6] + 1, agg_rang_sel[7]);
4491+
4492+#define BIT_0_to_15_MASK 0x0000FFFF
4493+#define BIT_15_to_31_MASK 0xFFFF0000
4494+#define SHFIT_16_BIT 16
4495+
4496+ for (idx = 3; idx < 11; idx++)
4497+ total_ampdu = total_ampdu + (ampdu_cnt[idx] & BIT_0_to_15_MASK) + ((ampdu_cnt[idx] & BIT_15_to_31_MASK) >> SHFIT_16_BIT);
4498+
4499+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4500+ (ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK,
4501+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]),
4502+ (ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK,
4503+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]),
4504+ (ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK,
4505+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]),
4506+ (ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK,
4507+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]));
4508+
4509+ if (total_ampdu != 0) {
4510+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4511+ ((ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4512+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]) * 100 / total_ampdu,
4513+ ((ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4514+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]) * 100 / total_ampdu,
4515+ ((ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4516+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]) * 100 / total_ampdu,
4517+ ((ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4518+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]) * 100 / total_ampdu);
4519+ }
4520+
4521+ seq_printf(s, "\t\t\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~256\n",
4522+ agg_rang_sel[7] + 1, agg_rang_sel[8],
4523+ agg_rang_sel[8] + 1, agg_rang_sel[9],
4524+ agg_rang_sel[9] + 1, agg_rang_sel[10],
4525+ agg_rang_sel[10] + 1, agg_rang_sel[11],
4526+ agg_rang_sel[11] + 1, agg_rang_sel[12],
4527+ agg_rang_sel[12] + 1, agg_rang_sel[13],
4528+ agg_rang_sel[13] + 1, agg_rang_sel[14],
4529+ agg_rang_sel[14] + 1);
4530+
4531+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4532+ (ampdu_cnt[7]) & MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK,
4533+ FIELD_GET(MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK, ampdu_cnt[7]),
4534+ (ampdu_cnt[8]) & MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK,
4535+ FIELD_GET(MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK, ampdu_cnt[8]),
4536+ (ampdu_cnt[9]) & MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK,
4537+ FIELD_GET(MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK, ampdu_cnt[9]),
4538+ (ampdu_cnt[10]) & MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK,
4539+ FIELD_GET(MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK, ampdu_cnt[10]));
4540+
4541+ if (total_ampdu != 0) {
4542+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4543+ ((ampdu_cnt[7]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4544+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[7]) * 100 / total_ampdu,
4545+ ((ampdu_cnt[8]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4546+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[8]) * 100 / total_ampdu,
4547+ ((ampdu_cnt[9]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4548+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[9]) * 100 / total_ampdu,
4549+ ((ampdu_cnt[10]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4550+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[10]) * 100 / total_ampdu);
4551+ }
4552+
4553+ return 0;
4554+}
4555+
4556+static int mt7915_agginfo_read_band0(struct seq_file *s, void *data)
4557+{
4558+ mt7915_agginfo_read_per_band(s, 0);
4559+ return 0;
4560+}
4561+
4562+static int mt7915_agginfo_read_band1(struct seq_file *s, void *data)
4563+{
4564+ mt7915_agginfo_read_per_band(s, 1);
4565+ return 0;
4566+}
4567+
4568+/*usage: <en> <num> <len>
4569+ en: BIT(16) 0: sw amsdu 1: hw amsdu
4570+ num: GENMASK(15, 8) range 1-8
4571+ len: GENMASK(7, 0) unit: 256 bytes */
4572+static int mt7915_sta_tx_amsdu_set(void *data, u64 tx_amsdu)
4573+{
4574+/* UWTBL DW 6 */
4575+#define WTBL_AMSDU_LEN_MASK GENMASK(5, 0)
4576+#define WTBL_AMSDU_NUM_MASK GENMASK(8, 6)
4577+#define WTBL_AMSDU_EN_MASK BIT(9)
4578+#define UWTBL_HW_AMSDU_DW 6
4579+
4580+ struct mt7915_dev *dev = data;
4581+ u32 len = FIELD_GET(GENMASK(7, 0), tx_amsdu);
4582+ u32 num = FIELD_GET(GENMASK(15, 8), tx_amsdu);
4583+ u32 uwtbl;
4584+
developer9e5bcc52022-09-27 10:30:15 +08004585+ mt7915_mcu_set_amsdu_algo(dev, dev->wlan_idx, 0);
4586+
developer3fa816c2022-04-19 10:21:20 +08004587+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4588+ UWTBL_HW_AMSDU_DW, 1, &uwtbl);
4589+
4590+ if (len) {
4591+ uwtbl &= ~WTBL_AMSDU_LEN_MASK;
4592+ uwtbl |= FIELD_PREP(WTBL_AMSDU_LEN_MASK, len);
4593+ }
4594+
4595+ uwtbl &= ~WTBL_AMSDU_NUM_MASK;
4596+ uwtbl |= FIELD_PREP(WTBL_AMSDU_NUM_MASK, num);
4597+
4598+ if (tx_amsdu & BIT(16))
4599+ uwtbl |= WTBL_AMSDU_EN_MASK;
4600+
4601+ mt7915_wtbl_write_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4602+ UWTBL_HW_AMSDU_DW, uwtbl);
4603+
4604+ return 0;
4605+}
4606+
4607+DEFINE_DEBUGFS_ATTRIBUTE(fops_tx_amsdu, NULL,
4608+ mt7915_sta_tx_amsdu_set, "%llx\n");
4609+
4610+static int mt7915_red_enable_set(void *data, u64 en)
4611+{
4612+ struct mt7915_dev *dev = data;
4613+
4614+ return mt7915_mcu_set_red(dev, en);
4615+}
4616+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_en, NULL,
4617+ mt7915_red_enable_set, "%llx\n");
4618+
4619+static int mt7915_red_show_sta_set(void *data, u64 wlan_idx)
4620+{
4621+ struct mt7915_dev *dev = data;
4622+
4623+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4624+ MCU_WA_PARAM_RED_SHOW_STA,
4625+ wlan_idx, 0, true);
4626+
4627+ return 0;
4628+}
4629+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_show_sta, NULL,
4630+ mt7915_red_show_sta_set, "%llx\n");
4631+
4632+static int mt7915_red_target_dly_set(void *data, u64 delay)
4633+{
4634+ struct mt7915_dev *dev = data;
4635+
4636+ if (delay > 0 && delay <= 32767)
4637+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4638+ MCU_WA_PARAM_RED_TARGET_DELAY,
4639+ delay, 0, true);
4640+
4641+ return 0;
4642+}
4643+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_target_dly, NULL,
4644+ mt7915_red_target_dly_set, "%llx\n");
4645+
4646+static int
4647+mt7915_txpower_level_set(void *data, u64 val)
4648+{
4649+ struct mt7915_dev *dev = data;
4650+ struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
4651+ mt7915_mcu_set_txpower_level(&dev->phy, val);
4652+ if (ext_phy)
4653+ mt7915_mcu_set_txpower_level(ext_phy, val);
4654+
4655+ return 0;
4656+}
4657+
4658+DEFINE_DEBUGFS_ATTRIBUTE(fops_txpower_level, NULL,
4659+ mt7915_txpower_level_set, "%lld\n");
4660+
4661+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
4662+static int
4663+mt7915_wa_set(void *data, u64 val)
4664+{
4665+ struct mt7915_dev *dev = data;
4666+ u32 arg1, arg2, arg3;
4667+
4668+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4669+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4670+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4671+
4672+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), arg1, arg2, arg3, false);
4673+
4674+ return 0;
4675+}
4676+
4677+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7915_wa_set,
4678+ "0x%llx\n");
4679+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
4680+static int
4681+mt7915_wa_query(void *data, u64 val)
4682+{
4683+ struct mt7915_dev *dev = data;
4684+ u32 arg1, arg2, arg3;
4685+
4686+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4687+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4688+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4689+
4690+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), arg1, arg2, arg3, false);
4691+
4692+ return 0;
4693+}
4694+
4695+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7915_wa_query,
4696+ "0x%llx\n");
4697+/* set wa debug level
4698+ usage:
4699+ echo 0x[arg] > fw_wa_debug
4700+ bit0 : DEBUG_WIFI_TX
4701+ bit1 : DEBUG_CMD_EVENT
4702+ bit2 : DEBUG_RED
4703+ bit3 : DEBUG_WARN
4704+ bit4 : DEBUG_WIFI_RX
4705+ bit5 : DEBUG_TIME_STAMP
4706+ bit6 : DEBUG_TX_FREE_DONE_EVENT
4707+ bit12 : DEBUG_WIFI_TXD */
4708+static int
4709+mt7915_wa_debug(void *data, u64 val)
4710+{
4711+ struct mt7915_dev *dev = data;
4712+ u32 arg;
4713+
4714+ arg = FIELD_GET(GENMASK_ULL(15, 0), val);
4715+
4716+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(DEBUG), arg, 0, 0, false);
4717+
4718+ return 0;
4719+}
4720+
4721+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_debug, NULL, mt7915_wa_debug,
4722+ "0x%llx\n");
4723+
4724+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
4725+{
4726+ struct mt7915_dev *dev = phy->dev;
4727+ u32 device_id = (dev->mt76.rev) >> 16;
4728+ int i = 0;
4729+
4730+ for (i = 0; i < ARRAY_SIZE(dbg_reg_s); i++) {
4731+ if (device_id == dbg_reg_s[i].id) {
4732+ dev->dbg_reg = &dbg_reg_s[i];
4733+ break;
4734+ }
4735+ }
4736+
4737+ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
4738+
4739+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
4740+ &fops_fw_debug_module);
4741+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
4742+ &fops_fw_debug_level);
4743+
developerf32dabf2022-06-01 10:59:24 +08004744+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
4745+ mt7915_sta_info);
developer3fa816c2022-04-19 10:21:20 +08004746+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
4747+ mt7915_wtbl_read);
4748+ debugfs_create_devm_seqfile(dev->mt76.dev, "uwtbl_info", dir,
4749+ mt7915_uwtbl_read);
4750+
4751+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
4752+ mt7915_trinfo_read);
4753+
4754+ debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir,
4755+ mt7915_drr_info);
4756+
4757+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
4758+ mt7915_pleinfo_read);
4759+
4760+ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir,
4761+ mt7915_pseinfo_read);
4762+
4763+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
4764+ mt7915_mibinfo_band0);
4765+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
4766+ mt7915_mibinfo_band1);
4767+
4768+ debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx);
4769+ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir,
4770+ mt7915_token_read);
4771+ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
4772+ mt7915_token_txd_read);
4773+
4774+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
4775+ mt7915_amsduinfo_read);
4776+
4777+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
4778+ mt7915_agginfo_read_band0);
4779+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
4780+ mt7915_agginfo_read_band1);
4781+
4782+ debugfs_create_file("tx_amsdu", 0600, dir, dev, &fops_tx_amsdu);
4783+
4784+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
4785+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
4786+ debugfs_create_file("fw_wa_debug", 0600, dir, dev, &fops_wa_debug);
4787+
4788+ debugfs_create_file("red_en", 0600, dir, dev,
4789+ &fops_red_en);
4790+ debugfs_create_file("red_show_sta", 0600, dir, dev,
4791+ &fops_red_show_sta);
4792+ debugfs_create_file("red_target_dly", 0600, dir, dev,
4793+ &fops_red_target_dly);
4794+
4795+ debugfs_create_file("txpower_level", 0400, dir, dev,
4796+ &fops_txpower_level);
4797+
developeraace7f52022-06-24 13:40:42 +08004798+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
4799+
developer3fa816c2022-04-19 10:21:20 +08004800+ return 0;
4801+}
4802+#endif
4803diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
4804new file mode 100644
developerb8853042023-02-17 11:50:45 +08004805index 00000000..143dae26
developer3fa816c2022-04-19 10:21:20 +08004806--- /dev/null
4807+++ b/mt7915/mtk_mcu.c
4808@@ -0,0 +1,51 @@
4809+#include <linux/firmware.h>
4810+#include <linux/fs.h>
4811+#include<linux/inet.h>
4812+#include "mt7915.h"
4813+#include "mcu.h"
4814+#include "mac.h"
4815+
4816+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
4817+{
4818+ struct mt7915_dev *dev = phy->dev;
4819+ struct mt7915_sku_val {
4820+ u8 format_id;
4821+ u8 val;
4822+ u8 band;
4823+ u8 _rsv;
4824+ } __packed req = {
4825+ .format_id = 1,
developer2458e702022-12-13 15:52:04 +08004826+ .band = phy->mt76->band_idx,
developer3fa816c2022-04-19 10:21:20 +08004827+ .val = !!drop_level,
4828+ };
4829+ int ret;
4830+
4831+ ret = mt76_mcu_send_msg(&dev->mt76,
4832+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4833+ sizeof(req), true);
4834+ if (ret)
4835+ return ret;
4836+
4837+ req.format_id = 2;
4838+ if ((drop_level > 90 && drop_level < 100) || !drop_level)
4839+ req.val = 0;
4840+ else if (drop_level > 60 && drop_level <= 90)
4841+ /* reduce Pwr for 1 dB. */
4842+ req.val = 2;
4843+ else if (drop_level > 30 && drop_level <= 60)
4844+ /* reduce Pwr for 3 dB. */
4845+ req.val = 6;
4846+ else if (drop_level > 15 && drop_level <= 30)
4847+ /* reduce Pwr for 6 dB. */
4848+ req.val = 12;
4849+ else if (drop_level > 9 && drop_level <= 15)
4850+ /* reduce Pwr for 9 dB. */
4851+ req.val = 18;
4852+ else if (drop_level > 0 && drop_level <= 9)
4853+ /* reduce Pwr for 12 dB. */
4854+ req.val = 24;
4855+
4856+ return mt76_mcu_send_msg(&dev->mt76,
4857+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4858+ sizeof(req), true);
4859+}
4860diff --git a/tools/fwlog.c b/tools/fwlog.c
developerb8853042023-02-17 11:50:45 +08004861index e5d4a105..3d51d9ec 100644
developer3fa816c2022-04-19 10:21:20 +08004862--- a/tools/fwlog.c
4863+++ b/tools/fwlog.c
4864@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
4865 return path;
4866 }
4867
4868-static int mt76_set_fwlog_en(const char *phyname, bool en)
4869+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
4870 {
4871 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
4872
4873@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
4874 return 1;
4875 }
4876
4877- fprintf(f, "7");
4878+ if (en && val)
4879+ fprintf(f, "%s", val);
4880+ else if (en)
4881+ fprintf(f, "7");
4882+ else
4883+ fprintf(f, "0");
4884+
4885 fclose(f);
4886
4887 return 0;
4888@@ -76,6 +82,7 @@ static void handle_signal(int sig)
4889
4890 int mt76_fwlog(const char *phyname, int argc, char **argv)
4891 {
4892+#define BUF_SIZE 1504
4893 struct sockaddr_in local = {
4894 .sin_family = AF_INET,
4895 .sin_addr.s_addr = INADDR_ANY,
developerf32dabf2022-06-01 10:59:24 +08004896@@ -84,9 +91,10 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08004897 .sin_family = AF_INET,
4898 .sin_port = htons(55688),
4899 };
4900- char buf[1504];
4901+ char *buf = calloc(BUF_SIZE, sizeof(char));
developerf32dabf2022-06-01 10:59:24 +08004902+ FILE *logfile = NULL;
developer3fa816c2022-04-19 10:21:20 +08004903 int ret = 0;
4904- int yes = 1;
4905+ /* int yes = 1; */
4906 int s, fd;
4907
4908 if (argc < 1) {
developerf32dabf2022-06-01 10:59:24 +08004909@@ -99,19 +107,28 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4910 return 1;
4911 }
4912
4913+ if (argc == 3) {
4914+ fprintf(stdout, "start logging to file %s\n", argv[2]);
4915+ logfile = fopen(argv[2], "wb");
4916+ if (!logfile) {
4917+ perror("fopen");
4918+ return 1;
4919+ }
4920+ }
4921+
4922 s = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
4923 if (s < 0) {
4924 perror("socket");
developer3fa816c2022-04-19 10:21:20 +08004925 return 1;
4926 }
4927
4928- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
4929+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
4930 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
4931 perror("bind");
4932 return 1;
4933 }
4934
4935- if (mt76_set_fwlog_en(phyname, true))
4936+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
4937 return 1;
4938
4939 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
developerf32dabf2022-06-01 10:59:24 +08004940@@ -145,8 +162,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08004941 if (!r)
4942 continue;
4943
4944- if (len > sizeof(buf)) {
4945- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
4946+ if (len > BUF_SIZE) {
4947+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
4948 ret = 1;
4949 break;
4950 }
developerf32dabf2022-06-01 10:59:24 +08004951@@ -164,14 +181,19 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4952 break;
4953 }
4954
4955- /* send buf */
4956- sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
4957+ if (logfile)
4958+ fwrite(buf, 1, len, logfile);
4959+ else
4960+ /* send buf */
4961+ sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
4962 }
4963
developer3fa816c2022-04-19 10:21:20 +08004964 close(fd);
4965
4966 out:
4967- mt76_set_fwlog_en(phyname, false);
4968+ mt76_set_fwlog_en(phyname, false, NULL);
4969+ free(buf);
developerf32dabf2022-06-01 10:59:24 +08004970+ fclose(logfile);
developer3fa816c2022-04-19 10:21:20 +08004971
4972 return ret;
4973 }
4974--
developerb8853042023-02-17 11:50:45 +080049752.18.0
developer3fa816c2022-04-19 10:21:20 +08004976