- a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 1 year, 7 months ago
- 1a832bf Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration by Madhukar Pappireddy · 2 years, 2 months ago
- a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 3 months ago
- e026eea feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC by Sieu Mun Tang · 2 years, 2 months ago
- 8ebd237 intel: System Manager refactoring by Hadi Asyrafi · 4 years, 7 months ago
- 67cb0ea intel: Refactor reset manager driver by Hadi Asyrafi · 4 years, 7 months ago
- e73c511 intel: Enable bridge access in Intel platform by Hadi Asyrafi · 4 years, 9 months ago
- 3afb87a intel: Modify non secure access function by Hadi Asyrafi · 4 years, 9 months ago
- 966f282 intel: Fix memory calibration by Hadi Asyrafi · 4 years, 9 months ago
- 6f8a2b2 intel: Refactor common platform code [3/5] by Hadi Asyrafi · 4 years, 9 months ago
- 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · 4 years, 9 months ago
- 78fee35 intel: stratix10: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
- 309ac01 intel: Platform common code refactor by Hadi Asyrafi · 5 years ago
- 2b9a741 plat/intel: Fix SMPLSEL for MMC by Tien Hock, Loh · 5 years ago
- c0d4d93 intel: Enable watchdog timer on Intel S10 platform by Muhammad Hadi Asyrafi Abdul Halim · 5 years ago
- bd9e0a0 plat: intel: Improve ECC scrubbing performance by Tien Hock, Loh · 5 years ago
- ab34f74 plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform by Tien Hock, Loh · 5 years ago
- 3d1063e plat: intel: Fix faulty DDR calibration value by Loh Tien Hock · 5 years ago
- 59400a4 plat: intel: Add BL2 support for Stratix 10 SoC by Loh Tien Hock · 5 years ago