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git01.mediatek.com / filogic / atf / ece4c258266576da916ecf49983ee9d434e3eb7e / plat / intel / soc / stratix10
  1. d6cede3 Merge "feat(intel): enable SDMMC frontdoor load for ATF->Linux" into integration by Sandrine Bailleux · Fri Jan 19 11:08:14 2024 +0100
  2. c271599 feat(intel): enable query of fip offset on RSU by Mahesh Rao · Tue Aug 22 17:26:23 2023 +0800
  3. 961f7f1 Merge "feat(intel): support wipe DDR after calibration" into integration by Sandrine Bailleux · Wed Jan 10 14:49:27 2024 +0100
  4. 7a22863 Merge changes Id85b2541,I4d253e2f into integration by Sandrine Bailleux · Wed Jan 10 13:54:11 2024 +0100
  5. 477aef4 feat(intel): support wipe DDR after calibration by Jit Loon Lim · Mon Aug 14 13:12:01 2023 +0800
  6. 6e0e1b5 fix(intel): update system counter back to 400MHz by Sieu Mun Tang · Fri Dec 22 11:30:46 2023 +0800
  7. 60f7fb8 fix(intel): revert back to use L4 clock by Sieu Mun Tang · Fri Dec 22 11:12:17 2023 +0800
  8. 0cd0954 feat(intel): support QSPI ECC Linux for Stratix10 by Jit Loon Lim · Wed Oct 18 16:19:27 2023 +0800
  9. e7ab132 Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration by Sandrine Bailleux · Tue Dec 19 16:12:59 2023 +0100
  10. 8995426 Merge "fix(intel): bl31 overwrite OCRAM configuration" into integration by Sandrine Bailleux · Tue Dec 19 16:07:22 2023 +0100
  11. c5a3e3a feat(intel): enable SDMMC frontdoor load for ATF->Linux by Jit Loon Lim · Mon Oct 16 00:19:34 2023 +0800
  12. ffa06e7 fix(intel): fix hardcoded mpu frequency ticks by Jit Loon Lim · Fri Jul 07 17:15:26 2023 +0800
  13. 94f4418 Merge "feat(intel): restructure watchdog" into integration by Manish Pandey · Tue Nov 28 22:45:38 2023 +0100
  14. d5f8a23 fix(intel): bl31 overwrite OCRAM configuration by Jit Loon Lim · Thu Oct 19 11:04:51 2023 +0800
  15. f6186b2 feat(intel): increase bl2 size limit by Jit Loon Lim · Wed Sep 27 11:02:45 2023 +0800
  16. 6284537 feat(intel): restructure watchdog by Sieu Mun Tang · Fri Jun 09 23:33:36 2023 +0800
  17. 4c249f1 feat(intel): platform enablement for Agilex5 SoC FPGA by Jit Loon Lim · Wed May 17 12:26:11 2023 +0800
  18. 28c1c78 feat(intel): restructure sys mgr for S10/N5X by Jit Loon Lim · Wed May 17 12:26:11 2023 +0800
  19. 2be03c0 fix(tree): correct some typos by Elyes Haouas · Mon Feb 13 09:14:48 2023 +0100
  20. a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · Thu Dec 22 21:52:36 2022 +0800
  21. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · Thu Jun 23 18:05:02 2022 +0800
  22. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · Tue Nov 22 14:41:00 2022 -0600
  23. 55803a2 fix(intel): fix UART baud rate and clock by Sieu Mun Tang · Fri Jul 01 09:08:57 2022 +0800
  24. dce970c build(stratix10): platform changes for verifying gpt header crc by Rohit Ner · Wed May 11 03:18:31 2022 -0700
  25. b56c078 fix(intel): remove redundant NOC header declarations by Sieu Mun Tang · Fri May 13 11:14:08 2022 +0800
  26. 044ed48 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · Wed May 11 10:45:19 2022 +0800
  27. 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · Tue May 10 20:17:51 2022 +0200
  28. 1a832bf Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration by Madhukar Pappireddy · Fri May 06 19:33:59 2022 +0200
  29. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · Wed Apr 06 10:19:16 2022 +0800
  30. e026eea feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC by Sieu Mun Tang · Thu May 05 23:42:55 2022 +0800
  31. 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · Thu May 05 17:07:21 2022 +0800
  32. 2f94ca4 feat(intel): enable firewall for OCRAM in BL31 by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 05 22:40:46 2020 +0800
  33. 1205ef0 feat(intel): create source file for firewall configuration by Abdul Halim, Muhammad Hadi Asyrafi · Thu Aug 06 10:21:54 2020 +0800
  34. 616b5e7 fix(intel): refactor NOC header by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 05 22:12:23 2020 +0800
  35. b19ac61 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · Fri Aug 06 01:16:46 2021 +0800
  36. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · Mon Feb 28 15:24:59 2022 +0800
  37. dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · Mon Mar 07 12:13:04 2022 +0800
  38. f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · Mon Jun 29 12:15:27 2020 +0800
  39. 9f22cbf build(intel): initial commit for crypto driver by Sieu Mun Tang · Wed Mar 02 11:04:09 2022 +0800
  40. c353b0a Merge "fix(intel): assert if bl_mem_params is NULL pointer" into integration by Madhukar Pappireddy · Mon Feb 28 20:36:30 2022 +0100
  41. 380924d fix(intel): assert if bl_mem_params is NULL pointer by Siew Chin Lim · Sat Jun 12 13:25:05 2021 +0800
  42. ae4cd3a fix(intel): enable HPS QSPI access by default by Abdul Halim, Muhammad Hadi Asyrafi · Tue Oct 06 20:09:53 2020 +0800
  43. cf93158 plat/intel: do not keep mmc_device_info in stack by Yann Gautier · Mon Mar 22 14:21:54 2021 +0100
  44. 6474096 intel: mailbox: Ensure time out duration is predictive by Chee Hong Ang · Mon May 11 00:55:01 2020 +0800
  45. 2382b11 intel: clear 'PLAT_SEC_ENTRY' in early platform setup by Chee Hong Ang · Fri Apr 24 21:51:00 2020 +0800
  46. 0ae8d9a intel: platform: Include GICv2 makefile by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 19 14:50:01 2020 +0800
  47. 7dd4add Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration by Sandrine Bailleux · Fri Feb 28 10:51:49 2020 +0000
  48. 98b5a11 16550: Use generic console_t data structure by Andre Przywara · Sat Jan 25 00:58:35 2020 +0000
  49. 8d9e891 intel: Enable EMAC PHY in Intel FPGA platform by Tien Hock, Loh · Wed Oct 02 13:49:25 2019 +0800
  50. 7f95059 Merge "intel: Change boot source selection" into integration by Sandrine Bailleux · Wed Feb 12 15:54:02 2020 +0000
  51. 593c4c5 intel: Extend SiP service to support mailbox's RSU by Hadi Asyrafi · Tue Dec 17 19:22:17 2019 +0800
  52. 786db4d intel: Change boot source selection by Hadi Asyrafi · Mon Dec 30 16:00:30 2019 +0800
  53. 6aeb55d intel: Add function to check fpga readiness by Hadi Asyrafi · Tue Dec 24 14:43:22 2019 +0800
  54. 36a9f30 intel: Add bridge control for FPGA reconfig by Hadi Asyrafi · Tue Dec 24 10:42:52 2019 +0800
  55. 8ebd237 intel: System Manager refactoring by Hadi Asyrafi · Mon Dec 23 17:58:04 2019 +0800
  56. 67cb0ea intel: Refactor reset manager driver by Hadi Asyrafi · Mon Dec 23 13:25:33 2019 +0800
  57. e73c511 intel: Enable bridge access in Intel platform by Hadi Asyrafi · Mon Oct 21 16:35:08 2019 +0800
  58. 3afb87a intel: Modify non secure access function by Hadi Asyrafi · Mon Oct 21 16:27:29 2019 +0800
  59. 99361aa Merge "intel: Fix memory calibration" into integration by Manish Pandey · Tue Jan 14 18:28:43 2020 +0000
  60. 1fab9c3 Remove redundant declarations. by Madhukar Pappireddy · Thu Jan 02 16:32:41 2020 -0600
  61. 966f282 intel: Fix memory calibration by Hadi Asyrafi · Wed Oct 16 13:02:22 2019 +0800
  62. c8a281c intel: stratix10: Modify BL31 parameter handling by Hadi Asyrafi · Thu Oct 24 16:13:09 2019 +0800
  63. 0563a85 intel: stratix10: Enable uboot entrypoint support by Hadi Asyrafi · Tue Oct 22 12:59:32 2019 +0800
  64. 0c98ae8 intel: s10: Remove unused source code by Hadi Asyrafi · Thu Dec 12 10:46:09 2019 +0800
  65. 5ae876f intel: Refactor common platform code [5/5] by Hadi Asyrafi · Wed Oct 23 17:58:06 2019 +0800
  66. 4d9f395 intel: Refactor common platform code [4/5] by Hadi Asyrafi · Wed Oct 23 17:35:32 2019 +0800
  67. 6f8a2b2 intel: Refactor common platform code [3/5] by Hadi Asyrafi · Wed Oct 23 18:34:14 2019 +0800
  68. f0fa807 intel: Refactor common platform code [2/5] by Hadi Asyrafi · Wed Oct 23 17:02:55 2019 +0800
  69. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · Wed Oct 23 16:26:53 2019 +0800
  70. 78fee35 intel: stratix10: Fix reliance on hard coded clock information by Hadi Asyrafi · Tue Jul 30 22:18:17 2019 +0800
  71. 462c6c4 Merge changes from topic "intel-plat-refactor" into integration by Sandrine Bailleux · Wed Aug 07 14:20:01 2019 +0000
  72. 309ac01 intel: Platform common code refactor by Hadi Asyrafi · Thu Aug 01 14:48:39 2019 +0800
  73. acee488 intel: stratix10: Fix BL31 memory mapping by Hadi Asyrafi · Thu Aug 01 11:29:48 2019 +0800
  74. 6a240c7 intel: Platform common code refactor by Hadi Asyrafi · Thu Aug 01 15:21:20 2019 +0800
  75. c81e4f1 Merge changes from topic "jc/shift-overflow" into integration by Soby Mathew · Tue Jul 16 10:11:27 2019 +0000
  76. 8e5662d Update intel platform to not rely on undefined overflow behaviour by Justin Chadwell · Wed Jul 03 14:12:25 2019 +0100
  77. 2b9a741 plat/intel: Fix SMPLSEL for MMC by Tien Hock, Loh · Tue Jul 09 13:17:04 2019 +0800
  78. 636a913 Merge changes from topic "av/console-port" into integration by Paul Beesley · Fri Jun 28 11:04:02 2019 +0000
  79. 55828d5 Remove MULTI_CONSOLE_API flag and references to it by Ambroise Vincent · Thu Apr 04 09:13:28 2019 +0100
  80. c461add intel: Pull out common drivers into platform common by Hadi Asyrafi · Wed Jun 12 11:24:12 2019 +0800
  81. c0d4d93 intel: Enable watchdog timer on Intel S10 platform by Muhammad Hadi Asyrafi Abdul Halim · Tue Mar 19 17:59:06 2019 +0800
  82. 49ccacd Merge pull request #1874 from hadi-asyrafi/qspi_boot by Soby Mathew · Wed Mar 13 15:31:33 2019 +0000
  83. 2444bfa intel: QSPI boot enablement by Muhammad Hadi Asyrafi Abdul Halim · Fri Mar 08 19:02:33 2019 +0800
  84. 59d501e intel: Add driver for QSPI To support the enablement of QSPI booting by Muhammad Hadi Asyrafi Abdul Halim · Fri Mar 08 19:21:04 2019 +0800
  85. e408aa2 Merge pull request #1863 from thloh85-intel/mmc_fixes by Dimitris Papastamos · Fri Mar 08 09:41:22 2019 +0000
  86. b978c08 plat: intel: Add MMC OCR voltage information for initialization by Tien Hock, Loh · Fri Mar 08 09:26:24 2019 +0800
  87. b2bbe98 Merge pull request #1864 from hadi-asyrafi/mailbox_fix by Dimitris Papastamos · Thu Mar 07 13:58:12 2019 +0000
  88. b5ed794 intel: Mailbox service un-accessible by Muhammad Hadi Asyrafi Abdul Halim · Thu Mar 07 13:17:25 2019 +0800
  89. bd9e0a0 plat: intel: Improve ECC scrubbing performance by Tien Hock, Loh · Thu Mar 07 11:28:05 2019 +0800
  90. ab34f74 plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform by Tien Hock, Loh · Tue Feb 26 09:25:14 2019 +0800
  91. 3d1063e plat: intel: Fix faulty DDR calibration value by Loh Tien Hock · Wed Feb 13 14:39:31 2019 +0800
  92. 59400a4 plat: intel: Add BL2 support for Stratix 10 SoC by Loh Tien Hock · Mon Feb 04 16:17:24 2019 +0800