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git01.mediatek.com / filogic / atf / d4ff272f496daac8a08e3d092f5a9f2d1f0ba959 / include / lib / cpus / aarch32
  1. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · Tue Nov 22 14:41:00 2022 -0600
  2. 33bfc5e build: always prefix section names with `.` by Chris Kay · Tue Feb 14 11:30:04 2023 +0000
  3. 619d6fb feat(ti): set snoop-delayed exclusive handling on A72 cores by Andrew Davis · Thu Jan 12 09:32:33 2023 -0600
  4. b3fd376 feat(ti): set L2 cache ECC and and parity on A72 cores by Andrew Davis · Tue Jan 10 13:25:42 2023 -0600
  5. e7d7d11 feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles by Andrew Davis · Tue Jan 10 13:14:37 2023 -0600
  6. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · Tue Jul 09 13:49:11 2019 -0700
  7. 68a8d2b cpus: Fix Cortex-A12 MIDR mask by Heiko Stuebner · Fri Apr 05 14:44:33 2019 +0200
  8. 8cf9eef Cortex-A17: Implement workaround for errata 852421 by Ambroise Vincent · Thu Feb 28 16:23:53 2019 +0000
  9. 68b3812 Cortex-A15: Implement workaround for errata 827671 by Ambroise Vincent · Tue Mar 05 09:54:21 2019 +0000
  10. 1b0db76 Cortex-A57: Implement workaround for erratum 814670 by Ambroise Vincent · Thu Feb 21 16:35:07 2019 +0000
  11. 5e79cfe cpus: Add casts to all definitions in CPU headers by Antonio Nino Diaz · Mon Feb 11 13:34:15 2019 +0000
  12. 96f1631 cpus: Fix some incorrect definitions in CPU headers by Antonio Nino Diaz · Mon Feb 11 13:34:54 2019 +0000
  13. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  14. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
  15. 0980dce Make errata reporting mandatory for CPU files by Soby Mathew · Mon Sep 17 04:34:35 2018 +0100
  16. b561536 plat/arm: relocate the jump_if_cpu_midr macro. by Deepak Pandey · Thu Oct 11 13:44:43 2018 +0530
  17. dc9fab1 Remove all other deprecated interfaces and files by Antonio Nino Diaz · Tue Sep 25 09:39:51 2018 +0100
  18. 26b8589 Remove integrity check in declare_cpu_ops_base by Roberto Vargas · Fri May 04 10:54:33 2018 +0100
  19. 67762d9 Remove .struct directive by Roberto Vargas · Tue May 01 09:54:54 2018 +0100
  20. 4a284a4 aarch32: Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu May 17 14:41:13 2018 +0100
  21. 04285cf Merge pull request #1228 from dp-arm/dp/cve_2017_5715 by davidcunado-arm · Thu Jan 25 00:06:50 2018 +0000
  22. 8ca0af2 Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 by Dimitris Papastamos · Wed Jan 03 10:48:59 2018 +0000
  23. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · Mon Oct 30 14:43:43 2017 +0000
  24. 09d26a6 ARMv7: introduce Cortex-A12 by Etienne Carriere · Sun Nov 05 22:56:50 2017 +0100
  25. 010dd1f ARMv7: introduce Cortex-A17 by Etienne Carriere · Sun Nov 05 22:56:41 2017 +0100
  26. f2f7b91 ARMv7: introduce Cortex-A7 by Etienne Carriere · Sun Nov 05 22:56:34 2017 +0100
  27. 37f8cdc ARMv7: introduce Cortex-A5 by Etienne Carriere · Sun Nov 05 22:56:26 2017 +0100
  28. a1249e0 ARMv7: introduce Cortex-A9 by Etienne Carriere · Sun Nov 05 22:56:19 2017 +0100
  29. 4ece755 ARMv7: introduce Cortex-A15 by Etienne Carriere · Sun Nov 05 22:56:10 2017 +0100
  30. c3b4ca1 Cortex-A72: Implement workaround for erratum 859971 by Eleanor Bonnici · Wed Aug 02 18:33:41 2017 +0100
  31. 0c9bd27 Cortex-A57: Implement workaround for erratum 859972 by Eleanor Bonnici · Wed Aug 02 16:35:04 2017 +0100
  32. 41b61be CPU: Correct names of implementation-defined aux regs by Eleanor Bonnici · Wed Aug 09 16:42:40 2017 +0100
  33. b83e42b CPU: Make shifted constants unsigned by Eleanor Bonnici · Wed Aug 09 10:36:08 2017 +0100
  34. ac838c5 aarch32: Fix L2CTRL definition for Cortex A57 and A72 by Dimitris Papastamos · Tue Jun 13 12:33:39 2017 +0100
  35. 9c47a5a aarch32: Implement errata workarounds for Cortex A53 by Dimitris Papastamos · Mon Jun 05 13:37:25 2017 +0100
  36. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · Mon Jun 05 14:54:46 2017 -0700
  37. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  38. a9f776c AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor by Yatharth Kochar · Thu Nov 10 16:17:51 2016 +0000
  39. d5ec367 Report errata workaround status to console by Jeenu Viswambharan · Tue Jan 03 11:01:51 2017 +0000
  40. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  41. ee5eb80 Add provision to extend CPU operations at more levels by Jeenu Viswambharan · Fri Nov 18 12:58:28 2016 +0000
  42. a4c219a AArch32: Add support for ARM Cortex-A32 MPCore Processor by Yatharth Kochar · Tue Jul 12 15:47:03 2016 +0100
  43. f528faf AArch32: Common changes needed for BL1/BL2 by Yatharth Kochar · Tue Jun 28 16:58:26 2016 +0100
  44. 748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100