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git01.mediatek.com / filogic / atf / b6709b08d13b4e20c11afa77ccae9dec32202f8b / include / lib / cpus / aarch32
  1. 619d6fb feat(ti): set snoop-delayed exclusive handling on A72 cores by Andrew Davis · 1 year, 10 months ago
  2. b3fd376 feat(ti): set L2 cache ECC and and parity on A72 cores by Andrew Davis · 1 year, 10 months ago
  3. e7d7d11 feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles by Andrew Davis · 1 year, 10 months ago
  4. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · 5 years ago
  5. 68a8d2b cpus: Fix Cortex-A12 MIDR mask by Heiko Stuebner · 6 years ago
  6. 8cf9eef Cortex-A17: Implement workaround for errata 852421 by Ambroise Vincent · 6 years ago
  7. 68b3812 Cortex-A15: Implement workaround for errata 827671 by Ambroise Vincent · 6 years ago
  8. 1b0db76 Cortex-A57: Implement workaround for erratum 814670 by Ambroise Vincent · 6 years ago
  9. 5e79cfe cpus: Add casts to all definitions in CPU headers by Antonio Nino Diaz · 6 years ago
  10. 96f1631 cpus: Fix some incorrect definitions in CPU headers by Antonio Nino Diaz · 6 years ago
  11. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  12. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · 6 years ago
  13. 0980dce Make errata reporting mandatory for CPU files by Soby Mathew · 6 years ago
  14. b561536 plat/arm: relocate the jump_if_cpu_midr macro. by Deepak Pandey · 6 years ago
  15. dc9fab1 Remove all other deprecated interfaces and files by Antonio Nino Diaz · 6 years ago
  16. 26b8589 Remove integrity check in declare_cpu_ops_base by Roberto Vargas · 7 years ago
  17. 67762d9 Remove .struct directive by Roberto Vargas · 7 years ago
  18. 4a284a4 aarch32: Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · 6 years ago
  19. 04285cf Merge pull request #1228 from dp-arm/dp/cve_2017_5715 by davidcunado-arm · 7 years ago
  20. 8ca0af2 Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 by Dimitris Papastamos · 7 years ago
  21. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · 7 years ago
  22. 09d26a6 ARMv7: introduce Cortex-A12 by Etienne Carriere · 7 years ago
  23. 010dd1f ARMv7: introduce Cortex-A17 by Etienne Carriere · 7 years ago
  24. f2f7b91 ARMv7: introduce Cortex-A7 by Etienne Carriere · 7 years ago
  25. 37f8cdc ARMv7: introduce Cortex-A5 by Etienne Carriere · 7 years ago
  26. a1249e0 ARMv7: introduce Cortex-A9 by Etienne Carriere · 7 years ago
  27. 4ece755 ARMv7: introduce Cortex-A15 by Etienne Carriere · 7 years ago
  28. c3b4ca1 Cortex-A72: Implement workaround for erratum 859971 by Eleanor Bonnici · 7 years ago
  29. 0c9bd27 Cortex-A57: Implement workaround for erratum 859972 by Eleanor Bonnici · 7 years ago
  30. 41b61be CPU: Correct names of implementation-defined aux regs by Eleanor Bonnici · 7 years ago
  31. b83e42b CPU: Make shifted constants unsigned by Eleanor Bonnici · 7 years ago
  32. ac838c5 aarch32: Fix L2CTRL definition for Cortex A57 and A72 by Dimitris Papastamos · 7 years ago
  33. 9c47a5a aarch32: Implement errata workarounds for Cortex A53 by Dimitris Papastamos · 7 years ago
  34. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · 7 years ago
  35. fa3cf0b Use SPDX license identifiers by dp-arm · 8 years ago
  36. a9f776c AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor by Yatharth Kochar · 8 years ago
  37. d5ec367 Report errata workaround status to console by Jeenu Viswambharan · 8 years ago
  38. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · 8 years ago
  39. ee5eb80 Add provision to extend CPU operations at more levels by Jeenu Viswambharan · 8 years ago
  40. a4c219a AArch32: Add support for ARM Cortex-A32 MPCore Processor by Yatharth Kochar · 8 years ago
  41. f528faf AArch32: Common changes needed for BL1/BL2 by Yatharth Kochar · 8 years ago
  42. 748be1d AArch32: Add support in TF libraries by Soby Mathew · 9 years ago