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git01.mediatek.com / filogic / atf / 9bc79791b2c1181b424567a1ff8e874d2d894a4c / drivers / nxp / clk / s32cc / s32cc_early_clks.c
  1. d89e32f feat(nxp-clk): enable the DDR clock by Ghennadi Procopciuc · Tue Sep 17 11:22:30 2024 +0300
  2. 74dde09 feat(nxp-clk): setup the DDR PLL by Ghennadi Procopciuc · Mon Sep 09 10:24:35 2024 +0300
  3. eaf9cb1 feat(nxp-clk): refactor clock enablement by Ghennadi Procopciuc · Mon Sep 09 13:00:26 2024 +0300
  4. 0609bcd feat(nxp-clk): enable UART clock by Ghennadi Procopciuc · Tue Aug 06 13:25:51 2024 +0300
  5. 22f9474 feat(nxp-clk): add PERIPH PLL enablement by Ghennadi Procopciuc · Tue Aug 06 11:48:11 2024 +0300
  6. b3950cf feat(nxp-clk): enable the XBAR clock by Ghennadi Procopciuc · Mon Aug 05 16:51:03 2024 +0300
  7. 97a3090 refactor(nxp-clk): organize early clocks in groups by Ghennadi Procopciuc · Tue Jul 23 12:14:02 2024 +0300
  8. a080f78 feat(nxp-clk): enable the A53 clock by Ghennadi Procopciuc · Wed Jun 12 14:44:47 2024 +0300
  9. 9efc750 feat(nxp-clk): add ARM PLL ODIV enablement by Ghennadi Procopciuc · Wed Jun 12 14:30:30 2024 +0300
  10. b390c4d feat(nxp-clk): add ARM PLL enablement by Ghennadi Procopciuc · Wed Jun 12 14:21:39 2024 +0300
  11. a6a39e8 feat(nxp-clk): set rate for clock muxes by Ghennadi Procopciuc · Wed Jun 12 13:05:05 2024 +0300
  12. 907f654 feat(nxp-clk): set rate for PLL divider objects by Ghennadi Procopciuc · Wed Jun 12 12:00:15 2024 +0300
  13. e18cf33 feat(nxp-clk): set rate for PLL objects by Ghennadi Procopciuc · Wed Jun 12 11:55:32 2024 +0300
  14. 4e4786d feat(nxp-clk): set parent for ARM PLL and MC_CGM muxes by Ghennadi Procopciuc · Wed Jun 12 11:17:37 2024 +0300
  15. 9dee8e4 feat(nxp-clk): add FXOSC clock enablement by Ghennadi Procopciuc · Wed Jun 12 09:25:17 2024 +0300
  16. f648e5d feat(s32g274a): enable BL2 early clocks by Ghennadi Procopciuc · Wed Jun 12 09:07:16 2024 +0300