| commit | 0609bcd51453870783188c625fd30b322f073afc | [log] [tgz] |
|---|---|---|
| author | Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> | Tue Aug 06 13:25:51 2024 +0300 |
| committer | Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> | Tue Aug 20 16:28:56 2024 +0300 |
| tree | 787eb40269897fe87369755ac24b7bd9d7ce0e78 | |
| parent | 22f947468175532e4eb83ad29baa703ac9352666 [diff] |
feat(nxp-clk): enable UART clock Before this change, the internal oscillator clocked the UART with a frequency of 48MHz. With the necessary support added, the UART clock rate is increased to 125MHz by changing the clock source from FIRC to PERIPH PLL PHI3. Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>