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git01.mediatek.com / filogic / atf / 706b9fed31499362be91310111003646967d3063 / lib
  1. e5dce5d Merge "Coding guideline suggest not to use unsigned long" into integration by Sandrine Bailleux · Fri Nov 15 07:40:52 2019 +0000
  2. d091bf6 Merge "Fix white space errors + remove #if defined" into integration by Sandrine Bailleux · Wed Nov 13 16:22:52 2019 +0000
  3. eb2b2b6 Coding guideline suggest not to use unsigned long by Deepika Bhavnani · Tue Sep 03 21:06:17 2019 +0300
  4. 839a966 Merge "Disable stack protection explicitly" into integration by Paul Beesley · Tue Nov 12 13:20:46 2019 +0000
  5. cd9a943 Fix white space errors + remove #if defined by laurenw-arm · Fri Oct 11 15:45:24 2019 -0500
  6. da12924 Disable stack protection explicitly by Simon South · Sun Oct 20 13:54:32 2019 -0400
  7. bce728f xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config by Artsem Artsemenka · Thu Oct 17 13:51:27 2019 +0100
  8. 2fbce24 Merge "Neoverse N1 Errata Workaround 1542419" into integration by Soby Mathew · Mon Oct 07 12:05:26 2019 +0000
  9. a5b401b Merge "Fix the CAS spinlock implementation" into integration by Soby Mathew · Mon Oct 07 11:43:32 2019 +0000
  10. 94accd3 Neoverse N1 Errata Workaround 1542419 by laurenw-arm · Tue Aug 20 15:51:24 2019 -0500
  11. ad04201 Fix the CAS spinlock implementation by Soby Mathew · Wed Sep 25 14:03:41 2019 +0100
  12. efda055 Merge "TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U" into integration by Soby Mathew · Thu Oct 03 16:22:41 2019 +0000
  13. 3dd9f2b TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U by Alexei Fedorov · Tue Oct 01 13:58:23 2019 +0100
  14. 584410e Introducing support for Cortex-A65AE by Imre Kis · Mon Jul 22 14:36:30 2019 +0200
  15. 05e4d22 Introducing support for Cortex-A65 by Imre Kis · Thu Jul 18 14:30:03 2019 +0200
  16. d3dc940 Merge "Cortex_hercules: Add support for Hercules-AE" into integration by Soby Mathew · Tue Oct 01 20:15:23 2019 +0000
  17. fea97f7 Cortex_hercules: Add support for Hercules-AE by Artsem Artsemenka · Mon Sep 16 15:11:21 2019 +0100
  18. 14e508b Merge "AArch32: Disable Secure Cycle Counter" into integration by Soby Mathew · Fri Sep 27 10:55:15 2019 +0000
  19. 4bb606c Merge "Fix MTE support from causing unused variable warnings" into integration by Soby Mathew · Fri Sep 27 09:46:59 2019 +0000
  20. 9074dea AArch32: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 20 15:22:44 2019 +0100
  21. 33bd514 Adding new optional PSCI hook pwr_domain_on_finish_late by Madhukar Pappireddy · Mon Aug 12 18:31:33 2019 -0500
  22. 05e030e Fix MTE support from causing unused variable warnings by Justin Chadwell · Fri Sep 20 09:13:14 2019 +0100
  23. c3a1836 Merge changes from topic "db/unsigned_long" into integration by Sandrine Bailleux · Wed Sep 18 14:30:09 2019 +0000
  24. b0f2602 SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64 by Deepika Bhavnani · Tue Sep 03 21:08:51 2019 +0300
  25. 7c9a4e6 Merge "Refactor ARMv8.3 Pointer Authentication support code" into integration by Soby Mathew · Fri Sep 13 15:22:23 2019 +0000
  26. f41355c Refactor ARMv8.3 Pointer Authentication support code by Alexei Fedorov · Fri Sep 13 14:11:59 2019 +0100
  27. 4490ad2 Merge "Assert if power level value greater then PSCI_INVALID_PWR_LVL" into integration by Soby Mathew · Fri Sep 13 12:02:11 2019 +0000
  28. fd276b2 Merge "Unify type of "cpu_idx" across PSCI module." into integration by Soby Mathew · Fri Sep 13 11:35:56 2019 +0000
  29. 79ffab5 Unify type of "cpu_idx" across PSCI module. by Deepika Bhavnani · Tue Aug 27 00:32:24 2019 +0300
  30. 9180af2 Merge "libc: fix sparse warning for __assert()" into integration by Soby Mathew · Thu Sep 12 12:34:27 2019 +0000
  31. c235b12 Merge changes from topic "jc/mte_enable" into integration by Soby Mathew · Thu Sep 12 12:31:22 2019 +0000
  32. e412788 Zeus: apply the MSR SSBS instruction by John Tsichritzis · Tue Aug 13 10:28:25 2019 +0100
  33. 77389b2 libc: fix sparse warning for __assert() by Masahiro Yamada · Fri Jul 26 20:21:39 2019 +0900
  34. 523024c Assert if power level value greater then PSCI_INVALID_PWR_LVL by Deepika Bhavnani · Sat Aug 17 01:10:02 2019 +0300
  35. 1c7c13a Enable MTE support in both secure and non-secure worlds by Justin Chadwell · Thu Jul 18 14:25:33 2019 +0100
  36. c7a7cc3 Merge "AArch64: Disable Secure Cycle Counter" into integration by Paul Beesley · Fri Aug 23 11:26:57 2019 +0000
  37. 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 13 15:17:53 2019 +0100
  38. 5866c59 Merge "Fix for N1 1043202 Errata Workaround" into integration by Alexei Fedorov · Tue Aug 20 09:31:16 2019 +0000
  39. 9771749 Merge "Coverity fix: Remove GGC ignore -Warray-bounds" into integration by Paul Beesley · Tue Aug 20 09:25:00 2019 +0000
  40. 33e58f3 Fix for N1 1043202 Errata Workaround by laurenw-arm · Mon Aug 19 11:06:18 2019 -0500
  41. 6bd4666 Coverity fix: Remove GGC ignore -Warray-bounds by Deepika Bhavnani · Thu Aug 15 00:56:46 2019 +0300
  42. a95a589 FVP_Base_AEMv8A platform: Fix cache maintenance operations by Alexei Fedorov · Mon Jul 29 17:22:53 2019 +0100
  43. 1da61af Merge changes from topic "jc/coverity-fixes" into integration by Paul Beesley · Tue Aug 13 11:20:25 2019 +0000
  44. ca536f3 Fix Coverity #261967, Infinite loop by Justin Chadwell · Tue Jul 23 14:56:48 2019 +0100
  45. 0aab960 Fix Coverity #343008, Side affect in assertion by Justin Chadwell · Tue Jul 23 09:48:38 2019 +0100
  46. 72065ec Fix Coverity #342970, Uninitialized scalar variable by Justin Chadwell · Tue Jul 23 09:45:18 2019 +0100
  47. 8e0ef0f Switch AARCH32/AARCH64 to __aarch64__ by Julius Werner · Tue Jul 09 14:02:43 2019 -0700
  48. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · Tue Jul 09 13:49:11 2019 -0700
  49. db2ec85 Enable AMU for Cortex-Hercules by Balint Dobszay · Mon Jul 15 11:46:20 2019 +0200
  50. 33bc410 Merge "Romlib makefile refactoring and script rewriting" into integration by Soby Mathew · Thu Jul 25 12:54:59 2019 +0000
  51. 4047728 Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration by Soby Mathew · Thu Jul 25 09:04:21 2019 +0000
  52. f0081be Merge "Cortex_hercules: Introduce preliminary cpu support" into integration by Soby Mathew · Tue Jul 23 09:33:15 2019 +0000
  53. 4bf6afa Merge "Enable MTE support unilaterally for Normal World" into integration by Soby Mathew · Tue Jul 23 08:55:10 2019 +0000
  54. 2d137c5 Romlib makefile refactoring and script rewriting by Imre Kis · Tue Jul 09 18:30:58 2019 +0200
  55. dbba2b3 Introduce lightweight BL platform parameter library by Julius Werner · Fri May 24 20:31:15 2019 -0700
  56. f57f108 Cortex_hercules: Introduce preliminary cpu support by Louis Mayencourt · Tue May 14 11:00:45 2019 +0100
  57. c81e4f1 Merge changes from topic "jc/shift-overflow" into integration by Soby Mathew · Tue Jul 16 10:11:27 2019 +0000
  58. 830f0ad Enable MTE support unilaterally for Normal World by Soby Mathew · Fri Jul 12 09:23:38 2019 +0100
  59. 8294602 Update base code to not rely on undefined overflow behaviour by Justin Chadwell · Wed Jul 03 14:15:22 2019 +0100
  60. cc94264 Rename Cortex-Deimos to Cortex-A77 by Balint Dobszay · Wed Jul 03 13:02:56 2019 +0200
  61. cf12f26 Removing redundant ISB instructions by lauwal01 · Thu Jun 27 11:03:25 2019 -0500
  62. 644b6ed Workaround for Neoverse N1 erratum 1275112 by lauwal01 · Mon Jun 24 11:49:01 2019 -0500
  63. 00396bf Workaround for Neoverse N1 erratum 1262888 by lauwal01 · Mon Jun 24 11:47:30 2019 -0500
  64. 42771af Workaround for Neoverse N1 erratum 1262606 by lauwal01 · Mon Jun 24 11:44:58 2019 -0500
  65. 07c2a23 Workaround for Neoverse N1 erratum 1257314 by lauwal01 · Mon Jun 24 11:42:02 2019 -0500
  66. 197f14c Workaround for Neoverse N1 erratum 1220197 by lauwal01 · Mon Jun 24 11:38:53 2019 -0500
  67. e159044 Workaround for Neoverse N1 erratum 1207823 by lauwal01 · Mon Jun 24 11:35:37 2019 -0500
  68. f2adb13 Workaround for Neoverse N1 erratum 1165347 by lauwal01 · Mon Jun 24 11:32:40 2019 -0500
  69. 363ee3c Workaround for Neoverse N1 erratum 1130799 by lauwal01 · Mon Jun 24 11:28:34 2019 -0500
  70. bd555f4 Workaround for Neoverse N1 erratum 1073348 by lauwal01 · Mon Jun 24 11:23:50 2019 -0500
  71. 782f7e6 libc: fix memchr implementation by Ambroise Vincent · Fri Jun 07 11:19:45 2019 +0100
  72. 714d43a Merge "DSU: Apply erratum 936184 for Neoverse N1/E1" into integration by John Tsichritzis · Mon Jun 17 11:50:52 2019 +0000
  73. 8b8b13b DSU: Apply erratum 936184 for Neoverse N1/E1 by Louis Mayencourt · Mon Jun 10 16:43:39 2019 +0100
  74. 7901252 Merge changes from topic "jts/ti_fix" into integration by Soby Mathew · Mon Jun 10 09:40:25 2019 +0000
  75. 31df678 Merge "PSCI: Lookup list of parent nodes to lock only once" into integration by Soby Mathew · Mon Jun 10 09:39:23 2019 +0000
  76. 401cc1f Merge "Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703" into integration by John Tsichritzis · Fri Jun 07 15:20:45 2019 +0000
  77. 74e8978 PSCI: Lookup list of parent nodes to lock only once by Andrew F. Davis · Tue Jun 04 10:46:54 2019 -0400
  78. b934740 Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 by Andre Przywara · Mon May 20 14:57:06 2019 +0100
  79. c23d78c Merge "Introduce BTI support in ROMLIB" into integration by John Tsichritzis · Thu Jun 06 10:26:10 2019 +0000
  80. f4acb92 ti: k3: common: Remove coherency workaround for AM65x by Andrew F. Davis · Thu Apr 25 14:33:30 2019 -0400
  81. 7557c66 Apply compile-time check for AArch64-only cores by John Tsichritzis · Mon Jun 03 13:54:30 2019 +0100
  82. db737bb Merge "Cortex-A55: workarounds for errata 1221012" into integration by Paul Beesley · Wed May 29 11:29:12 2019 +0000
  83. b72fe7a Cortex-A55: workarounds for errata 1221012 by Ambroise Vincent · Tue May 28 09:52:48 2019 +0100
  84. 90f2e88 Add support for Branch Target Identification by Alexei Fedorov · Fri May 24 12:17:09 2019 +0100
  85. f6ea99b Introduce BTI support in ROMLIB by John Tsichritzis · Tue May 21 15:47:37 2019 +0100
  86. 70d4c9c romlib: Improve compilation flags definition by Louis Mayencourt · Mon Apr 29 16:35:30 2019 +0100
  87. 66e121a Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration by Soby Mathew · Thu May 16 08:33:56 2019 +0000
  88. a8722e9 Disable speculative loads only if SSBS is supported by Sami Mujawar · Fri May 10 14:28:37 2019 +0100
  89. 3a377b2 Remove .arch directives from spinlock.S by Alexei Fedorov · Fri May 10 16:55:16 2019 +0100
  90. 7fa6965 Merge changes from topic "sm/fix_a76_errata" into integration by Soby Mathew · Tue May 07 14:31:25 2019 +0000
  91. 16d006b Workaround for cortex-A76 errata 1286807 by Soby Mathew · Fri May 03 13:17:56 2019 +0100
  92. 1d3ba1c Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112 by Soby Mathew · Wed May 01 09:43:18 2019 +0100
  93. fe6df39 Add compile-time errors for HW_ASSISTED_COHERENCY flag by John Tsichritzis · Tue Mar 19 17:20:52 2019 +0000
  94. 845bb54 Merge changes from topic "lm/stack_protector" into integration by Soby Mathew · Tue Apr 30 15:43:21 2019 +0000
  95. 768bf0c Add support for default stack-protector flag by Louis Mayencourt · Tue Mar 26 16:59:26 2019 +0000
  96. 3e2ef2e Cortex-A53: Fix reporting of missing errata when not needed by Andrew F. Davis · Wed Apr 24 16:11:03 2019 -0400
  97. b58142b Neoverse N1: Forces cacheable atomic to near by Louis Mayencourt · Thu Apr 18 14:34:11 2019 +0100
  98. 4498b15 DSU: Implement workaround for errata 798953 by Louis Mayencourt · Tue Apr 09 16:29:01 2019 +0100
  99. 254f6f0 DSU: Small fix and reformat on errata framework by Louis Mayencourt · Tue Apr 09 14:11:06 2019 +0100
  100. 8a06127 Cortex-A35: Implement workaround for errata 855472 by Louis Mayencourt · Fri Apr 05 16:25:25 2019 +0100