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git01.mediatek.com / filogic / atf / 477aef46a17b4e889fc4ebb90361fd7b45131b30 / plat / intel / soc / agilex / include / agilex_clock_manager.h
  1. a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 1 year, 7 months ago
  2. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years ago
  3. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 3 months ago
  4. fcbc33d plat: intel: set DRVSEL and SMPLSEL for DWMMC by Tien Hock Loh · 4 years, 2 months ago
  5. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · 4 years, 9 months ago
  6. 56c4901 intel: agilex: Clear PLL lostlock bypass mode by Hadi Asyrafi · 5 years ago
  7. a813fed intel: agilex: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
  8. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · 5 years ago