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git01.mediatek.com / filogic / atf / 4699f5997dbd49f283902d893b8575b7f0292de1 / plat / intel / soc / stratix10 / soc
  1. a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 1 year, 11 months ago
  2. 1a832bf Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration by Madhukar Pappireddy · 2 years, 7 months ago
  3. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 8 months ago
  4. e026eea feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC by Sieu Mun Tang · 2 years, 7 months ago
  5. 8ebd237 intel: System Manager refactoring by Hadi Asyrafi · 5 years ago
  6. 67cb0ea intel: Refactor reset manager driver by Hadi Asyrafi · 5 years ago
  7. e73c511 intel: Enable bridge access in Intel platform by Hadi Asyrafi · 5 years ago
  8. 3afb87a intel: Modify non secure access function by Hadi Asyrafi · 5 years ago
  9. 966f282 intel: Fix memory calibration by Hadi Asyrafi · 5 years ago
  10. 6f8a2b2 intel: Refactor common platform code [3/5] by Hadi Asyrafi · 5 years ago
  11. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · 5 years ago
  12. 78fee35 intel: stratix10: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
  13. 309ac01 intel: Platform common code refactor by Hadi Asyrafi · 5 years ago
  14. 2b9a741 plat/intel: Fix SMPLSEL for MMC by Tien Hock, Loh · 5 years ago
  15. c0d4d93 intel: Enable watchdog timer on Intel S10 platform by Muhammad Hadi Asyrafi Abdul Halim · 6 years ago
  16. bd9e0a0 plat: intel: Improve ECC scrubbing performance by Tien Hock, Loh · 6 years ago
  17. ab34f74 plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform by Tien Hock, Loh · 6 years ago
  18. 3d1063e plat: intel: Fix faulty DDR calibration value by Loh Tien Hock · 6 years ago
  19. 59400a4 plat: intel: Add BL2 support for Stratix 10 SoC by Loh Tien Hock · 6 years ago