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git01.mediatek.com / filogic / atf / 3c42328bb2d65b2dd24c8d682a30b877dbd437c5 / include / bl31
  1. 669bf40 fix(bl31): allow use of EHF with S-EL2 SPMC by Raghu Krishnamurthy · Mon Jul 25 14:44:33 2022 -0700
  2. 4d37db8 feat(rme): add ENABLE_RME build option and support for RMM image by Zelalem Aweke · Sun Jul 11 18:33:20 2021 -0500
  3. 1c819c3 Use correct type when reading SCR register by Louis Mayencourt · Fri Jan 24 13:30:28 2020 +0000
  4. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · Tue Jul 09 13:49:11 2019 -0700
  5. 47a9064 BL31: Enable pointer authentication support by Antonio Nino Diaz · Thu Jan 31 11:01:26 2019 +0000
  6. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  7. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
  8. e0b757d Fix MISRA defects in BL31 common code by Antonio Nino Diaz · Fri Aug 24 16:30:29 2018 +0100
  9. 4b32e62 libc: Fix all includes in codebase by Antonio Nino Diaz · Thu Aug 16 16:52:57 2018 +0100
  10. 837cc9c EHF: MISRA fixes by Jeenu Viswambharan · Thu Aug 02 10:14:12 2018 +0100
  11. 32ceef5 SDEI: MISRA fixes by Jeenu Viswambharan · Thu Aug 02 10:14:12 2018 +0100
  12. d86cc5b RAS: Allow individual interrupt registration by Jeenu Viswambharan · Tue Dec 12 10:34:58 2017 +0000
  13. 9a7ce2f AArch64: Introduce RAS handling by Jeenu Viswambharan · Wed Apr 04 16:07:11 2018 +0100
  14. 96c7df0 AArch64: Introduce External Abort handling by Jeenu Viswambharan · Thu Nov 30 12:54:15 2017 +0000
  15. b8d8145 Merge pull request #1282 from robertovargas-arm/misra-changes by davidcunado-arm · Wed Feb 28 18:53:30 2018 +0000
  16. 0571270 Fix MISRA rule 8.4 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  17. 777dd43 Fix MISRA rule 8.3 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  18. eeb353c EHF: Introduce preempted return code parameter to ehf_allow_ns_preemption() by Jeenu Viswambharan · Mon Jan 22 12:29:12 2018 +0000
  19. f4194ee Deprecate one EL3 interrupt routing model with EL3 exception handling by Jeenu Viswambharan · Wed Jan 10 15:00:20 2018 +0000
  20. 6c6f24d BL31: Program Priority Mask for SMC handling by Jeenu Viswambharan · Wed Oct 04 12:21:34 2017 +0100
  21. 10a6727 BL31: Introduce Exception Handling Framework by Jeenu Viswambharan · Fri Sep 22 08:32:10 2017 +0100
  22. aeb267c GIC: Allow specifying interrupt properties by Jeenu Viswambharan · Fri Sep 22 08:32:09 2017 +0100
  23. dce70b3 GIC: Add API to set interrupt routing by Jeenu Viswambharan · Fri Sep 22 08:32:09 2017 +0100
  24. c6a11f6 include: add U()/ULL() macros for constants by Varun Wadekar · Thu May 25 18:04:48 2017 -0700
  25. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  26. d019487 Introduce PSCI Library Interface by Soby Mathew · Fri Apr 29 19:01:30 2016 +0100
  27. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000
  28. 24ab34f Fix coding guideline warnings by Soby Mathew · Tue May 03 17:11:42 2016 +0100
  29. a0fedc4 Rework type usage in Trusted Firmware by Soby Mathew · Thu Jun 16 14:52:04 2016 +0100
  30. 241ec6c Add optional PSCI STAT residency & count functions by Yatharth Kochar · Mon May 09 18:26:35 2016 +0100
  31. 6a81641 PSCI: Add pwr_domain_pwr_down_wfi() hook in plat_psci_ops by Soby Mathew · Wed Apr 27 14:46:28 2016 +0100
  32. 46dd170 Remove direct usage of __attribute__((foo)) by Soren Brinkmann · Thu Jan 14 10:11:05 2016 -0800
  33. 7162afa Use designated initialization in DECLARE_RT_SVC macro by Soby Mathew · Tue Jan 12 10:28:42 2016 +0000
  34. f4119ec Miscellaneous doc fixes for v1.2 by Sandrine Bailleux · Thu Dec 17 13:58:58 2015 +0000
  35. 6c0566c Move context management code to common location by Yatharth Kochar · Fri Oct 02 17:56:48 2015 +0100
  36. 58e32d1 Enable support for EL3 interrupt in IMF by Soby Mathew · Mon Nov 23 13:58:45 2015 +0000
  37. a31c9f3 Merge pull request #390 from vikramkanigiri/at/unify_bakery_locks_v2 by Achin Gupta · Mon Sep 14 21:49:10 2015 +0100
  38. e466c9f Re-design bakery lock memory allocation and algorithm by Andrew Thoelke · Thu Sep 10 11:39:36 2015 +0100
  39. 9a0ff9b Pass the target suspend level to SPD suspend hooks by Achin Gupta · Mon Sep 07 20:43:27 2015 +0100
  40. 011ca18 PSCI: Rework generic code to conform to coding guidelines by Soby Mathew · Wed Jul 29 17:05:03 2015 +0100
  41. f1f97a1 PSCI: Fix the return code for invalid entrypoint by Soby Mathew · Wed Jul 15 12:13:26 2015 +0100
  42. 3700a92 PSCI: Migrate TF to the new platform API and CM helpers by Soby Mathew · Mon Jul 13 11:21:11 2015 +0100
  43. 70716d6 PSCI: Add deprecated API for SPD when compatibility is disabled by Soby Mathew · Mon Jul 13 16:26:11 2015 +0100
  44. 981487a PSCI: Switch to the new PSCI frameworks by Soby Mathew · Mon Jul 13 14:10:57 2015 +0100
  45. 49473e4 PSCI: Implement platform compatibility layer by Soby Mathew · Wed Jun 10 13:49:59 2015 +0100
  46. 574d685 PSCI: Unify warm reset entry points by Sandrine Bailleux · Thu Jun 11 10:46:48 2015 +0100
  47. 85dbf5a PSCI: Add framework to handle composite power states by Soby Mathew · Tue Apr 07 12:16:56 2015 +0100
  48. 9d754f6 PSCI: Introduce new platform interface to describe topology by Soby Mathew · Wed Apr 08 17:42:06 2015 +0100
  49. b0082d2 PSCI: Introduce new platform and CM helper APIs by Soby Mathew · Thu Apr 09 13:40:55 2015 +0100
  50. 3a9e8bf PSCI: Remove references to affinity based power management by Soby Mathew · Tue May 05 16:33:16 2015 +0100
  51. 6b8b302 PSCI: Invoke PM hooks only for the highest level by Soby Mathew · Tue Jun 30 11:00:24 2015 +0100
  52. 991d42c PSCI: Create new directory to implement new frameworks by Soby Mathew · Mon Jun 29 16:30:12 2015 +0100
  53. 9616838 PSCI: Add SYSTEM_SUSPEND API support by Soby Mathew · Wed Dec 17 14:47:57 2014 +0000
  54. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · Thu Jan 29 18:27:38 2015 +0000
  55. 47903c0 Demonstrate model for routing IRQs to EL3 by Soby Mathew · Tue Jan 13 15:48:26 2015 +0000
  56. 1df077b Increment the PSCI VERSION to 1.0 by Soby Mathew · Thu Jan 15 11:49:58 2015 +0000
  57. 6cdddaf Implement PSCI_FEATURES API by Soby Mathew · Wed Jan 07 11:10:22 2015 +0000
  58. 110fe36 Rework the PSCI migrate APIs by Soby Mathew · Thu Oct 23 10:35:34 2014 +0100
  59. 74e52a7 Validate power_state and entrypoint when executing PSCI calls by Soby Mathew · Thu Oct 02 16:56:51 2014 +0100
  60. f512157 Save 'power_state' early in PSCI CPU_SUSPEND call by Soby Mathew · Tue Sep 30 11:19:51 2014 +0100
  61. ffb4ab1 Remove `ns_entrypoint` and `mpidr` from parameters in pm_ops by Soby Mathew · Fri Sep 26 15:08:52 2014 +0100
  62. 523d633 Move bakery algorithm implementation out of coherent memory by Soby Mathew · Thu Jan 08 18:02:19 2015 +0000
  63. 7d861ea Invalidate the dcache after initializing cpu-ops by Soby Mathew · Tue Nov 18 10:14:14 2014 +0000
  64. c704cbc Introduce framework for CPU specific operations by Soby Mathew · Thu Aug 14 11:33:56 2014 +0100
  65. 56bcdc2 Miscellaneous PSCI code cleanups by Achin Gupta · Mon Jul 28 00:15:23 2014 +0100
  66. f6b9e99 Add APIs to preserve highest affinity level in OFF state by Achin Gupta · Thu Jul 31 11:19:11 2014 +0100
  67. f3ccbab Add PSCI service specific per-CPU data by Achin Gupta · Fri Jul 25 14:52:47 2014 +0100
  68. e4b9fa4 Add macro to flush per-CPU data by Achin Gupta · Fri Jul 25 14:47:05 2014 +0100
  69. 4dc4a47 Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs by Juan Castillo · Tue Aug 12 11:17:06 2014 +0100
  70. 2ed46e9 Optimize EL3 register state stored in cpu_context structure by Soby Mathew · Fri Jul 04 16:02:26 2014 +0100
  71. 45c31c4 Merge pull request #172 from soby-mathew/sm/asm_assert by danh-arm · Mon Jul 28 14:28:40 2014 +0100
  72. c1adbbc Rework the crash reporting in BL3-1 to use less stack by Soby Mathew · Wed Jun 25 10:07:40 2014 +0100
  73. e1aa516 Remove coherent stack usage from the warm boot path by Achin Gupta · Thu Jun 26 09:58:52 2014 +0100
  74. 258e94f Allow FP register context to be optional at build time by Juan Castillo · Wed Jun 25 17:26:36 2014 +0100
  75. 2d55240 Remove all checkpatch errors from codebase by Juan Castillo · Fri Jun 13 17:05:10 2014 +0100
  76. 56f4470 Correctly dimension the PSCI aff_map_node array by Andrew Thoelke · Fri Jun 20 00:36:14 2014 +0100
  77. 4e12607 Initialise CPU contexts from entry_point_info by Andrew Thoelke · Wed Jun 04 21:10:52 2014 +0100
  78. 40110f7 Merge pull request #138 from athoelke/at/cpu-context by danh-arm · Mon Jun 23 13:10:00 2014 +0100
  79. 4d2d553 Remove early_exceptions from BL3-1 by Andrew Thoelke · Mon Jun 02 12:38:12 2014 +0100
  80. c02dbd6 Move CPU context pointers into cpu_data by Andrew Thoelke · Mon Jun 02 10:00:25 2014 +0100
  81. 8c28fe0 Per-cpu data cache restructuring by Andrew Thoelke · Mon Jun 02 11:40:35 2014 +0100
  82. a2f6553 Provide cm_get/set_context() for current CPU by Andrew Thoelke · Wed May 14 17:09:32 2014 +0100
  83. 701fea7 Further renames of platform porting functions by Dan Handley · Tue May 27 16:17:21 2014 +0100
  84. 7ce42df Move BL porting functions into platform.h by Dan Handley · Thu May 15 14:11:36 2014 +0100
  85. 60b13e3 Remove unused data declarations by Dan Handley · Wed May 14 15:13:16 2014 +0100
  86. a17fefa Remove extern keyword from function declarations by Dan Handley · Wed May 14 12:38:32 2014 +0100
  87. 077193f Merge pull request #105 from athoelke:sm/support_normal_irq_in_tsp-v2 by Andrew Thoelke · Fri May 23 11:00:04 2014 +0100
  88. 58484d4 Merge pull request #102 from achingupta:ag/tf-issues#104-v2 by Andrew Thoelke · Fri May 23 11:00:04 2014 +0100
  89. 29c7ae1 Merge pull request #99 from vikramkanigiri:vk/tf-issues-133_V3 by Andrew Thoelke · Fri May 23 11:00:04 2014 +0100
  90. 1c5630d Merge pull request #67 from achingupta:ag/psci_standby_bug_fix by Andrew Thoelke · Fri May 23 11:00:04 2014 +0100
  91. 9f71f70 Non-Secure Interrupt support during Standard SMC processing in TSP by Soby Mathew · Fri May 09 20:49:17 2014 +0100
  92. aeaab68 Add S-EL1 interrupt handling support in the TSPD by Achin Gupta · Fri May 09 13:21:31 2014 +0100
  93. 9cf2bb7 Introduce interrupt handling framework in BL3-1 by Achin Gupta · Fri May 09 11:07:09 2014 +0100
  94. 191e86e Introduce interrupt registration framework in BL3-1 by Achin Gupta · Fri May 09 10:03:15 2014 +0100
  95. 27b895e Add context library API to change a bit in SCR_EL3 by Achin Gupta · Sun May 04 18:38:28 2014 +0100
  96. d8c9d26 Rework memory information passing to BL3-x images by Vikram Kanigiri · Fri May 16 18:48:12 2014 +0100
  97. da56743 Populate BL31 input parameters as per new spec by Vikram Kanigiri · Tue Apr 15 18:08:08 2014 +0100
  98. b058556 Merge pull request #78 from jeenuv:tf-issues-148 by Andrew Thoelke · Mon May 19 12:54:05 2014 +0100
  99. d1b6015 Add build configuration for timer save/restore by Jeenu Viswambharan · Mon May 12 15:28:47 2014 +0100
  100. 5e5c207 Rework BL3-1 unhandled exception handling and reporting by Soby Mathew · Mon Apr 07 15:28:55 2014 +0100