| commit | 191e86e3d7773895da24db417bccd411773dfaed | [log] [tgz] |
|---|---|---|
| author | Achin Gupta <achin.gupta@arm.com> | Fri May 09 10:03:15 2014 +0100 |
| committer | Achin Gupta <achin.gupta@arm.com> | Thu May 22 17:46:56 2014 +0100 |
| tree | e3085f1eb529fd97b66f9deccf56bc0307f2b6cd | |
| parent | 27b895e91e6122d4f182e704c5480eb6f1a2c55e [diff] |
Introduce interrupt registration framework in BL3-1 This patch introduces a framework for registering interrupts routed to EL3. The interrupt routing model is governed by the SCR_EL3.IRQ and FIQ bits and the security state an interrupt is generated in. The framework recognizes three type of interrupts depending upon which exception level and security state they should be handled in i.e. Secure EL1 interrupts, Non-secure interrupts and EL3 interrupts. It provides an API and macros that allow a runtime service to register an handler for a type of interrupt and specify the routing model. The framework validates the routing model and uses the context management framework to ensure that it is applied to the SCR_EL3 prior to entry into the target security state. It saves the handler in internal data structures. An API is provided to retrieve the handler when an interrupt of a particular type is asserted. Registration is expected to be done once by the primary CPU. The same handler and routing model is used for all CPUs. Support for EL3 interrupts will be added to the framework in the future. A makefile flag has been added to allow the FVP port choose between ARM GIC v2 and v3 support in EL3. The latter version is currently unsupported. A framework for handling interrupts in BL3-1 will be introduced in subsequent patches. The default routing model in the absence of any handlers expects no interrupts to be routed to EL3. Change-Id: Idf7c023b34fcd4800a5980f2bef85e4b5c29e649
ARM Trusted Firmware provides a reference implementation of secure world software for ARMv8-A, including Exception Level 3 (EL3) software. This release focuses on support for ARM's [Fixed Virtual Platforms (FVPs)] FVP.
The intent is to provide a reference implementation of various ARM interface standards, such as the Power State Coordination Interface (PSCI), Trusted Board Boot Requirements (TBBR) and [Secure Monitor] TEE-SMC code. As far as possible the code is designed for reuse or porting to other ARMv8-A model and hardware platforms.
This release builds on the previous source code release, which has been available in source and binary form since the [Linaro AArch64 OpenEmbedded 13.11 Engineering Build] AArch64 LEB. These support the Base FVP platform models from ARM.
ARM will continue development in collaboration with interested parties to provide a full reference implementation of PSCI, TBBR and Secure Monitor code to the benefit of all developers working with ARMv8-A TrustZone software.
The software is provided under a BSD 3-Clause license. Certain source files are derived from FreeBSD code: the original license is included in these source files.
This release is an incomplete implementation of the Trusted Firmware. Only limited functionality is provided at present and it has not been optimized or subjected to extended robustness or stress testing.
Initial implementation of a subset of the Trusted Board Boot Requirements Platform Design Document (PDD). This includes packaging the various firmware images into a Firmware Image Package (FIP) to be loaded from non-volatile storage.
Initializes the secure world (for example, exception vectors, control registers, GIC and interrupts for the platform), before transitioning into the normal world.
Supports both GICv2 and GICv3 initialization for use by normal world software.
Starts the normal world at the highest available Exception Level: EL2 if available, otherwise EL1.
Handles SMCs (Secure Monitor Calls) conforming to the [SMC Calling Convention PDD] SMCCC using an EL3 runtime services framework.
Handles SMCs relating to the [Power State Coordination Interface PDD] PSCI for the Secondary CPU Boot, CPU hotplug and CPU idle use-cases.
A Test Secure-EL1 Payload and Dispatcher to demonstrate Secure Monitor functionality such as world switching and EL1 context management. This also demonstrates Secure-EL1 interaction with PSCI. Some of this functionality is provided in library form for re-use by other Secure-EL1 Payload Dispatchers.
For a full list of updated functionality and implementation details, please see the User Guide. The Change Log provides details of changes made since the last release.
This release of the Trusted Firmware has been tested on the following ARM FVPs (64-bit versions only):
Foundation_v8 (Version 2.0, Build 0.8.5206)FVP_Base_AEMv8A-AEMv8A (Version 5.4, Build 0.8.5405)FVP_Base_Cortex-A57x4-A53x4 (Version 5.4, Build 0.8.5405)FVP_Base_Cortex-A57x1-A53x1 (Version 5.4, Build 0.8.5405)The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from ARM: see [www.arm.com/fvp] FVP.
Complete implementation of the PSCI specification.
Secure memory, Secure interrupts and support for other types of Secure-EL1 Payloads.
Booting the firmware from a Virtio block device.
Completing the currently experimental GICv3 support.
For a full list of detailed issues in the current code, please see the Change Log and the GitHub issue tracker.
Get the Trusted Firmware source code from GitHub.
See the User Guide for instructions on how to install, build and use the Trusted Firmware with the ARM FVPs.
See the Firmware Design for information on how the ARM Trusted Firmware works.
See the Porting Guide as well for information about how to use this software on another ARMv8-A platform.
See the Contributing Guidelines for information on how to contribute to this project and the Acknowledgements file for a list of contributors to the project.
ARM welcomes any feedback on the Trusted Firmware. Please send feedback using the GitHub issue tracker.
ARM licensees may contact ARM directly via their partner managers.
Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.