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git01.mediatek.com / filogic / atf / 20ce06c4daea5619329b4af9bf38f60b05ea8228 / plat / intel / soc / agilex
  1. bd8da63 feat(intel): extending to support SMMU in FCS by Sieu Mun Tang · Wed Sep 28 15:58:28 2022 +0800
  2. b9ae467 feat(intel): setup FPGA interface for Agilex by Jit Loon Lim · Wed Jun 15 14:59:33 2022 +0200
  3. a3e5635 fix(intel): fix pinmux handoff bug on Agilex by Jit Loon Lim · Thu Jun 16 22:54:01 2022 +0200
  4. 55803a2 fix(intel): fix UART baud rate and clock by Sieu Mun Tang · Fri Jul 01 09:08:57 2022 +0800
  5. dc2daae build(agilex): platform changes for verifying gpt header crc by Rohit Ner · Wed May 11 03:15:40 2022 -0700
  6. b56c078 fix(intel): remove redundant NOC header declarations by Sieu Mun Tang · Fri May 13 11:14:08 2022 +0800
  7. 044ed48 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · Wed May 11 10:45:19 2022 +0800
  8. 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · Tue May 10 20:17:51 2022 +0200
  9. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · Wed Apr 06 10:19:16 2022 +0800
  10. 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · Thu May 05 17:07:21 2022 +0800
  11. 2f94ca4 feat(intel): enable firewall for OCRAM in BL31 by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 05 22:40:46 2020 +0800
  12. 1205ef0 feat(intel): create source file for firewall configuration by Abdul Halim, Muhammad Hadi Asyrafi · Thu Aug 06 10:21:54 2020 +0800
  13. 616b5e7 fix(intel): refactor NOC header by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 05 22:12:23 2020 +0800
  14. b19ac61 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · Fri Aug 06 01:16:46 2021 +0800
  15. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · Mon Feb 28 15:24:59 2022 +0800
  16. dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · Mon Mar 07 12:13:04 2022 +0800
  17. f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · Mon Jun 29 12:15:27 2020 +0800
  18. 9f22cbf build(intel): initial commit for crypto driver by Sieu Mun Tang · Wed Mar 02 11:04:09 2022 +0800
  19. c353b0a Merge "fix(intel): assert if bl_mem_params is NULL pointer" into integration by Madhukar Pappireddy · Mon Feb 28 20:36:30 2022 +0100
  20. 380924d fix(intel): assert if bl_mem_params is NULL pointer by Siew Chin Lim · Sat Jun 12 13:25:05 2021 +0800
  21. ae4cd3a fix(intel): enable HPS QSPI access by default by Abdul Halim, Muhammad Hadi Asyrafi · Tue Oct 06 20:09:53 2020 +0800
  22. cf93158 plat/intel: do not keep mmc_device_info in stack by Yann Gautier · Mon Mar 22 14:21:54 2021 +0100
  23. 6474096 intel: mailbox: Ensure time out duration is predictive by Chee Hong Ang · Mon May 11 00:55:01 2020 +0800
  24. 2382b11 intel: clear 'PLAT_SEC_ENTRY' in early platform setup by Chee Hong Ang · Fri Apr 24 21:51:00 2020 +0800
  25. 0ae8d9a intel: platform: Include GICv2 makefile by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 19 14:50:01 2020 +0800
  26. c5baddf plat: intel: Add FPGAINTF configuration to when configuring pinmux by Tien Hock Loh · Mon May 11 01:11:48 2020 -0700
  27. fcbc33d plat: intel: set DRVSEL and SMPLSEL for DWMMC by Tien Hock Loh · Mon May 11 01:11:39 2020 -0700
  28. 7a5f8da plat: intel: Fix clock configuration bugs by Tien Hock Loh · Mon May 11 01:11:23 2020 -0700
  29. 7dd4add Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration by Sandrine Bailleux · Fri Feb 28 10:51:49 2020 +0000
  30. 98b5a11 16550: Use generic console_t data structure by Andre Przywara · Sat Jan 25 00:58:35 2020 +0000
  31. 8d9e891 intel: Enable EMAC PHY in Intel FPGA platform by Tien Hock, Loh · Wed Oct 02 13:49:25 2019 +0800
  32. 7f95059 Merge "intel: Change boot source selection" into integration by Sandrine Bailleux · Wed Feb 12 15:54:02 2020 +0000
  33. 593c4c5 intel: Extend SiP service to support mailbox's RSU by Hadi Asyrafi · Tue Dec 17 19:22:17 2019 +0800
  34. 786db4d intel: Change boot source selection by Hadi Asyrafi · Mon Dec 30 16:00:30 2019 +0800
  35. 218d8fe intel: agilex: Enable uboot BL31 loading by Hadi Asyrafi · Tue Jan 14 10:51:31 2020 +0800
  36. 6aeb55d intel: Add function to check fpga readiness by Hadi Asyrafi · Tue Dec 24 14:43:22 2019 +0800
  37. 36a9f30 intel: Add bridge control for FPGA reconfig by Hadi Asyrafi · Tue Dec 24 10:42:52 2019 +0800
  38. 8ebd237 intel: System Manager refactoring by Hadi Asyrafi · Mon Dec 23 17:58:04 2019 +0800
  39. 67cb0ea intel: Refactor reset manager driver by Hadi Asyrafi · Mon Dec 23 13:25:33 2019 +0800
  40. e73c511 intel: Enable bridge access in Intel platform by Hadi Asyrafi · Mon Oct 21 16:35:08 2019 +0800
  41. 3afb87a intel: Modify non secure access function by Hadi Asyrafi · Mon Oct 21 16:27:29 2019 +0800
  42. 99361aa Merge "intel: Fix memory calibration" into integration by Manish Pandey · Tue Jan 14 18:28:43 2020 +0000
  43. 1fab9c3 Remove redundant declarations. by Madhukar Pappireddy · Thu Jan 02 16:32:41 2020 -0600
  44. 966f282 intel: Fix memory calibration by Hadi Asyrafi · Wed Oct 16 13:02:22 2019 +0800
  45. 5ae876f intel: Refactor common platform code [5/5] by Hadi Asyrafi · Wed Oct 23 17:58:06 2019 +0800
  46. 4d9f395 intel: Refactor common platform code [4/5] by Hadi Asyrafi · Wed Oct 23 17:35:32 2019 +0800
  47. 6f8a2b2 intel: Refactor common platform code [3/5] by Hadi Asyrafi · Wed Oct 23 18:34:14 2019 +0800
  48. f0fa807 intel: Refactor common platform code [2/5] by Hadi Asyrafi · Wed Oct 23 17:02:55 2019 +0800
  49. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · Wed Oct 23 16:26:53 2019 +0800
  50. 461f8f4 Invalidate dcache build option for bl2 entry at EL3 by Hadi Asyrafi · Tue Aug 20 15:33:27 2019 +0800
  51. 91071fc intel: agilex: Fix psci power domain off by Hadi Asyrafi · Thu Sep 12 15:14:01 2019 +0800
  52. cc077d9 Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration by Paul Beesley · Wed Aug 28 13:05:51 2019 +0000
  53. 5d7c656 intel: agilex: HMC driver calculate DDR size by Hadi Asyrafi · Fri Aug 16 17:07:42 2019 +0800
  54. 56c4901 intel: agilex: Clear PLL lostlock bypass mode by Hadi Asyrafi · Fri Aug 16 11:08:14 2019 +0800
  55. ad90712 Merge "intel: agilex: Fix memory controller driver" into integration by Paul Beesley · Thu Aug 15 15:30:51 2019 +0000
  56. 83fe38e intel: agilex: Fix memory controller driver by Hadi Asyrafi · Thu Aug 08 18:52:31 2019 +0800
  57. a813fed intel: agilex: Fix reliance on hard coded clock information by Hadi Asyrafi · Wed Aug 14 13:49:00 2019 +0800
  58. 462c6c4 Merge changes from topic "intel-plat-refactor" into integration by Sandrine Bailleux · Wed Aug 07 14:20:01 2019 +0000
  59. 309ac01 intel: Platform common code refactor by Hadi Asyrafi · Thu Aug 01 14:48:39 2019 +0800
  60. 6a240c7 intel: Platform common code refactor by Hadi Asyrafi · Thu Aug 01 15:21:20 2019 +0800
  61. e944d22 intel: agilex: Fix BL31 memory mapping by Hadi Asyrafi · Tue Jul 30 10:56:38 2019 +0800
  62. a724e43 intel: agilex: Fix build error by Ambroise Vincent · Tue Jul 23 11:10:27 2019 +0100
  63. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · Thu Jun 27 11:34:03 2019 +0800