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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +01002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch_helpers.h>
Soby Mathew0d9e8522015-07-15 13:36:24 +01008#include <arm_def.h>
Dan Handley9df48042015-03-19 18:58:55 +00009#include <assert.h>
10#include <errno.h>
Soby Mathew7799cf72015-04-16 14:49:09 +010011#include <plat_arm.h>
Soby Mathew9ca28062017-10-11 16:08:58 +010012#include <platform.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010013#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000014#include <psci.h>
15
Dimitris Papastamosd7a36512018-06-18 13:01:06 +010016/* Allow ARM Standard platforms to override these functions */
Dimitris Papastamosd7a36512018-06-18 13:01:06 +010017#pragma weak plat_arm_program_trusted_mailbox
Soby Mathew0b4c5a32016-10-21 17:51:22 +010018
Soby Mathew7799cf72015-04-16 14:49:09 +010019#if !ARM_RECOM_STATE_ID_ENC
Dan Handley9df48042015-03-19 18:58:55 +000020/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +010021 * ARM standard platform handler called to check the validity of the power state
22 * parameter.
Dan Handley9df48042015-03-19 18:58:55 +000023 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010024int arm_validate_power_state(unsigned int power_state,
25 psci_power_state_t *req_state)
Dan Handley9df48042015-03-19 18:58:55 +000026{
Antonio Nino Diazfec756f2018-07-18 16:24:16 +010027 unsigned int pstate = psci_get_pstate_type(power_state);
28 unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
29 unsigned int i;
Dan Handley9df48042015-03-19 18:58:55 +000030
Sathees Balya50905c72018-10-05 13:30:59 +010031 assert(req_state != NULL);
Dan Handley9df48042015-03-19 18:58:55 +000032
Soby Mathewfec4eb72015-07-01 16:16:20 +010033 if (pwr_lvl > PLAT_MAX_PWR_LVL)
34 return PSCI_E_INVALID_PARAMS;
Dan Handley9df48042015-03-19 18:58:55 +000035
Dan Handley9df48042015-03-19 18:58:55 +000036 /* Sanity check the requested state */
Soby Mathewfec4eb72015-07-01 16:16:20 +010037 if (pstate == PSTATE_TYPE_STANDBY) {
Dan Handley9df48042015-03-19 18:58:55 +000038 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +010039 * It's possible to enter standby only on power level 0
40 * Ignore any other power level.
Dan Handley9df48042015-03-19 18:58:55 +000041 */
Soby Mathewfec4eb72015-07-01 16:16:20 +010042 if (pwr_lvl != ARM_PWR_LVL0)
Dan Handley9df48042015-03-19 18:58:55 +000043 return PSCI_E_INVALID_PARAMS;
Soby Mathewfec4eb72015-07-01 16:16:20 +010044
45 req_state->pwr_domain_state[ARM_PWR_LVL0] =
46 ARM_LOCAL_STATE_RET;
47 } else {
48 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++)
49 req_state->pwr_domain_state[i] =
50 ARM_LOCAL_STATE_OFF;
Dan Handley9df48042015-03-19 18:58:55 +000051 }
52
53 /*
54 * We expect the 'state id' to be zero.
55 */
Antonio Nino Diazfec756f2018-07-18 16:24:16 +010056 if (psci_get_pstate_id(power_state) != 0U)
Dan Handley9df48042015-03-19 18:58:55 +000057 return PSCI_E_INVALID_PARAMS;
58
Soby Mathew7799cf72015-04-16 14:49:09 +010059 return PSCI_E_SUCCESS;
60}
61
62#else
63/*******************************************************************************
64 * ARM standard platform handler called to check the validity of the power
65 * state parameter. The power state parameter has to be a composite power
66 * state.
67 ******************************************************************************/
68int arm_validate_power_state(unsigned int power_state,
69 psci_power_state_t *req_state)
70{
71 unsigned int state_id;
72 int i;
73
Sathees Balya50905c72018-10-05 13:30:59 +010074 assert(req_state != NULL);
Soby Mathew7799cf72015-04-16 14:49:09 +010075
76 /*
77 * Currently we are using a linear search for finding the matching
78 * entry in the idle power state array. This can be made a binary
79 * search if the number of entries justify the additional complexity.
80 */
81 for (i = 0; !!arm_pm_idle_states[i]; i++) {
82 if (power_state == arm_pm_idle_states[i])
83 break;
84 }
85
86 /* Return error if entry not found in the idle state array */
87 if (!arm_pm_idle_states[i])
88 return PSCI_E_INVALID_PARAMS;
89
90 i = 0;
91 state_id = psci_get_pstate_id(power_state);
92
93 /* Parse the State ID and populate the state info parameter */
94 while (state_id) {
95 req_state->pwr_domain_state[i++] = state_id &
96 ARM_LOCAL_PSTATE_MASK;
97 state_id >>= ARM_LOCAL_PSTATE_WIDTH;
98 }
99
Dan Handley9df48042015-03-19 18:58:55 +0000100 return PSCI_E_SUCCESS;
101}
Soby Mathew7799cf72015-04-16 14:49:09 +0100102#endif /* __ARM_RECOM_STATE_ID_ENC__ */
Soby Mathew0d9e8522015-07-15 13:36:24 +0100103
104/*******************************************************************************
105 * ARM standard platform handler called to check the validity of the non secure
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100106 * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise.
Soby Mathew0d9e8522015-07-15 13:36:24 +0100107 ******************************************************************************/
108int arm_validate_ns_entrypoint(uintptr_t entrypoint)
109{
110 /*
111 * Check if the non secure entrypoint lies within the non
112 * secure DRAM.
113 */
114 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint <
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100115 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
116 return 0;
117 }
dp-arm84fc2952017-05-03 12:14:10 +0100118#ifndef AARCH32
Soby Mathew0d9e8522015-07-15 13:36:24 +0100119 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint <
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100120 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) {
121 return 0;
122 }
dp-arm84fc2952017-05-03 12:14:10 +0100123#endif
Soby Mathew0d9e8522015-07-15 13:36:24 +0100124
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100125 return -1;
126}
127
128int arm_validate_psci_entrypoint(uintptr_t entrypoint)
129{
Sathees Balya50905c72018-10-05 13:30:59 +0100130 return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS :
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100131 PSCI_E_INVALID_ADDRESS;
Soby Mathew0d9e8522015-07-15 13:36:24 +0100132}
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100133
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100134/******************************************************************************
Soby Mathew9ca28062017-10-11 16:08:58 +0100135 * Helper function to save the platform state before a system suspend. Save the
136 * state of the system components which are not in the Always ON power domain.
137 *****************************************************************************/
138void arm_system_pwr_domain_save(void)
139{
140 /* Assert system power domain is available on the platform */
141 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
142
143 plat_arm_gic_save();
144
145 /*
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100146 * Unregister console now so that it is not registered for a second
147 * time during resume.
148 */
149 arm_console_runtime_end();
150
151 /*
Soby Mathew9ca28062017-10-11 16:08:58 +0100152 * All the other peripheral which are configured by ARM TF are
153 * re-initialized on resume from system suspend. Hence we
154 * don't save their state here.
155 */
156}
157
158/******************************************************************************
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100159 * Helper function to resume the platform from system suspend. Reinitialize
160 * the system components which are not in the Always ON power domain.
161 * TODO: Unify the platform setup when waking up from cold boot and system
162 * resume in arm_bl31_platform_setup().
163 *****************************************************************************/
164void arm_system_pwr_domain_resume(void)
165{
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100166 /* Initialize the console */
167 arm_console_runtime_init();
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100168
169 /* Assert system power domain is available on the platform */
170 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
171
Soby Mathew9ca28062017-10-11 16:08:58 +0100172 plat_arm_gic_resume();
173
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100174 plat_arm_security_setup();
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100175 arm_configure_sys_timer();
176}
177
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100178/*******************************************************************************
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100179 * ARM platform function to program the mailbox for a cpu before it is released
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100180 * from reset. This function assumes that the Trusted mail box base is within
181 * the ARM_SHARED_RAM region
182 ******************************************************************************/
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100183void plat_arm_program_trusted_mailbox(uintptr_t address)
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100184{
185 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE;
186
187 *mailbox = address;
188
189 /*
190 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within
191 * ARM_SHARED_RAM region.
192 */
193 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) &&
194 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \
195 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)));
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100196}
197
198/*******************************************************************************
199 * The ARM Standard platform definition of platform porting API
200 * `plat_setup_psci_ops`.
201 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100202int __init plat_setup_psci_ops(uintptr_t sec_entrypoint,
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100203 const plat_psci_ops_t **psci_ops)
204{
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100205 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops);
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100206
207 /* Setup mailbox with entry point. */
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100208 plat_arm_program_trusted_mailbox(sec_entrypoint);
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100209 return 0;
210}