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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
Prasad Kummari7d0623a2023-06-09 14:32:00 +05303 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05304 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
Tejas Patel54d13192019-02-27 18:44:55 +05308#include <assert.h>
Prasad Kummari536e1102023-06-22 10:50:02 +05309
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/debug.h>
11#include <lib/mmio.h>
12#include <lib/psci/psci.h>
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -080013#include <plat/arm/common/plat_arm.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053014#include <plat/common/platform.h>
15#include <plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016
Jay Buddhabhatti10e71e42023-06-19 05:08:54 -070017#include "drivers/delay_timer.h"
Prasad Kummari536e1102023-06-22 10:50:02 +053018#include <plat_private.h>
Tejas Patel61717112019-02-27 18:44:57 +053019#include "pm_api_sys.h"
20#include "pm_client.h"
Prasad Kummari536e1102023-06-22 10:50:02 +053021#include <pm_common.h>
Jay Buddhabhatti10e71e42023-06-19 05:08:54 -070022#include "pm_ipi.h"
23#include "pm_svc_main.h"
Tejas Patel61717112019-02-27 18:44:57 +053024
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053025static uintptr_t versal_sec_entry;
26
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053027static int32_t versal_pwr_domain_on(u_register_t mpidr)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053028{
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053029 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
Tejas Patel61717112019-02-27 18:44:57 +053030 const struct pm_proc *proc;
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053031
32 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
33
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -070034 if (cpu_id == -1) {
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053035 return PSCI_E_INTERN_FAIL;
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -070036 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053037
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053038 proc = pm_get_proc((uint32_t)cpu_id);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053039
Tejas Patel61717112019-02-27 18:44:57 +053040 /* Send request to PMC to wake up selected ACPU core */
Abhyuday Godhasaraf435a142021-08-20 00:04:33 -070041 (void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
42 versal_sec_entry >> 32, 0, SECURE_FLAG);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053043
Tejas Patel61717112019-02-27 18:44:57 +053044 /* Clear power down request */
45 pm_client_wakeup(proc);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053046
47 return PSCI_E_SUCCESS;
48}
49
Tejas Patel54d13192019-02-27 18:44:55 +053050/**
51 * versal_pwr_domain_suspend() - This function sends request to PMC to suspend
Prasad Kummari7d0623a2023-06-09 14:32:00 +053052 * core.
53 * @target_state: Targated state.
Tejas Patel54d13192019-02-27 18:44:55 +053054 *
Tejas Patel54d13192019-02-27 18:44:55 +053055 */
56static void versal_pwr_domain_suspend(const psci_power_state_t *target_state)
57{
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053058 uint32_t state;
59 uint32_t cpu_id = plat_my_core_pos();
Tejas Patel54d13192019-02-27 18:44:55 +053060 const struct pm_proc *proc = pm_get_proc(cpu_id);
61
Abhyuday Godhasara589afa52021-08-11 06:15:13 -070062 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
Tejas Patel54d13192019-02-27 18:44:55 +053063 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
64 __func__, i, target_state->pwr_domain_state[i]);
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -070065 }
Tejas Patel54d13192019-02-27 18:44:55 +053066
67 plat_versal_gic_cpuif_disable();
68
Ravi Pateleafc8782019-06-21 05:00:49 -070069 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
70 plat_versal_gic_save();
71 }
Tejas Patel54d13192019-02-27 18:44:55 +053072
73 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
74 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
75
76 /* Send request to PMC to suspend this core */
Abhyuday Godhasaraf435a142021-08-20 00:04:33 -070077 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry,
78 SECURE_FLAG);
Tejas Patel54d13192019-02-27 18:44:55 +053079
80 /* APU is to be turned off */
81 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
82 /* disable coherency */
83 plat_arm_interconnect_exit_coherency();
84 }
85}
86
87/**
88 * versal_pwr_domain_suspend_finish() - This function performs actions to finish
Prasad Kummari7d0623a2023-06-09 14:32:00 +053089 * suspend procedure.
90 * @target_state: Targated state.
Tejas Patel54d13192019-02-27 18:44:55 +053091 *
Tejas Patel54d13192019-02-27 18:44:55 +053092 */
93static void versal_pwr_domain_suspend_finish(
94 const psci_power_state_t *target_state)
95{
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053096 uint32_t cpu_id = plat_my_core_pos();
Tejas Patel54d13192019-02-27 18:44:55 +053097 const struct pm_proc *proc = pm_get_proc(cpu_id);
98
Abhyuday Godhasara589afa52021-08-11 06:15:13 -070099 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
Tejas Patel54d13192019-02-27 18:44:55 +0530100 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
101 __func__, i, target_state->pwr_domain_state[i]);
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700102 }
Tejas Patel54d13192019-02-27 18:44:55 +0530103
104 /* Clear the APU power control register for this cpu */
105 pm_client_wakeup(proc);
106
107 /* enable coherency */
108 plat_arm_interconnect_enter_coherency();
109
110 /* APU was turned off, so restore GIC context */
111 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
112 plat_versal_gic_resume();
Tejas Patel54d13192019-02-27 18:44:55 +0530113 }
Ravi Pateleafc8782019-06-21 05:00:49 -0700114
115 plat_versal_gic_cpuif_enable();
Tejas Patel54d13192019-02-27 18:44:55 +0530116}
117
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530118void versal_pwr_domain_on_finish(const psci_power_state_t *target_state)
119{
120 /* Enable the gic cpu interface */
121 plat_versal_gic_pcpu_init();
122
123 /* Program the gic per-cpu distributor or re-distributor interface */
124 plat_versal_gic_cpuif_enable();
125}
126
Tejas Patel54d13192019-02-27 18:44:55 +0530127/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530128 * versal_system_off() - This function sends the system off request to firmware.
129 * This function does not return.
130 *
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800131 */
132static void __dead2 versal_system_off(void)
133{
134 /* Send the power down request to the PMC */
Abhyuday Godhasaraf435a142021-08-20 00:04:33 -0700135 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
136 pm_get_shutdown_scope(), SECURE_FLAG);
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800137
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700138 while (1) {
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800139 wfi();
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700140 }
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800141}
142
143/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530144 * versal_system_reset() - This function sends the reset request to firmware
145 * for the system to reset. This function does not
146 * return.
147 *
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800148 */
149static void __dead2 versal_system_reset(void)
150{
Jay Buddhabhatti10e71e42023-06-19 05:08:54 -0700151 uint32_t ret, timeout = 10000U;
152
153 request_cpu_pwrdwn();
154
155 /*
156 * Send the system reset request to the firmware if power down request
157 * is not received from firmware.
158 */
159 if (!pwrdwn_req_received) {
160 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
161 pm_get_shutdown_scope(), SECURE_FLAG);
162
163 /*
164 * Wait for system shutdown request completed and idle callback
165 * not received.
166 */
167 do {
168 ret = ipi_mb_enquire_status(primary_proc->ipi->local_ipi_id,
169 primary_proc->ipi->remote_ipi_id);
170 udelay(100);
171 timeout--;
172 } while ((ret != IPI_MB_STATUS_RECV_PENDING) && (timeout > 0U));
173 }
174
175 (void)psci_cpu_off();
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800176
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700177 while (1) {
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800178 wfi();
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700179 }
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800180}
181
182/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530183 * versal_pwr_domain_off() - This function performs actions to turn off core.
184 * @target_state: Targated state.
Tejas Patel54d13192019-02-27 18:44:55 +0530185 *
Tejas Patel54d13192019-02-27 18:44:55 +0530186 */
187static void versal_pwr_domain_off(const psci_power_state_t *target_state)
188{
Jay Buddhabhatti31488a32023-09-11 23:50:06 -0700189 uint32_t ret, fw_api_version, version[PAYLOAD_ARG_CNT] = {0U};
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +0530190 uint32_t cpu_id = plat_my_core_pos();
Tejas Patel54d13192019-02-27 18:44:55 +0530191 const struct pm_proc *proc = pm_get_proc(cpu_id);
192
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700193 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
Tejas Patel54d13192019-02-27 18:44:55 +0530194 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
195 __func__, i, target_state->pwr_domain_state[i]);
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700196 }
Tejas Patel54d13192019-02-27 18:44:55 +0530197
198 /* Prevent interrupts from spuriously waking up this cpu */
199 plat_versal_gic_cpuif_disable();
200
201 /*
202 * Send request to PMC to power down the appropriate APU CPU
203 * core.
204 * According to PSCI specification, CPU_off function does not
205 * have resume address and CPU core can only be woken up
206 * invoking CPU_on function, during which resume address will
207 * be set.
208 */
Jay Buddhabhatti31488a32023-09-11 23:50:06 -0700209 ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version[0], SECURE_FLAG);
210 if (ret == PM_RET_SUCCESS) {
211 fw_api_version = version[0] & 0xFFFFU;
212 if (fw_api_version >= 3U) {
213 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0,
214 SECURE_FLAG);
215 } else {
216 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0,
217 SECURE_FLAG);
218 }
219 }
Tejas Patel54d13192019-02-27 18:44:55 +0530220}
221
222/**
223 * versal_validate_power_state() - This function ensures that the power state
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530224 * parameter in request is valid.
225 * @power_state: Power state of core.
226 * @req_state: Requested state.
Tejas Patel54d13192019-02-27 18:44:55 +0530227 *
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530228 * Return: Returns status, either success or reason.
Tejas Patel54d13192019-02-27 18:44:55 +0530229 *
Tejas Patel54d13192019-02-27 18:44:55 +0530230 */
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +0530231static int32_t versal_validate_power_state(uint32_t power_state,
Tejas Patel54d13192019-02-27 18:44:55 +0530232 psci_power_state_t *req_state)
233{
234 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
235
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +0530236 uint32_t pstate = psci_get_pstate_type(power_state);
Tejas Patel54d13192019-02-27 18:44:55 +0530237
238 assert(req_state);
239
240 /* Sanity check the requested state */
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700241 if (pstate == PSTATE_TYPE_STANDBY) {
Tejas Patel54d13192019-02-27 18:44:55 +0530242 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700243 } else {
Tejas Patel54d13192019-02-27 18:44:55 +0530244 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700245 }
Tejas Patel54d13192019-02-27 18:44:55 +0530246
247 /* We expect the 'state id' to be zero */
Abhyuday Godhasarabacbdee2021-08-20 00:27:03 -0700248 if (psci_get_pstate_id(power_state) != 0U) {
Tejas Patel54d13192019-02-27 18:44:55 +0530249 return PSCI_E_INVALID_PARAMS;
Abhyuday Godhasaraf55a5cd2021-08-09 08:15:13 -0700250 }
Tejas Patel54d13192019-02-27 18:44:55 +0530251
252 return PSCI_E_SUCCESS;
253}
254
255/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530256 * versal_get_sys_suspend_power_state() - Get power state for system suspend.
257 * @req_state: Requested state.
Tejas Patel54d13192019-02-27 18:44:55 +0530258 *
Tejas Patel54d13192019-02-27 18:44:55 +0530259 */
260static void versal_get_sys_suspend_power_state(psci_power_state_t *req_state)
261{
262 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
263 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
264}
265
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530266static const struct plat_psci_ops versal_nopmc_psci_ops = {
Tejas Patel61717112019-02-27 18:44:57 +0530267 .pwr_domain_on = versal_pwr_domain_on,
Tejas Patel54d13192019-02-27 18:44:55 +0530268 .pwr_domain_off = versal_pwr_domain_off,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530269 .pwr_domain_on_finish = versal_pwr_domain_on_finish,
Tejas Patel54d13192019-02-27 18:44:55 +0530270 .pwr_domain_suspend = versal_pwr_domain_suspend,
271 .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish,
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -0800272 .system_off = versal_system_off,
273 .system_reset = versal_system_reset,
Tejas Patel54d13192019-02-27 18:44:55 +0530274 .validate_power_state = versal_validate_power_state,
275 .get_sys_suspend_power_state = versal_get_sys_suspend_power_state,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530276};
277
278/*******************************************************************************
279 * Export the platform specific power ops.
280 ******************************************************************************/
Venkatesh Yadav Abbarapu2cefbcd2022-07-31 14:05:40 +0530281int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530282 const struct plat_psci_ops **psci_ops)
283{
284 versal_sec_entry = sec_entrypoint;
285
286 *psci_ops = &versal_nopmc_psci_ops;
287
288 return 0;
289}