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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Tejas Patel69409962018-12-14 00:55:29 -08002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Tejas Patel54d13192019-02-27 18:44:55 +05307#include <assert.h>
8#include <plat_arm.h>
Tejas Patel69409962018-12-14 00:55:29 -08009#include <plat_private.h>
Tejas Patel61717112019-02-27 18:44:57 +053010#include <pm_common.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/debug.h>
12#include <lib/mmio.h>
13#include <lib/psci/psci.h>
14#include <plat/common/platform.h>
15
Tejas Patel61717112019-02-27 18:44:57 +053016#include "pm_api_sys.h"
17#include "pm_client.h"
18
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053019static uintptr_t versal_sec_entry;
20
Tejas Patel61717112019-02-27 18:44:57 +053021static int versal_pwr_domain_on(u_register_t mpidr)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053022{
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053023 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
Tejas Patel61717112019-02-27 18:44:57 +053024 const struct pm_proc *proc;
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053025
26 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
27
28 if (cpu_id == -1)
29 return PSCI_E_INTERN_FAIL;
30
Tejas Patel61717112019-02-27 18:44:57 +053031 proc = pm_get_proc(cpu_id);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053032
Tejas Patel61717112019-02-27 18:44:57 +053033 /* Send request to PMC to wake up selected ACPU core */
34 pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFF) | 0x1,
35 versal_sec_entry >> 32, 0);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053036
Tejas Patel61717112019-02-27 18:44:57 +053037 /* Clear power down request */
38 pm_client_wakeup(proc);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053039
40 return PSCI_E_SUCCESS;
41}
42
Tejas Patel54d13192019-02-27 18:44:55 +053043/**
44 * versal_pwr_domain_suspend() - This function sends request to PMC to suspend
45 * core.
46 *
47 * @target_state Targated state
48 */
49static void versal_pwr_domain_suspend(const psci_power_state_t *target_state)
50{
51 unsigned int state;
52 unsigned int cpu_id = plat_my_core_pos();
53 const struct pm_proc *proc = pm_get_proc(cpu_id);
54
55 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
56 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
57 __func__, i, target_state->pwr_domain_state[i]);
58
59 plat_versal_gic_cpuif_disable();
60
61 plat_versal_gic_save();
62
63 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
64 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
65
66 /* Send request to PMC to suspend this core */
67 pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry);
68
69 /* APU is to be turned off */
70 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
71 /* disable coherency */
72 plat_arm_interconnect_exit_coherency();
73 }
74}
75
76/**
77 * versal_pwr_domain_suspend_finish() - This function performs actions to finish
78 * suspend procedure.
79 *
80 * @target_state Targated state
81 */
82static void versal_pwr_domain_suspend_finish(
83 const psci_power_state_t *target_state)
84{
85 unsigned int cpu_id = plat_my_core_pos();
86 const struct pm_proc *proc = pm_get_proc(cpu_id);
87
88 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
89 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
90 __func__, i, target_state->pwr_domain_state[i]);
91
92 /* Clear the APU power control register for this cpu */
93 pm_client_wakeup(proc);
94
95 /* enable coherency */
96 plat_arm_interconnect_enter_coherency();
97
98 /* APU was turned off, so restore GIC context */
99 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
100 plat_versal_gic_resume();
101 plat_versal_gic_cpuif_enable();
102 } else {
103 plat_versal_gic_cpuif_enable();
104 plat_versal_gic_pcpu_init();
105 }
106}
107
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530108void versal_pwr_domain_on_finish(const psci_power_state_t *target_state)
109{
110 /* Enable the gic cpu interface */
111 plat_versal_gic_pcpu_init();
112
113 /* Program the gic per-cpu distributor or re-distributor interface */
114 plat_versal_gic_cpuif_enable();
115}
116
Tejas Patel54d13192019-02-27 18:44:55 +0530117/**
118 * versal_pwr_domain_off() - This function performs actions to turn off core
119 *
120 * @target_state Targated state
121 */
122static void versal_pwr_domain_off(const psci_power_state_t *target_state)
123{
124 unsigned int cpu_id = plat_my_core_pos();
125 const struct pm_proc *proc = pm_get_proc(cpu_id);
126
127 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
128 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
129 __func__, i, target_state->pwr_domain_state[i]);
130
131 /* Prevent interrupts from spuriously waking up this cpu */
132 plat_versal_gic_cpuif_disable();
133
134 /*
135 * Send request to PMC to power down the appropriate APU CPU
136 * core.
137 * According to PSCI specification, CPU_off function does not
138 * have resume address and CPU core can only be woken up
139 * invoking CPU_on function, during which resume address will
140 * be set.
141 */
142 pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
143}
144
145/**
146 * versal_validate_power_state() - This function ensures that the power state
147 * parameter in request is valid.
148 *
149 * @power_state Power state of core
150 * @req_state Requested state
151 *
152 * @return Returns status, either success or reason
153 */
154static int versal_validate_power_state(unsigned int power_state,
155 psci_power_state_t *req_state)
156{
157 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
158
159 int pstate = psci_get_pstate_type(power_state);
160
161 assert(req_state);
162
163 /* Sanity check the requested state */
164 if (pstate == PSTATE_TYPE_STANDBY)
165 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
166 else
167 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
168
169 /* We expect the 'state id' to be zero */
170 if (psci_get_pstate_id(power_state))
171 return PSCI_E_INVALID_PARAMS;
172
173 return PSCI_E_SUCCESS;
174}
175
176/**
177 * versal_get_sys_suspend_power_state() - Get power state for system suspend
178 *
179 * @req_state Requested state
180 */
181static void versal_get_sys_suspend_power_state(psci_power_state_t *req_state)
182{
183 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
184 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
185}
186
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530187static const struct plat_psci_ops versal_nopmc_psci_ops = {
Tejas Patel61717112019-02-27 18:44:57 +0530188 .pwr_domain_on = versal_pwr_domain_on,
Tejas Patel54d13192019-02-27 18:44:55 +0530189 .pwr_domain_off = versal_pwr_domain_off,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530190 .pwr_domain_on_finish = versal_pwr_domain_on_finish,
Tejas Patel54d13192019-02-27 18:44:55 +0530191 .pwr_domain_suspend = versal_pwr_domain_suspend,
192 .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish,
193 .validate_power_state = versal_validate_power_state,
194 .get_sys_suspend_power_state = versal_get_sys_suspend_power_state,
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530195};
196
197/*******************************************************************************
198 * Export the platform specific power ops.
199 ******************************************************************************/
200int plat_setup_psci_ops(uintptr_t sec_entrypoint,
201 const struct plat_psci_ops **psci_ops)
202{
203 versal_sec_entry = sec_entrypoint;
204
205 *psci_ops = &versal_nopmc_psci_ops;
206
207 return 0;
208}