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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handleyfb42b122014-06-20 09:43:15 +010033#include <arm_gic.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010034#include <assert.h>
35#include <bl_common.h>
Vikram Kanigiri96377452014-04-24 11:02:16 +010036#include <cci400.h>
Dan Handley714a0d22014-04-09 13:13:04 +010037#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010038#include <mmio.h>
Jon Medhurstb1eb0932014-02-26 16:27:53 +000039#include <platform.h>
Dan Handley1c54d972014-06-20 12:02:01 +010040#include <plat_config.h>
Jon Medhurstb1eb0932014-02-26 16:27:53 +000041#include <xlat_tables.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010042#include "../fvp_def.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010043
Achin Gupta4f6ad662013-10-25 09:08:21 +010044/*******************************************************************************
Dan Handley1c54d972014-06-20 12:02:01 +010045 * plat_config holds the characteristics of the differences between the three
Achin Gupta4f6ad662013-10-25 09:08:21 +010046 * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
47 * boot at each boot stage by the primary before enabling the MMU (to allow cci
48 * configuration) & used thereafter. Each BL will have its own copy to allow
49 * independent operation.
50 ******************************************************************************/
Dan Handley1c54d972014-06-20 12:02:01 +010051plat_config_t plat_config;
Achin Gupta4f6ad662013-10-25 09:08:21 +010052
Jon Medhurstb1eb0932014-02-26 16:27:53 +000053/*
54 * Table of regions to map using the MMU.
Sandrine Bailleux74a62b32014-05-09 11:35:36 +010055 * This doesn't include TZRAM as the 'mem_layout' argument passed to
56 * configure_mmu_elx() will give the available subset of that,
Jon Medhurstb1eb0932014-02-26 16:27:53 +000057 */
Dan Handleye2712bc2014-04-10 15:37:22 +010058const mmap_region_t fvp_mmap[] = {
Lin Ma13592362014-06-02 11:45:36 -070059 { TZROM_BASE, TZROM_BASE, TZROM_SIZE,
60 MT_MEMORY | MT_RO | MT_SECURE },
61 { TZDRAM_BASE, TZDRAM_BASE, TZDRAM_SIZE,
62 MT_MEMORY | MT_RW | MT_SECURE },
63 { FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE,
64 MT_MEMORY | MT_RO | MT_SECURE },
65 { FLASH1_BASE, FLASH1_BASE, FLASH1_SIZE,
66 MT_MEMORY | MT_RO | MT_SECURE },
67 { VRAM_BASE, VRAM_BASE, VRAM_SIZE,
68 MT_MEMORY | MT_RW | MT_SECURE },
69 { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE,
70 MT_DEVICE | MT_RW | MT_SECURE },
Lin Ma13592362014-06-02 11:45:36 -070071 { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE,
72 MT_DEVICE | MT_RW | MT_SECURE },
Jon Medhurstb1eb0932014-02-26 16:27:53 +000073 /* 2nd GB as device for now...*/
Lin Ma13592362014-06-02 11:45:36 -070074 { 0x40000000, 0x40000000, 0x40000000,
75 MT_DEVICE | MT_RW | MT_SECURE },
76 { DRAM1_BASE, DRAM1_BASE, DRAM1_SIZE,
77 MT_MEMORY | MT_RW | MT_NS },
Jon Medhurstb1eb0932014-02-26 16:27:53 +000078 {0}
79};
80
Dan Handleyfb42b122014-06-20 09:43:15 +010081/* Array of secure interrupts to be configured by the gic driver */
82const unsigned int irq_sec_array[] = {
83 IRQ_TZ_WDOG,
84 IRQ_SEC_PHY_TIMER,
85 IRQ_SEC_SGI_0,
86 IRQ_SEC_SGI_1,
87 IRQ_SEC_SGI_2,
88 IRQ_SEC_SGI_3,
89 IRQ_SEC_SGI_4,
90 IRQ_SEC_SGI_5,
91 IRQ_SEC_SGI_6,
92 IRQ_SEC_SGI_7
93};
94
95const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
96 sizeof(irq_sec_array[0]);
97
Achin Gupta4f6ad662013-10-25 09:08:21 +010098/*******************************************************************************
Sandrine Bailleux74a62b32014-05-09 11:35:36 +010099 * Macro generating the code for the function setting up the pagetables as per
100 * the platform memory map & initialize the mmu, for the given exception level
101 ******************************************************************************/
102#define DEFINE_CONFIGURE_MMU_EL(_el) \
Lin Ma13592362014-06-02 11:45:36 -0700103 void fvp_configure_mmu_el##_el(unsigned long total_base, \
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100104 unsigned long total_size, \
Sandrine Bailleux74a62b32014-05-09 11:35:36 +0100105 unsigned long ro_start, \
106 unsigned long ro_limit, \
107 unsigned long coh_start, \
108 unsigned long coh_limit) \
109 { \
Lin Ma13592362014-06-02 11:45:36 -0700110 mmap_add_region(total_base, total_base, \
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100111 total_size, \
Sandrine Bailleux74a62b32014-05-09 11:35:36 +0100112 MT_MEMORY | MT_RW | MT_SECURE); \
Lin Ma13592362014-06-02 11:45:36 -0700113 mmap_add_region(ro_start, ro_start, \
114 ro_limit - ro_start, \
Sandrine Bailleux74a62b32014-05-09 11:35:36 +0100115 MT_MEMORY | MT_RO | MT_SECURE); \
Lin Ma13592362014-06-02 11:45:36 -0700116 mmap_add_region(coh_start, coh_start, \
117 coh_limit - coh_start, \
Sandrine Bailleux74a62b32014-05-09 11:35:36 +0100118 MT_DEVICE | MT_RW | MT_SECURE); \
119 mmap_add(fvp_mmap); \
120 init_xlat_tables(); \
121 \
122 enable_mmu_el##_el(); \
123 }
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000124
Sandrine Bailleux74a62b32014-05-09 11:35:36 +0100125/* Define EL1 and EL3 variants of the function initialising the MMU */
126DEFINE_CONFIGURE_MMU_EL(1)
127DEFINE_CONFIGURE_MMU_EL(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129/*******************************************************************************
130 * A single boot loader stack is expected to work on both the Foundation FVP
131 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
132 * SYS_ID register provides a mechanism for detecting the differences between
133 * these platforms. This information is stored in a per-BL array to allow the
134 * code to take the correct path.Per BL platform configuration.
135 ******************************************************************************/
Dan Handleyea451572014-05-15 14:53:30 +0100136int fvp_config_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137{
138 unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
139
140 sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
141 rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
142 hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK;
143 bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK;
144 arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK;
145
Andrew Thoelke960347d2014-06-26 14:27:26 +0100146 if (arch != ARCH_MODEL) {
147 ERROR("This firmware is for FVP models\n");
James Morrissey40a6f642014-02-10 14:24:36 +0000148 panic();
Andrew Thoelke960347d2014-06-26 14:27:26 +0100149 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150
151 /*
152 * The build field in the SYS_ID tells which variant of the GIC
153 * memory is implemented by the model.
154 */
155 switch (bld) {
156 case BLD_GIC_VE_MMAP:
Dan Handley1c54d972014-06-20 12:02:01 +0100157 plat_config.gicd_base = VE_GICD_BASE;
158 plat_config.gicc_base = VE_GICC_BASE;
159 plat_config.gich_base = VE_GICH_BASE;
160 plat_config.gicv_base = VE_GICV_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161 break;
162 case BLD_GIC_A53A57_MMAP:
Dan Handley1c54d972014-06-20 12:02:01 +0100163 plat_config.gicd_base = BASE_GICD_BASE;
164 plat_config.gicc_base = BASE_GICC_BASE;
165 plat_config.gich_base = BASE_GICH_BASE;
166 plat_config.gicv_base = BASE_GICV_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167 break;
168 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100169 ERROR("Unsupported board build %x\n", bld);
170 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100171 }
172
173 /*
174 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
175 * for the Foundation FVP.
176 */
177 switch (hbi) {
178 case HBI_FOUNDATION:
Dan Handley1c54d972014-06-20 12:02:01 +0100179 plat_config.max_aff0 = 4;
180 plat_config.max_aff1 = 1;
181 plat_config.flags = 0;
Andrew Thoelke960347d2014-06-26 14:27:26 +0100182
183 /*
184 * Check for supported revisions of Foundation FVP
185 * Allow future revisions to run but emit warning diagnostic
186 */
187 switch (rev) {
188 case REV_FOUNDATION_V2_0:
189 case REV_FOUNDATION_V2_1:
190 break;
191 default:
192 WARN("Unrecognized Foundation FVP revision %x\n", rev);
193 break;
194 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100195 break;
196 case HBI_FVP_BASE:
197 midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
Dan Handley1c54d972014-06-20 12:02:01 +0100198 plat_config.flags =
199 ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
200 ? CONFIG_CPUECTLR_SMP_BIT : 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100201
Dan Handley1c54d972014-06-20 12:02:01 +0100202 plat_config.max_aff0 = 4;
203 plat_config.max_aff1 = 2;
204 plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI |
205 CONFIG_HAS_TZC;
Andrew Thoelke960347d2014-06-26 14:27:26 +0100206
207 /*
208 * Check for supported revisions
209 * Allow future revisions to run but emit warning diagnostic
210 */
211 switch (rev) {
212 case REV_FVP_BASE_V0:
213 break;
214 default:
215 WARN("Unrecognized Base FVP revision %x\n", rev);
216 break;
217 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100218 break;
219 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100220 ERROR("Unsupported board HBI number 0x%x\n", hbi);
221 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222 }
223
224 return 0;
225}
226
Ian Spray84687392014-01-02 16:57:12 +0000227unsigned long plat_get_ns_image_entrypoint(void)
228{
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229 return NS_IMAGE_OFFSET;
230}
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100231
232uint64_t plat_get_syscnt_freq(void)
233{
234 uint64_t counter_base_frequency;
235
236 /* Read the frequency from Frequency modes table */
237 counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
238
239 /* The first entry of the frequency modes table must not be 0 */
240 assert(counter_base_frequency != 0);
241
242 return counter_base_frequency;
243}
Vikram Kanigiri96377452014-04-24 11:02:16 +0100244
245void fvp_cci_setup(void)
246{
Vikram Kanigiri96377452014-04-24 11:02:16 +0100247 /*
248 * Enable CCI-400 for this cluster. No need
249 * for locks as no other cpu is active at the
250 * moment
251 */
Dan Handley1c54d972014-06-20 12:02:01 +0100252 if (plat_config.flags & CONFIG_HAS_CCI)
Vikram Kanigiri96377452014-04-24 11:02:16 +0100253 cci_enable_coherency(read_mpidr());
254}
255
Dan Handleyfb42b122014-06-20 09:43:15 +0100256void fvp_gic_init(void)
257{
258 arm_gic_init(plat_config.gicc_base,
259 plat_config.gicd_base,
260 BASE_GICR_BASE,
261 irq_sec_array,
262 num_sec_irqs);
263}
264
Vikram Kanigiri96377452014-04-24 11:02:16 +0100265
266/*******************************************************************************
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100267 * Gets SPSR for BL32 entry
Vikram Kanigiri96377452014-04-24 11:02:16 +0100268 ******************************************************************************/
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100269uint32_t fvp_get_spsr_for_bl32_entry(void)
Vikram Kanigiri96377452014-04-24 11:02:16 +0100270{
Vikram Kanigiri96377452014-04-24 11:02:16 +0100271 /*
272 * The Secure Payload Dispatcher service is responsible for
273 * setting the SPSR prior to entry into the BL32 image.
274 */
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100275 return 0;
Vikram Kanigiri96377452014-04-24 11:02:16 +0100276}
277
278/*******************************************************************************
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100279 * Gets SPSR for BL33 entry
Vikram Kanigiri96377452014-04-24 11:02:16 +0100280 ******************************************************************************/
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100281uint32_t fvp_get_spsr_for_bl33_entry(void)
Vikram Kanigiri96377452014-04-24 11:02:16 +0100282{
283 unsigned long el_status;
284 unsigned int mode;
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100285 uint32_t spsr;
Vikram Kanigiri96377452014-04-24 11:02:16 +0100286
287 /* Figure out what mode we enter the non-secure world in */
288 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
289 el_status &= ID_AA64PFR0_ELX_MASK;
290
291 if (el_status)
292 mode = MODE_EL2;
293 else
294 mode = MODE_EL1;
295
296 /*
297 * TODO: Consider the possibility of specifying the SPSR in
298 * the FIP ToC and allowing the platform to have a say as
299 * well.
300 */
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100301 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
302 return spsr;
Vikram Kanigiri96377452014-04-24 11:02:16 +0100303}