Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 35 | #include <cci400.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 36 | #include <debug.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 37 | #include <mmio.h> |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 38 | #include <platform.h> |
| 39 | #include <xlat_tables.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 40 | #include "../fvp_def.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 41 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 42 | /******************************************************************************* |
| 43 | * This array holds the characteristics of the differences between the three |
| 44 | * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold |
| 45 | * boot at each boot stage by the primary before enabling the MMU (to allow cci |
| 46 | * configuration) & used thereafter. Each BL will have its own copy to allow |
| 47 | * independent operation. |
| 48 | ******************************************************************************/ |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 49 | static unsigned long fvp_config[CONFIG_LIMIT]; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 50 | |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 51 | /* |
| 52 | * Table of regions to map using the MMU. |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 53 | * This doesn't include TZRAM as the 'mem_layout' argument passed to |
| 54 | * configure_mmu_elx() will give the available subset of that, |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 55 | */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 56 | const mmap_region_t fvp_mmap[] = { |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame^] | 57 | { TZROM_BASE, TZROM_BASE, TZROM_SIZE, |
| 58 | MT_MEMORY | MT_RO | MT_SECURE }, |
| 59 | { TZDRAM_BASE, TZDRAM_BASE, TZDRAM_SIZE, |
| 60 | MT_MEMORY | MT_RW | MT_SECURE }, |
| 61 | { FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE, |
| 62 | MT_MEMORY | MT_RO | MT_SECURE }, |
| 63 | { FLASH1_BASE, FLASH1_BASE, FLASH1_SIZE, |
| 64 | MT_MEMORY | MT_RO | MT_SECURE }, |
| 65 | { VRAM_BASE, VRAM_BASE, VRAM_SIZE, |
| 66 | MT_MEMORY | MT_RW | MT_SECURE }, |
| 67 | { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, |
| 68 | MT_DEVICE | MT_RW | MT_SECURE }, |
| 69 | { NSRAM_BASE, NSRAM_BASE, NSRAM_SIZE, |
| 70 | MT_MEMORY | MT_RW | MT_NS }, |
| 71 | { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, |
| 72 | MT_DEVICE | MT_RW | MT_SECURE }, |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 73 | /* 2nd GB as device for now...*/ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame^] | 74 | { 0x40000000, 0x40000000, 0x40000000, |
| 75 | MT_DEVICE | MT_RW | MT_SECURE }, |
| 76 | { DRAM1_BASE, DRAM1_BASE, DRAM1_SIZE, |
| 77 | MT_MEMORY | MT_RW | MT_NS }, |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 78 | {0} |
| 79 | }; |
| 80 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 81 | /******************************************************************************* |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 82 | * Macro generating the code for the function setting up the pagetables as per |
| 83 | * the platform memory map & initialize the mmu, for the given exception level |
| 84 | ******************************************************************************/ |
| 85 | #define DEFINE_CONFIGURE_MMU_EL(_el) \ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame^] | 86 | void fvp_configure_mmu_el##_el(unsigned long total_base, \ |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame] | 87 | unsigned long total_size, \ |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 88 | unsigned long ro_start, \ |
| 89 | unsigned long ro_limit, \ |
| 90 | unsigned long coh_start, \ |
| 91 | unsigned long coh_limit) \ |
| 92 | { \ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame^] | 93 | mmap_add_region(total_base, total_base, \ |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame] | 94 | total_size, \ |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 95 | MT_MEMORY | MT_RW | MT_SECURE); \ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame^] | 96 | mmap_add_region(ro_start, ro_start, \ |
| 97 | ro_limit - ro_start, \ |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 98 | MT_MEMORY | MT_RO | MT_SECURE); \ |
Lin Ma | 1359236 | 2014-06-02 11:45:36 -0700 | [diff] [blame^] | 99 | mmap_add_region(coh_start, coh_start, \ |
| 100 | coh_limit - coh_start, \ |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 101 | MT_DEVICE | MT_RW | MT_SECURE); \ |
| 102 | mmap_add(fvp_mmap); \ |
| 103 | init_xlat_tables(); \ |
| 104 | \ |
| 105 | enable_mmu_el##_el(); \ |
| 106 | } |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 107 | |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 108 | /* Define EL1 and EL3 variants of the function initialising the MMU */ |
| 109 | DEFINE_CONFIGURE_MMU_EL(1) |
| 110 | DEFINE_CONFIGURE_MMU_EL(3) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 111 | |
| 112 | /* Simple routine which returns a configuration variable value */ |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 113 | unsigned long fvp_get_cfgvar(unsigned int var_id) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 114 | { |
| 115 | assert(var_id < CONFIG_LIMIT); |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 116 | return fvp_config[var_id]; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | /******************************************************************************* |
| 120 | * A single boot loader stack is expected to work on both the Foundation FVP |
| 121 | * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The |
| 122 | * SYS_ID register provides a mechanism for detecting the differences between |
| 123 | * these platforms. This information is stored in a per-BL array to allow the |
| 124 | * code to take the correct path.Per BL platform configuration. |
| 125 | ******************************************************************************/ |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 126 | int fvp_config_setup(void) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 127 | { |
| 128 | unsigned int rev, hbi, bld, arch, sys_id, midr_pn; |
| 129 | |
| 130 | sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID); |
| 131 | rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK; |
| 132 | hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK; |
| 133 | bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK; |
| 134 | arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK; |
| 135 | |
James Morrissey | 40a6f64 | 2014-02-10 14:24:36 +0000 | [diff] [blame] | 136 | if ((rev != REV_FVP) || (arch != ARCH_MODEL)) |
| 137 | panic(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * The build field in the SYS_ID tells which variant of the GIC |
| 141 | * memory is implemented by the model. |
| 142 | */ |
| 143 | switch (bld) { |
| 144 | case BLD_GIC_VE_MMAP: |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 145 | fvp_config[CONFIG_GICD_ADDR] = VE_GICD_BASE; |
| 146 | fvp_config[CONFIG_GICC_ADDR] = VE_GICC_BASE; |
| 147 | fvp_config[CONFIG_GICH_ADDR] = VE_GICH_BASE; |
| 148 | fvp_config[CONFIG_GICV_ADDR] = VE_GICV_BASE; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 149 | break; |
| 150 | case BLD_GIC_A53A57_MMAP: |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 151 | fvp_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE; |
| 152 | fvp_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE; |
| 153 | fvp_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE; |
| 154 | fvp_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 155 | break; |
| 156 | default: |
| 157 | assert(0); |
| 158 | } |
| 159 | |
| 160 | /* |
| 161 | * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 |
| 162 | * for the Foundation FVP. |
| 163 | */ |
| 164 | switch (hbi) { |
| 165 | case HBI_FOUNDATION: |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 166 | fvp_config[CONFIG_MAX_AFF0] = 4; |
| 167 | fvp_config[CONFIG_MAX_AFF1] = 1; |
| 168 | fvp_config[CONFIG_CPU_SETUP] = 0; |
| 169 | fvp_config[CONFIG_BASE_MMAP] = 0; |
| 170 | fvp_config[CONFIG_HAS_CCI] = 0; |
| 171 | fvp_config[CONFIG_HAS_TZC] = 0; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 172 | break; |
| 173 | case HBI_FVP_BASE: |
| 174 | midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK; |
| 175 | if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53)) |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 176 | fvp_config[CONFIG_CPU_SETUP] = 1; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 177 | else |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 178 | fvp_config[CONFIG_CPU_SETUP] = 0; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 179 | |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 180 | fvp_config[CONFIG_MAX_AFF0] = 4; |
| 181 | fvp_config[CONFIG_MAX_AFF1] = 2; |
| 182 | fvp_config[CONFIG_BASE_MMAP] = 1; |
| 183 | fvp_config[CONFIG_HAS_CCI] = 1; |
| 184 | fvp_config[CONFIG_HAS_TZC] = 1; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 185 | break; |
| 186 | default: |
| 187 | assert(0); |
| 188 | } |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 193 | unsigned long plat_get_ns_image_entrypoint(void) |
| 194 | { |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 195 | return NS_IMAGE_OFFSET; |
| 196 | } |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 197 | |
| 198 | uint64_t plat_get_syscnt_freq(void) |
| 199 | { |
| 200 | uint64_t counter_base_frequency; |
| 201 | |
| 202 | /* Read the frequency from Frequency modes table */ |
| 203 | counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); |
| 204 | |
| 205 | /* The first entry of the frequency modes table must not be 0 */ |
| 206 | assert(counter_base_frequency != 0); |
| 207 | |
| 208 | return counter_base_frequency; |
| 209 | } |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 210 | |
| 211 | void fvp_cci_setup(void) |
| 212 | { |
| 213 | unsigned long cci_setup; |
| 214 | |
| 215 | /* |
| 216 | * Enable CCI-400 for this cluster. No need |
| 217 | * for locks as no other cpu is active at the |
| 218 | * moment |
| 219 | */ |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 220 | cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI); |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 221 | if (cci_setup) |
| 222 | cci_enable_coherency(read_mpidr()); |
| 223 | } |
| 224 | |
| 225 | |
| 226 | /******************************************************************************* |
| 227 | * Set SPSR and secure state for BL32 image |
| 228 | ******************************************************************************/ |
| 229 | void fvp_set_bl32_ep_info(entry_point_info_t *bl32_ep_info) |
| 230 | { |
| 231 | SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); |
| 232 | /* |
| 233 | * The Secure Payload Dispatcher service is responsible for |
| 234 | * setting the SPSR prior to entry into the BL32 image. |
| 235 | */ |
| 236 | bl32_ep_info->spsr = 0; |
| 237 | } |
| 238 | |
| 239 | /******************************************************************************* |
| 240 | * Set SPSR and secure state for BL33 image |
| 241 | ******************************************************************************/ |
| 242 | void fvp_set_bl33_ep_info(entry_point_info_t *bl33_ep_info) |
| 243 | { |
| 244 | unsigned long el_status; |
| 245 | unsigned int mode; |
| 246 | |
| 247 | /* Figure out what mode we enter the non-secure world in */ |
| 248 | el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; |
| 249 | el_status &= ID_AA64PFR0_ELX_MASK; |
| 250 | |
| 251 | if (el_status) |
| 252 | mode = MODE_EL2; |
| 253 | else |
| 254 | mode = MODE_EL1; |
| 255 | |
| 256 | /* |
| 257 | * TODO: Consider the possibility of specifying the SPSR in |
| 258 | * the FIP ToC and allowing the platform to have a say as |
| 259 | * well. |
| 260 | */ |
| 261 | bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 262 | SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); |
| 263 | } |