Enable mapping higher physical address
Current ATF uses a direct physical-to-virtual mapping, that is, a physical
address is mapped to the same address in the virtual space. For example,
physical address 0x8000_0000 is mapped to 0x8000_0000 virtual. This
approach works fine for FVP as all its physical addresses fall into 0 to
4GB range. But for other platform where all I/O addresses are 48-bit long,
If we follow the same direct mapping, we would need virtual address range
from 0 to 0x8fff_ffff_ffff, which is about 144TB. This requires a
significant amount of memory for MMU tables and it is not necessary to use
that much virtual space in ATF.
The patch is to enable mapping a physical address range to an arbitrary
virtual address range (instead of flat mapping)
Changed "base" to "base_va" and added "base_pa" in mmap_region_t and
modified functions such as mmap_add_region and init_xlation_table etc.
Fixes ARM-software/tf-issues#158
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index 3a07844..41234cb 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -54,17 +54,27 @@
* configure_mmu_elx() will give the available subset of that,
*/
const mmap_region_t fvp_mmap[] = {
- { TZROM_BASE, TZROM_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
- { TZDRAM_BASE, TZDRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
- { FLASH0_BASE, FLASH0_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
- { FLASH1_BASE, FLASH1_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
- { VRAM_BASE, VRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
- { DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
- { NSRAM_BASE, NSRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
- { DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
+ { TZROM_BASE, TZROM_BASE, TZROM_SIZE,
+ MT_MEMORY | MT_RO | MT_SECURE },
+ { TZDRAM_BASE, TZDRAM_BASE, TZDRAM_SIZE,
+ MT_MEMORY | MT_RW | MT_SECURE },
+ { FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE,
+ MT_MEMORY | MT_RO | MT_SECURE },
+ { FLASH1_BASE, FLASH1_BASE, FLASH1_SIZE,
+ MT_MEMORY | MT_RO | MT_SECURE },
+ { VRAM_BASE, VRAM_BASE, VRAM_SIZE,
+ MT_MEMORY | MT_RW | MT_SECURE },
+ { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE },
+ { NSRAM_BASE, NSRAM_BASE, NSRAM_SIZE,
+ MT_MEMORY | MT_RW | MT_NS },
+ { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE },
/* 2nd GB as device for now...*/
- { 0x40000000, 0x40000000, MT_DEVICE | MT_RW | MT_SECURE },
- { DRAM1_BASE, DRAM1_SIZE, MT_MEMORY | MT_RW | MT_NS },
+ { 0x40000000, 0x40000000, 0x40000000,
+ MT_DEVICE | MT_RW | MT_SECURE },
+ { DRAM1_BASE, DRAM1_BASE, DRAM1_SIZE,
+ MT_MEMORY | MT_RW | MT_NS },
{0}
};
@@ -73,19 +83,21 @@
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void fvp_configure_mmu_el##_el(unsigned long total_base, \
+ void fvp_configure_mmu_el##_el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit, \
unsigned long coh_start, \
unsigned long coh_limit) \
{ \
- mmap_add_region(total_base, \
+ mmap_add_region(total_base, total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
- mmap_add_region(ro_start, ro_limit - ro_start, \
+ mmap_add_region(ro_start, ro_start, \
+ ro_limit - ro_start, \
MT_MEMORY | MT_RO | MT_SECURE); \
- mmap_add_region(coh_start, coh_limit - coh_start, \
+ mmap_add_region(coh_start, coh_start, \
+ coh_limit - coh_start, \
MT_DEVICE | MT_RW | MT_SECURE); \
mmap_add(fvp_mmap); \
init_xlat_tables(); \