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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handleyed6ff952014-05-14 17:44:19 +01007#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <lib/xlat_tables/xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
11OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
12OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000013ENTRY(bl31_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010014
15
16MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010017 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010018}
19
Caesar Wangd90f43e2016-10-11 09:36:00 +080020#ifdef PLAT_EXTRA_LD_SCRIPT
21#include <plat.ld.S>
22#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010023
24SECTIONS
25{
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000026 . = BL31_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000027 ASSERT(. == ALIGN(PAGE_SIZE),
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000028 "BL31_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010029
Soby Mathew4e28c202018-10-14 08:09:22 +010030 __BL31_START__ = .;
31
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010032#if SEPARATE_CODE_AND_RODATA
33 .text . : {
34 __TEXT_START__ = .;
35 *bl31_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050036 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010037 *(.vectors)
Roberto Vargasd93fde32018-04-11 11:53:31 +010038 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010039 __TEXT_END__ = .;
40 } >RAM
41
42 .rodata . : {
43 __RODATA_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -050044 *(SORT_BY_ALIGNMENT(.rodata*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010045
46 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
47 . = ALIGN(8);
48 __RT_SVC_DESCS_START__ = .;
49 KEEP(*(rt_svc_descs))
50 __RT_SVC_DESCS_END__ = .;
51
52#if ENABLE_PMF
53 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
54 . = ALIGN(8);
55 __PMF_SVC_DESCS_START__ = .;
56 KEEP(*(pmf_svc_descs))
57 __PMF_SVC_DESCS_END__ = .;
58#endif /* ENABLE_PMF */
59
60 /*
61 * Ensure 8-byte alignment for cpu_ops so that its fields are also
62 * aligned. Also ensure cpu_ops inclusion.
63 */
64 . = ALIGN(8);
65 __CPU_OPS_START__ = .;
66 KEEP(*(cpu_ops))
67 __CPU_OPS_END__ = .;
68
Soby Mathew4e28c202018-10-14 08:09:22 +010069 /*
Soby Mathew2b3fc1d2018-12-12 14:33:11 +000070 * Keep the .got section in the RO section as it is patched
Soby Mathew4e28c202018-10-14 08:09:22 +010071 * prior to enabling the MMU and having the .got in RO is better for
Soby Mathew2b3fc1d2018-12-12 14:33:11 +000072 * security. GOT is a table of addresses so ensure 8-byte alignment.
Soby Mathew4e28c202018-10-14 08:09:22 +010073 */
Soby Mathew2b3fc1d2018-12-12 14:33:11 +000074 . = ALIGN(8);
Soby Mathew4e28c202018-10-14 08:09:22 +010075 __GOT_START__ = .;
76 *(.got)
77 __GOT_END__ = .;
78
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010079 /* Place pubsub sections for events */
80 . = ALIGN(8);
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000081#include <lib/el3_runtime/pubsub_events.h>
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010082
Roberto Vargasd93fde32018-04-11 11:53:31 +010083 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010084 __RODATA_END__ = .;
85 } >RAM
86#else
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000087 ro . : {
88 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000089 *bl31_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050090 *(SORT_BY_ALIGNMENT(.text*))
91 *(SORT_BY_ALIGNMENT(.rodata*))
Achin Gupta7421b462014-02-01 18:53:26 +000092
Andrew Thoelkee01ea342014-03-18 07:13:52 +000093 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
Achin Gupta7421b462014-02-01 18:53:26 +000094 . = ALIGN(8);
95 __RT_SVC_DESCS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000096 KEEP(*(rt_svc_descs))
Achin Gupta7421b462014-02-01 18:53:26 +000097 __RT_SVC_DESCS_END__ = .;
98
Yatharth Kochar9518d022016-03-11 14:20:19 +000099#if ENABLE_PMF
100 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
101 . = ALIGN(8);
102 __PMF_SVC_DESCS_START__ = .;
103 KEEP(*(pmf_svc_descs))
104 __PMF_SVC_DESCS_END__ = .;
105#endif /* ENABLE_PMF */
106
Soby Mathewc704cbc2014-08-14 11:33:56 +0100107 /*
108 * Ensure 8-byte alignment for cpu_ops so that its fields are also
109 * aligned. Also ensure cpu_ops inclusion.
110 */
111 . = ALIGN(8);
112 __CPU_OPS_START__ = .;
113 KEEP(*(cpu_ops))
114 __CPU_OPS_END__ = .;
115
Soby Mathew2b3fc1d2018-12-12 14:33:11 +0000116 /*
117 * Keep the .got section in the RO section as it is patched
118 * prior to enabling the MMU and having the .got in RO is better for
119 * security. GOT is a table of addresses so ensure 8-byte alignment.
120 */
121 . = ALIGN(8);
122 __GOT_START__ = .;
123 *(.got)
124 __GOT_END__ = .;
125
Jeenu Viswambharane3f22002017-09-22 08:32:10 +0100126 /* Place pubsub sections for events */
127 . = ALIGN(8);
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000128#include <lib/el3_runtime/pubsub_events.h>
Jeenu Viswambharane3f22002017-09-22 08:32:10 +0100129
Achin Guptab739f222014-01-18 16:50:09 +0000130 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000131 __RO_END_UNALIGNED__ = .;
132 /*
133 * Memory page(s) mapped to this section will be marked as read-only,
134 * executable. No RW data from the next section must creep in.
135 * Ensure the rest of the current memory page is unused.
136 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100137 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000138 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +0100140#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141
Soby Mathewc704cbc2014-08-14 11:33:56 +0100142 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
143 "cpu_ops not defined for this platform.")
144
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100145#if ENABLE_SPM
Ard Biesheuvel447d56f2019-01-06 10:07:24 +0100146#ifndef SPM_SHIM_EXCEPTIONS_VMA
147#define SPM_SHIM_EXCEPTIONS_VMA RAM
148#endif
149
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100150 /*
151 * Exception vectors of the SPM shim layer. They must be aligned to a 2K
152 * address, but we need to place them in a separate page so that we can set
153 * individual permissions to them, so the actual alignment needed is 4K.
154 *
155 * There's no need to include this into the RO section of BL31 because it
156 * doesn't need to be accessed by BL31.
157 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000158 spm_shim_exceptions : ALIGN(PAGE_SIZE) {
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100159 __SPM_SHIM_EXCEPTIONS_START__ = .;
160 *(.spm_shim_exceptions)
Roberto Vargasd93fde32018-04-11 11:53:31 +0100161 . = ALIGN(PAGE_SIZE);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100162 __SPM_SHIM_EXCEPTIONS_END__ = .;
Ard Biesheuvel447d56f2019-01-06 10:07:24 +0100163 } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM
164
165 PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions));
166 . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100167#endif
168
Achin Guptae9c4a642015-09-11 16:03:13 +0100169 /*
170 * Define a linker symbol to mark start of the RW memory area for this
171 * image.
172 */
173 __RW_START__ = . ;
174
Douglas Raillard306593d2017-02-24 18:14:15 +0000175 /*
176 * .data must be placed at a lower address than the stacks if the stack
177 * protector is enabled. Alternatively, the .data.stack_protector_canary
178 * section can be placed independently of the main .data section.
179 */
180 .data . : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000181 __DATA_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -0500182 *(SORT_BY_ALIGNMENT(.data*))
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000183 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100184 } >RAM
185
Soby Mathew4e28c202018-10-14 08:09:22 +0100186 /*
187 * .rela.dyn needs to come after .data for the read-elf utility to parse
Soby Mathew2b3fc1d2018-12-12 14:33:11 +0000188 * this section correctly. Ensure 8-byte alignment so that the fields of
189 * RELA data structure are aligned.
Soby Mathew4e28c202018-10-14 08:09:22 +0100190 */
Soby Mathew2b3fc1d2018-12-12 14:33:11 +0000191 . = ALIGN(8);
Soby Mathew4e28c202018-10-14 08:09:22 +0100192 __RELA_START__ = .;
193 .rela.dyn . : {
194 } >RAM
195 __RELA_END__ = .;
196
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +0100197#ifdef BL31_PROGBITS_LIMIT
Juan Castillo7d199412015-12-14 09:35:25 +0000198 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +0100199#endif
200
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000201 stacks (NOLOAD) : {
202 __STACKS_START__ = .;
203 *(tzfw_normal_stacks)
204 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100205 } >RAM
206
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000207 /*
208 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +0000209 * Its base address should be 16-byte aligned for better performance of the
210 * zero-initialization code.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000211 */
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100212 .bss (NOLOAD) : ALIGN(16) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000213 __BSS_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -0500214 *(SORT_BY_ALIGNMENT(.bss*))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215 *(COMMON)
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100216#if !USE_COHERENT_MEM
217 /*
218 * Bakery locks are stored in normal .bss memory
219 *
220 * Each lock's data is spread across multiple cache lines, one per CPU,
221 * but multiple locks can share the same cache line.
222 * The compiler will allocate enough memory for one CPU's bakery locks,
223 * the remaining cache lines are allocated by the linker script
224 */
225 . = ALIGN(CACHE_WRITEBACK_GRANULE);
226 __BAKERY_LOCK_START__ = .;
Varun Wadekar77c382c2019-01-30 08:26:20 -0800227 __PERCPU_BAKERY_LOCK_START__ = .;
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100228 *(bakery_lock)
229 . = ALIGN(CACHE_WRITEBACK_GRANULE);
Varun Wadekar77c382c2019-01-30 08:26:20 -0800230 __PERCPU_BAKERY_LOCK_END__ = .;
231 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__);
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100232 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
233 __BAKERY_LOCK_END__ = .;
Roberto Vargas00996942017-11-13 13:41:58 +0000234
235 /*
236 * If BL31 doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__
237 * will be zero. For this reason, the only two valid values for
238 * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value
239 * PLAT_PERCPU_BAKERY_LOCK_SIZE.
240 */
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100241#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
Roberto Vargas00996942017-11-13 13:41:58 +0000242 ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) || (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE),
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100243 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
244#endif
245#endif
Yatharth Kochar9518d022016-03-11 14:20:19 +0000246
247#if ENABLE_PMF
248 /*
249 * Time-stamps are stored in normal .bss memory
250 *
251 * The compiler will allocate enough memory for one CPU's time-stamps,
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000252 * the remaining memory for other CPUs is allocated by the
Yatharth Kochar9518d022016-03-11 14:20:19 +0000253 * linker script
254 */
255 . = ALIGN(CACHE_WRITEBACK_GRANULE);
256 __PMF_TIMESTAMP_START__ = .;
257 KEEP(*(pmf_timestamp_array))
258 . = ALIGN(CACHE_WRITEBACK_GRANULE);
259 __PMF_PERCPU_TIMESTAMP_END__ = .;
260 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__);
261 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1));
262 __PMF_TIMESTAMP_END__ = .;
263#endif /* ENABLE_PMF */
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000264 __BSS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100265 } >RAM
266
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000267 /*
Jeenu Viswambharan97cc9ee2014-02-24 15:20:28 +0000268 * The xlat_table section is for full, aligned page tables (4K).
Achin Guptaa0cd9892014-02-09 13:30:38 +0000269 * Removing them from .bss avoids forcing 4K alignment on
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +0000270 * the .bss section. The tables are initialized to zero by the translation
271 * tables library.
Achin Guptaa0cd9892014-02-09 13:30:38 +0000272 */
273 xlat_table (NOLOAD) : {
274 *(xlat_table)
275 } >RAM
276
Soby Mathew2ae20432015-01-08 18:02:44 +0000277#if USE_COHERENT_MEM
Achin Guptaa0cd9892014-02-09 13:30:38 +0000278 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000279 * The base address of the coherent memory section must be page-aligned (4K)
280 * to guarantee that the coherent data are stored on their own pages and
281 * are not mixed with normal data. This is required to set up the correct
282 * memory attributes for the coherent data page tables.
283 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000284 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000285 __COHERENT_RAM_START__ = .;
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100286 /*
287 * Bakery locks are stored in coherent memory
288 *
289 * Each lock's data is contiguous and fully allocated by the compiler
290 */
291 *(bakery_lock)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000292 *(tzfw_coherent_mem)
293 __COHERENT_RAM_END_UNALIGNED__ = .;
294 /*
295 * Memory page(s) mapped to this section will be marked
296 * as device memory. No other unexpected data must creep in.
297 * Ensure the rest of the current memory page is unused.
298 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100299 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000300 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100301 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000302#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100303
Achin Guptae9c4a642015-09-11 16:03:13 +0100304 /*
305 * Define a linker symbol to mark end of the RW memory area for this
306 * image.
307 */
308 __RW_END__ = .;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000309 __BL31_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100310
Juan Castillo7d199412015-12-14 09:35:25 +0000311 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100312}