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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handleyed6ff952014-05-14 17:44:19 +010031#include <platform_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000035ENTRY(bl31_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
37
38MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010039 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010040}
41
42
43SECTIONS
44{
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000045 . = BL31_BASE;
46 ASSERT(. == ALIGN(4096),
47 "BL31_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010048
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000049 ro . : {
50 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000051 *bl31_entrypoint.o(.text*)
52 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000053 *(.rodata*)
Achin Gupta7421b462014-02-01 18:53:26 +000054
Andrew Thoelkee01ea342014-03-18 07:13:52 +000055 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
Achin Gupta7421b462014-02-01 18:53:26 +000056 . = ALIGN(8);
57 __RT_SVC_DESCS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000058 KEEP(*(rt_svc_descs))
Achin Gupta7421b462014-02-01 18:53:26 +000059 __RT_SVC_DESCS_END__ = .;
60
Soby Mathewc704cbc2014-08-14 11:33:56 +010061 /*
62 * Ensure 8-byte alignment for cpu_ops so that its fields are also
63 * aligned. Also ensure cpu_ops inclusion.
64 */
65 . = ALIGN(8);
66 __CPU_OPS_START__ = .;
67 KEEP(*(cpu_ops))
68 __CPU_OPS_END__ = .;
69
Achin Guptab739f222014-01-18 16:50:09 +000070 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000071 __RO_END_UNALIGNED__ = .;
72 /*
73 * Memory page(s) mapped to this section will be marked as read-only,
74 * executable. No RW data from the next section must creep in.
75 * Ensure the rest of the current memory page is unused.
76 */
77 . = NEXT(4096);
78 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010079 } >RAM
80
Soby Mathewc704cbc2014-08-14 11:33:56 +010081 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
82 "cpu_ops not defined for this platform.")
83
Achin Guptae9c4a642015-09-11 16:03:13 +010084 /*
85 * Define a linker symbol to mark start of the RW memory area for this
86 * image.
87 */
88 __RW_START__ = . ;
89
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000090 .data . : {
91 __DATA_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000092 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000093 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010094 } >RAM
95
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +010096#ifdef BL31_PROGBITS_LIMIT
Juan Castillo7d199412015-12-14 09:35:25 +000097 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +010098#endif
99
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000100 stacks (NOLOAD) : {
101 __STACKS_START__ = .;
102 *(tzfw_normal_stacks)
103 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100104 } >RAM
105
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000106 /*
107 * The .bss section gets initialised to 0 at runtime.
108 * Its base address must be 16-byte aligned.
109 */
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100110 .bss (NOLOAD) : ALIGN(16) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000111 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000112 *(.bss*)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100113 *(COMMON)
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100114#if !USE_COHERENT_MEM
115 /*
116 * Bakery locks are stored in normal .bss memory
117 *
118 * Each lock's data is spread across multiple cache lines, one per CPU,
119 * but multiple locks can share the same cache line.
120 * The compiler will allocate enough memory for one CPU's bakery locks,
121 * the remaining cache lines are allocated by the linker script
122 */
123 . = ALIGN(CACHE_WRITEBACK_GRANULE);
124 __BAKERY_LOCK_START__ = .;
125 *(bakery_lock)
126 . = ALIGN(CACHE_WRITEBACK_GRANULE);
Vikram Kanigiri405fafe2015-09-24 15:45:43 +0100127 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100128 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
129 __BAKERY_LOCK_END__ = .;
130#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
131 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
132 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
133#endif
134#endif
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000135 __BSS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136 } >RAM
137
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000138 /*
Jeenu Viswambharan97cc9ee2014-02-24 15:20:28 +0000139 * The xlat_table section is for full, aligned page tables (4K).
Achin Guptaa0cd9892014-02-09 13:30:38 +0000140 * Removing them from .bss avoids forcing 4K alignment on
141 * the .bss section and eliminates the unecessary zero init
142 */
143 xlat_table (NOLOAD) : {
144 *(xlat_table)
145 } >RAM
146
Soby Mathew2ae20432015-01-08 18:02:44 +0000147#if USE_COHERENT_MEM
Achin Guptaa0cd9892014-02-09 13:30:38 +0000148 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000149 * The base address of the coherent memory section must be page-aligned (4K)
150 * to guarantee that the coherent data are stored on their own pages and
151 * are not mixed with normal data. This is required to set up the correct
152 * memory attributes for the coherent data page tables.
153 */
154 coherent_ram (NOLOAD) : ALIGN(4096) {
155 __COHERENT_RAM_START__ = .;
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100156 /*
157 * Bakery locks are stored in coherent memory
158 *
159 * Each lock's data is contiguous and fully allocated by the compiler
160 */
161 *(bakery_lock)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000162 *(tzfw_coherent_mem)
163 __COHERENT_RAM_END_UNALIGNED__ = .;
164 /*
165 * Memory page(s) mapped to this section will be marked
166 * as device memory. No other unexpected data must creep in.
167 * Ensure the rest of the current memory page is unused.
168 */
169 . = NEXT(4096);
170 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100171 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000172#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100173
Achin Guptae9c4a642015-09-11 16:03:13 +0100174 /*
175 * Define a linker symbol to mark end of the RW memory area for this
176 * image.
177 */
178 __RW_END__ = .;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000179 __BL31_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100180
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000181 __BSS_SIZE__ = SIZEOF(.bss);
Soby Mathew2ae20432015-01-08 18:02:44 +0000182#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000183 __COHERENT_RAM_UNALIGNED_SIZE__ =
184 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000185#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100186
Juan Castillo7d199412015-12-14 09:35:25 +0000187 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188}