Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 1 | /* |
Yann Gautier | d782056 | 2019-04-25 13:29:12 +0200 | [diff] [blame] | 2 | * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 7 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <common/debug.h> |
| 12 | #include <drivers/arm/tzc400.h> |
Yann Gautier | a205a5c | 2021-08-30 15:06:54 +0200 | [diff] [blame] | 13 | #include <drivers/clk.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <drivers/st/stm32mp1_clk.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <dt-bindings/clock/stm32mp1-clks.h> |
Yann Gautier | 68e6d69 | 2021-07-05 14:07:29 +0200 | [diff] [blame] | 16 | #include <dt-bindings/soc/stm32mp15-tzc400.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <lib/mmio.h> |
| 18 | |
Yann Gautier | de00f3e | 2020-08-20 16:36:07 +0200 | [diff] [blame] | 19 | static unsigned int region_nb; |
| 20 | |
Yann Gautier | f3bd87e | 2020-09-04 15:55:53 +0200 | [diff] [blame] | 21 | static void init_tzc400_begin(unsigned int region0_attr) |
Yann Gautier | de00f3e | 2020-08-20 16:36:07 +0200 | [diff] [blame] | 22 | { |
| 23 | tzc400_init(STM32MP1_TZC_BASE); |
| 24 | tzc400_disable_filters(); |
| 25 | |
Yann Gautier | f3bd87e | 2020-09-04 15:55:53 +0200 | [diff] [blame] | 26 | /* Region 0 set to cover all DRAM at 0xC000_0000 */ |
| 27 | tzc400_configure_region0(region0_attr, 0); |
| 28 | |
Yann Gautier | de00f3e | 2020-08-20 16:36:07 +0200 | [diff] [blame] | 29 | region_nb = 1U; |
| 30 | } |
| 31 | |
| 32 | static void init_tzc400_end(unsigned int action) |
| 33 | { |
| 34 | tzc400_set_action(action); |
| 35 | tzc400_enable_filters(); |
| 36 | } |
| 37 | |
| 38 | static void tzc400_add_region(unsigned long long region_base, |
| 39 | unsigned long long region_top, bool sec) |
| 40 | { |
| 41 | unsigned int sec_attr; |
| 42 | unsigned int nsaid_permissions; |
| 43 | |
| 44 | if (sec) { |
| 45 | sec_attr = TZC_REGION_S_RDWR; |
| 46 | nsaid_permissions = 0; |
| 47 | } else { |
| 48 | sec_attr = TZC_REGION_S_NONE; |
| 49 | nsaid_permissions = TZC_REGION_NSEC_ALL_ACCESS_RDWR; |
| 50 | } |
| 51 | |
| 52 | tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, region_nb, region_base, |
| 53 | region_top, sec_attr, nsaid_permissions); |
| 54 | |
| 55 | region_nb++; |
| 56 | } |
| 57 | |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 58 | /******************************************************************************* |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 59 | * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access |
| 60 | * and allow Non-Secure masters full access. |
| 61 | ******************************************************************************/ |
| 62 | static void init_tzc400(void) |
| 63 | { |
| 64 | unsigned long long region_base, region_top; |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 65 | unsigned long long ddr_base = STM32MP_DDR_BASE; |
Yann Gautier | cd40f32 | 2020-02-26 13:36:07 +0100 | [diff] [blame] | 66 | unsigned long long ddr_ns_size = |
| 67 | (unsigned long long)stm32mp_get_ddr_ns_size(); |
| 68 | unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U); |
Yann Gautier | de00f3e | 2020-08-20 16:36:07 +0200 | [diff] [blame] | 69 | unsigned long long ddr_top __unused; |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 70 | |
Yann Gautier | f3bd87e | 2020-09-04 15:55:53 +0200 | [diff] [blame] | 71 | init_tzc400_begin(TZC_REGION_S_NONE); |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 72 | |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 73 | /* |
| 74 | * Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the |
| 75 | * same configuration to all filters in the TZC. |
| 76 | */ |
| 77 | region_base = ddr_base; |
Yann Gautier | cd40f32 | 2020-02-26 13:36:07 +0100 | [diff] [blame] | 78 | region_top = ddr_ns_top; |
Yann Gautier | de00f3e | 2020-08-20 16:36:07 +0200 | [diff] [blame] | 79 | tzc400_add_region(region_base, region_top, false); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 80 | |
Yann Gautier | cd40f32 | 2020-02-26 13:36:07 +0100 | [diff] [blame] | 81 | #ifdef AARCH32_SP_OPTEE |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 82 | /* Region 2 set to cover all secure DRAM. */ |
| 83 | region_base = region_top + 1U; |
Yann Gautier | cd40f32 | 2020-02-26 13:36:07 +0100 | [diff] [blame] | 84 | region_top += STM32MP_DDR_S_SIZE; |
Yann Gautier | de00f3e | 2020-08-20 16:36:07 +0200 | [diff] [blame] | 85 | tzc400_add_region(region_base, region_top, true); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 86 | |
Yann Gautier | de00f3e | 2020-08-20 16:36:07 +0200 | [diff] [blame] | 87 | ddr_top = STM32MP_DDR_BASE + dt_get_ddr_size() - 1U; |
| 88 | if (region_top < ddr_top) { |
| 89 | /* Region 3 set to cover non-secure memory DRAM after BL32. */ |
| 90 | region_base = region_top + 1U; |
| 91 | region_top = ddr_top; |
| 92 | tzc400_add_region(region_base, region_top, false); |
| 93 | } |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 94 | #endif |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 95 | |
Yann Gautier | de00f3e | 2020-08-20 16:36:07 +0200 | [diff] [blame] | 96 | /* |
| 97 | * Raise an interrupt (secure FIQ) if a NS device tries to access |
| 98 | * secure memory |
| 99 | */ |
| 100 | init_tzc400_end(TZC_ACTION_INT); |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | /******************************************************************************* |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 104 | * Initialize the TrustZone Controller. |
| 105 | * Early initialization create only one region with full access to secure. |
| 106 | * This setting is used before and during DDR initialization. |
| 107 | ******************************************************************************/ |
| 108 | static void early_init_tzc400(void) |
| 109 | { |
Yann Gautier | a205a5c | 2021-08-30 15:06:54 +0200 | [diff] [blame] | 110 | clk_enable(TZC1); |
| 111 | clk_enable(TZC2); |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 112 | |
Yann Gautier | f3bd87e | 2020-09-04 15:55:53 +0200 | [diff] [blame] | 113 | /* Region 0 set to cover all DRAM secure at 0xC000_0000 */ |
| 114 | init_tzc400_begin(TZC_REGION_S_RDWR); |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 115 | |
| 116 | /* Raise an exception if a NS device tries to access secure memory */ |
Yann Gautier | de00f3e | 2020-08-20 16:36:07 +0200 | [diff] [blame] | 117 | init_tzc400_end(TZC_ACTION_ERR); |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | /******************************************************************************* |
| 121 | * Initialize the secure environment. At this moment only the TrustZone |
| 122 | * Controller is initialized. |
| 123 | ******************************************************************************/ |
| 124 | void stm32mp1_arch_security_setup(void) |
| 125 | { |
| 126 | early_init_tzc400(); |
| 127 | } |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 128 | |
| 129 | /******************************************************************************* |
| 130 | * Initialize the secure environment. At this moment only the TrustZone |
| 131 | * Controller is initialized. |
| 132 | ******************************************************************************/ |
| 133 | void stm32mp1_security_setup(void) |
| 134 | { |
| 135 | init_tzc400(); |
| 136 | } |