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Yann Gautiercaf575b2018-07-24 17:18:19 +02001/*
Yann Gautiercd40f322020-02-26 13:36:07 +01002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Yann Gautiercaf575b2018-07-24 17:18:19 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautiercaf575b2018-07-24 17:18:19 +02007#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <platform_def.h>
10
11#include <common/debug.h>
12#include <drivers/arm/tzc400.h>
13#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <dt-bindings/clock/stm32mp1-clks.h>
15#include <lib/mmio.h>
16
Yann Gautiere3de4c02019-04-18 15:32:10 +020017#define TZC_REGION_NSEC_ALL_ACCESS_RDWR \
18 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \
19 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | \
20 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \
21 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \
22 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | \
23 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \
24 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \
25 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \
26 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \
27 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \
28 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID)
29
Yann Gautiercaf575b2018-07-24 17:18:19 +020030/*******************************************************************************
Yann Gautier9d135e42018-07-16 19:36:06 +020031 * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
32 * and allow Non-Secure masters full access.
33 ******************************************************************************/
34static void init_tzc400(void)
35{
36 unsigned long long region_base, region_top;
Yann Gautiera2e2a302019-02-14 11:13:39 +010037 unsigned long long ddr_base = STM32MP_DDR_BASE;
Yann Gautiercd40f322020-02-26 13:36:07 +010038 unsigned long long ddr_ns_size =
39 (unsigned long long)stm32mp_get_ddr_ns_size();
40 unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U);
Yann Gautier9d135e42018-07-16 19:36:06 +020041
42 tzc400_init(STM32MP1_TZC_BASE);
43
44 tzc400_disable_filters();
45
Yann Gautierb3386f72019-04-19 09:41:01 +020046 /*
47 * Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the
48 * same configuration to all filters in the TZC.
49 */
50 region_base = ddr_base;
Yann Gautiercd40f322020-02-26 13:36:07 +010051 region_top = ddr_ns_top;
Yann Gautierb3386f72019-04-19 09:41:01 +020052 tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
53 region_base,
54 region_top,
55 TZC_REGION_S_NONE,
56 TZC_REGION_NSEC_ALL_ACCESS_RDWR);
57
Yann Gautiercd40f322020-02-26 13:36:07 +010058#ifdef AARCH32_SP_OPTEE
Yann Gautierb3386f72019-04-19 09:41:01 +020059 /* Region 2 set to cover all secure DRAM. */
60 region_base = region_top + 1U;
Yann Gautiercd40f322020-02-26 13:36:07 +010061 region_top += STM32MP_DDR_S_SIZE;
Yann Gautierb3386f72019-04-19 09:41:01 +020062 tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 2,
63 region_base,
64 region_top,
65 TZC_REGION_S_RDWR,
66 0);
67
68 /* Region 3 set to cover non-secure shared memory DRAM. */
69 region_base = region_top + 1U;
Yann Gautiercd40f322020-02-26 13:36:07 +010070 region_top += STM32MP_DDR_SHMEM_SIZE;
Yann Gautierb3386f72019-04-19 09:41:01 +020071 tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 3,
72 region_base,
73 region_top,
74 TZC_REGION_S_NONE,
75 TZC_REGION_NSEC_ALL_ACCESS_RDWR);
Yann Gautierb3386f72019-04-19 09:41:01 +020076#endif
Yann Gautier9d135e42018-07-16 19:36:06 +020077
78 /* Raise an exception if a NS device tries to access secure memory */
79 tzc400_set_action(TZC_ACTION_ERR);
80
81 tzc400_enable_filters();
82}
83
84/*******************************************************************************
Yann Gautiercaf575b2018-07-24 17:18:19 +020085 * Initialize the TrustZone Controller.
86 * Early initialization create only one region with full access to secure.
87 * This setting is used before and during DDR initialization.
88 ******************************************************************************/
89static void early_init_tzc400(void)
90{
Yann Gautiere4a3c352019-02-14 10:53:33 +010091 stm32mp_clk_enable(TZC1);
92 stm32mp_clk_enable(TZC2);
Yann Gautiercaf575b2018-07-24 17:18:19 +020093
94 tzc400_init(STM32MP1_TZC_BASE);
95
96 tzc400_disable_filters();
97
Yann Gautiere3de4c02019-04-18 15:32:10 +020098 /* Region 1 set to cover Non-Secure DRAM at 0xC000_0000 */
Yann Gautiercaf575b2018-07-24 17:18:19 +020099 tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
Yann Gautiera2e2a302019-02-14 11:13:39 +0100100 STM32MP_DDR_BASE,
101 STM32MP_DDR_BASE +
102 (STM32MP_DDR_MAX_SIZE - 1U),
Yann Gautiere3de4c02019-04-18 15:32:10 +0200103 TZC_REGION_S_NONE,
Yann Gautierf9d40d52019-01-17 14:41:46 +0100104 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
Yann Gautiercaf575b2018-07-24 17:18:19 +0200105 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));
106
107 /* Raise an exception if a NS device tries to access secure memory */
108 tzc400_set_action(TZC_ACTION_ERR);
109
110 tzc400_enable_filters();
111}
112
113/*******************************************************************************
114 * Initialize the secure environment. At this moment only the TrustZone
115 * Controller is initialized.
116 ******************************************************************************/
117void stm32mp1_arch_security_setup(void)
118{
119 early_init_tzc400();
120}
Yann Gautier9d135e42018-07-16 19:36:06 +0200121
122/*******************************************************************************
123 * Initialize the secure environment. At this moment only the TrustZone
124 * Controller is initialized.
125 ******************************************************************************/
126void stm32mp1_security_setup(void)
127{
128 init_tzc400();
129}