Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 7 | #include <assert.h> |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 8 | #include <cortex_a57.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <arch_helpers.h> |
| 10 | #include <common/debug.h> |
| 11 | #include <drivers/delay_timer.h> |
| 12 | #include <lib/mmio.h> |
| 13 | #include <lib/psci/psci.h> |
| 14 | #include <plat/common/platform.h> |
| 15 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 16 | #include <bpmp.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <flowctrl.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 18 | #include <pmc.h> |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 19 | #include <platform_def.h> |
| 20 | #include <security_engine.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 21 | #include <tegra_def.h> |
| 22 | #include <tegra_private.h> |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 23 | #include <tegra_platform.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 24 | |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 25 | /* |
| 26 | * Register used to clear CPU reset signals. Each CPU has two reset |
| 27 | * signals: CPU reset (3:0) and Core reset (19:16). |
| 28 | */ |
| 29 | #define CPU_CMPLX_RESET_CLR 0x454 |
| 30 | #define CPU_CORE_RESET_MASK 0x10001 |
| 31 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 32 | /* Clock and Reset controller registers for system clock's settings */ |
| 33 | #define SCLK_RATE 0x30 |
| 34 | #define SCLK_BURST_POLICY 0x28 |
| 35 | #define SCLK_BURST_POLICY_DEFAULT 0x10000000 |
| 36 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 37 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 38 | static bool tegra_bpmp_available = true; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 39 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 40 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 41 | psci_power_state_t *req_state) |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 42 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 43 | int state_id = psci_get_pstate_id(power_state); |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 44 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 45 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 46 | /* Sanity check the requested state id */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 47 | switch (state_id) { |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 48 | case PSTATE_ID_CORE_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 49 | /* |
| 50 | * Core powerdown request only for afflvl 0 |
| 51 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 52 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; |
| 53 | |
| 54 | break; |
| 55 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 56 | case PSTATE_ID_CLUSTER_IDLE: |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 57 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 58 | /* |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 59 | * Cluster idle request for afflvl 0 |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 60 | */ |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 61 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 62 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 63 | break; |
| 64 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 65 | case PSTATE_ID_SOC_POWERDN: |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 66 | |
| 67 | /* |
| 68 | * sc7entry-fw must be present in the system when the bpmp |
| 69 | * firmware is not present, for a successful System Suspend |
| 70 | * entry. |
| 71 | */ |
| 72 | if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base) |
| 73 | return PSCI_E_NOT_SUPPORTED; |
| 74 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 75 | /* |
| 76 | * System powerdown request only for afflvl 2 |
| 77 | */ |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 78 | for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 79 | req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| 80 | |
| 81 | req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = |
| 82 | PLAT_SYS_SUSPEND_STATE_ID; |
| 83 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 84 | break; |
| 85 | |
| 86 | default: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 87 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
| 88 | return PSCI_E_INVALID_PARAMS; |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | return PSCI_E_SUCCESS; |
| 92 | } |
| 93 | |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 94 | /******************************************************************************* |
| 95 | * Platform handler to calculate the proper target power level at the |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 96 | * specified affinity level. |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 97 | ******************************************************************************/ |
| 98 | plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, |
| 99 | const plat_local_state_t *states, |
| 100 | unsigned int ncpu) |
| 101 | { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 102 | plat_local_state_t target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 103 | int cpu = plat_my_core_pos(); |
| 104 | int core_pos = read_mpidr() & MPIDR_CPU_MASK; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 105 | uint32_t bpmp_reply, data[3], val; |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 106 | int ret; |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 107 | |
| 108 | /* get the power state at this level */ |
| 109 | if (lvl == MPIDR_AFFLVL1) |
| 110 | target = *(states + core_pos); |
| 111 | if (lvl == MPIDR_AFFLVL2) |
| 112 | target = *(states + cpu); |
| 113 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 114 | if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { |
| 115 | |
| 116 | /* initialize the bpmp interface */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 117 | ret = tegra_bpmp_init(); |
| 118 | if (ret != 0U) { |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 119 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 120 | /* Cluster idle not allowed */ |
| 121 | target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 122 | |
| 123 | /******************************************* |
| 124 | * BPMP is not present, so handle CC6 entry |
| 125 | * from the CPU |
| 126 | ******************************************/ |
| 127 | |
| 128 | /* check if cluster idle state has been enabled */ |
| 129 | val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL); |
| 130 | if (val == ENABLE_CLOSED_LOOP) { |
| 131 | /* |
| 132 | * flag to indicate that BPMP firmware is not |
| 133 | * available and the CPU has to handle entry/exit |
| 134 | * for all power states |
| 135 | */ |
| 136 | tegra_bpmp_available = false; |
| 137 | |
| 138 | /* |
| 139 | * Acquire the cluster idle lock to stop |
| 140 | * other CPUs from powering up. |
| 141 | */ |
| 142 | tegra_fc_ccplex_pgexit_lock(); |
| 143 | |
| 144 | /* Cluster idle only from the last standing CPU */ |
| 145 | if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) { |
| 146 | /* Cluster idle allowed */ |
| 147 | target = PSTATE_ID_CLUSTER_IDLE; |
| 148 | } else { |
| 149 | /* release cluster idle lock */ |
| 150 | tegra_fc_ccplex_pgexit_unlock(); |
| 151 | } |
| 152 | } |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 153 | } else { |
| 154 | |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 155 | /* Cluster power-down */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 156 | data[0] = (uint32_t)cpu; |
| 157 | data[1] = TEGRA_PM_CC6; |
| 158 | data[2] = TEGRA_PM_SC1; |
| 159 | ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, |
| 160 | (void *)&data, (int)sizeof(data), |
| 161 | (void *)&bpmp_reply, |
| 162 | (int)sizeof(bpmp_reply)); |
| 163 | |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 164 | /* check if cluster power down is allowed */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 165 | if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { |
| 166 | |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 167 | /* Cluster power down not allowed */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 168 | target = PSCI_LOCAL_STATE_RUN; |
| 169 | } |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 170 | } |
| 171 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 172 | } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && |
| 173 | (target == PSTATE_ID_SOC_POWERDN)) { |
| 174 | |
| 175 | /* System Suspend */ |
| 176 | target = PSTATE_ID_SOC_POWERDN; |
| 177 | |
| 178 | } else { |
| 179 | ; /* do nothing */ |
| 180 | } |
| 181 | |
| 182 | return target; |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 183 | } |
| 184 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 185 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 186 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 187 | u_register_t mpidr = read_mpidr(); |
| 188 | const plat_local_state_t *pwr_domain_state = |
| 189 | target_state->pwr_domain_state; |
| 190 | unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; |
| 191 | unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; |
| 192 | unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 193 | uint32_t cfg; |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 194 | int ret = PSCI_E_SUCCESS; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 195 | uint32_t val; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 196 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 197 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 198 | |
Harvey Hsieh | 20e9fef | 2016-12-28 21:53:18 +0800 | [diff] [blame] | 199 | assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 200 | (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); |
Harvey Hsieh | 20e9fef | 2016-12-28 21:53:18 +0800 | [diff] [blame] | 201 | assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 202 | (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); |
| 203 | |
| 204 | if (tegra_chipid_is_t210_b01()) { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 205 | |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 206 | /* Suspend se/se2 and pka1 */ |
| 207 | if (tegra_se_suspend() != 0) { |
| 208 | ret = PSCI_E_INTERN_FAIL; |
| 209 | } |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 210 | } |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 211 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 212 | } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 213 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 214 | assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 215 | |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 216 | if (!tegra_bpmp_available) { |
| 217 | |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 218 | /* Find if the platform uses OVR2/MAX77621 PMIC */ |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 219 | cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); |
| 220 | if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 221 | /* OVR2 */ |
| 222 | |
| 223 | /* PWM tristate */ |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 224 | val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); |
| 225 | val |= PINMUX_PWM_TRISTATE; |
| 226 | mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 227 | |
| 228 | /* |
| 229 | * SCRATCH201[1] is being used to identify CPU |
| 230 | * PMIC in warmboot code. |
| 231 | * 0 : OVR2 |
| 232 | * 1 : MAX77621 |
| 233 | */ |
| 234 | tegra_pmc_write_32(PMC_SCRATCH201, 0x0); |
| 235 | } else { |
| 236 | /* MAX77621 */ |
| 237 | tegra_pmc_write_32(PMC_SCRATCH201, 0x2); |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 238 | } |
| 239 | } |
| 240 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 241 | /* Prepare for cluster idle */ |
| 242 | tegra_fc_cluster_idle(mpidr); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 243 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 244 | } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { |
| 245 | |
| 246 | /* Prepare for cpu powerdn */ |
| 247 | tegra_fc_cpu_powerdn(mpidr); |
| 248 | |
| 249 | } else { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 250 | ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, |
| 251 | stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 252 | ret = PSCI_E_NOT_SUPPORTED; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 253 | } |
| 254 | |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 255 | return ret; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 256 | } |
| 257 | |
Harvey Hsieh | a16d4ea | 2017-06-15 16:28:43 -0700 | [diff] [blame] | 258 | int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
| 259 | { |
| 260 | u_register_t mpidr = read_mpidr(); |
| 261 | const plat_local_state_t *pwr_domain_state = |
| 262 | target_state->pwr_domain_state; |
| 263 | unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 264 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
| 265 | uint32_t val; |
Harvey Hsieh | a16d4ea | 2017-06-15 16:28:43 -0700 | [diff] [blame] | 266 | |
| 267 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 268 | |
| 269 | if (tegra_chipid_is_t210_b01()) { |
| 270 | /* Save tzram contents */ |
| 271 | tegra_se_save_tzram(); |
| 272 | } |
| 273 | |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 274 | /* |
| 275 | * The CPU needs to load the System suspend entry firmware |
| 276 | * if nothing is running on the BPMP. |
| 277 | */ |
| 278 | if (!tegra_bpmp_available) { |
| 279 | |
| 280 | /* |
| 281 | * BPMP firmware is not running on the co-processor, so |
| 282 | * we need to explicitly load the firmware to enable |
| 283 | * entry/exit to/from System Suspend and set the BPMP |
| 284 | * on its way. |
| 285 | */ |
| 286 | |
| 287 | /* Power off BPMP before we proceed */ |
| 288 | tegra_fc_bpmp_off(); |
| 289 | |
| 290 | /* Copy the firmware to BPMP's internal RAM */ |
| 291 | (void)memcpy((void *)(uintptr_t)TEGRA_IRAM_BASE, |
| 292 | (const void *)plat_params->sc7entry_fw_base, |
| 293 | plat_params->sc7entry_fw_size); |
| 294 | |
| 295 | /* Power on the BPMP and execute from IRAM base */ |
| 296 | tegra_fc_bpmp_on(TEGRA_IRAM_BASE); |
| 297 | |
| 298 | /* Wait until BPMP powers up */ |
| 299 | do { |
| 300 | val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET); |
| 301 | } while (val != SIGN_OF_LIFE); |
| 302 | } |
| 303 | |
Harvey Hsieh | a16d4ea | 2017-06-15 16:28:43 -0700 | [diff] [blame] | 304 | /* enter system suspend */ |
| 305 | tegra_fc_soc_powerdn(mpidr); |
| 306 | } |
| 307 | |
| 308 | return PSCI_E_SUCCESS; |
| 309 | } |
| 310 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 311 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 312 | { |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 313 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 314 | uint32_t cfg; |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 315 | uint32_t val, entrypoint = 0; |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 316 | |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 317 | /* platform parameter passed by the previous bootloader */ |
| 318 | if (plat_params->l2_ecc_parity_prot_dis != 1) { |
| 319 | /* Enable ECC Parity Protection for Cortex-A57 CPUs */ |
| 320 | val = read_l2ctlr_el1(); |
| 321 | val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; |
| 322 | write_l2ctlr_el1(val); |
| 323 | } |
| 324 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 325 | /* |
| 326 | * Check if we are exiting from SOC_POWERDN. |
| 327 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 328 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 329 | PLAT_SYS_SUSPEND_STATE_ID) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 330 | |
| 331 | /* |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 332 | * Security engine resume |
| 333 | */ |
| 334 | if (tegra_chipid_is_t210_b01()) { |
| 335 | tegra_se_resume(); |
| 336 | } |
| 337 | |
| 338 | /* |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 339 | * Lock scratch registers which hold the CPU vectors |
| 340 | */ |
| 341 | tegra_pmc_lock_cpu_vectors(); |
| 342 | |
| 343 | /* |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 344 | * Enable WRAP to INCR burst type conversions for |
| 345 | * incoming requests on the AXI slave ports. |
| 346 | */ |
| 347 | val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); |
| 348 | val &= ~ENABLE_UNSUP_TX_ERRORS; |
| 349 | val |= ENABLE_WRAP_TO_INCR_BURSTS; |
| 350 | mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); |
| 351 | |
| 352 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 353 | * Restore Boot and Power Management Processor (BPMP) reset |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 354 | * address and reset it, if it is supported by the platform. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 355 | */ |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame^] | 356 | if (!tegra_bpmp_available) { |
| 357 | tegra_fc_bpmp_off(); |
| 358 | } else { |
| 359 | entrypoint = tegra_pmc_read_32(PMC_SCRATCH39); |
| 360 | tegra_fc_bpmp_on(entrypoint); |
| 361 | } |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 362 | } |
| 363 | |
| 364 | /* |
| 365 | * Check if we are exiting cluster idle state |
| 366 | */ |
| 367 | if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == |
| 368 | PSTATE_ID_CLUSTER_IDLE) { |
| 369 | |
| 370 | if (!tegra_bpmp_available) { |
| 371 | |
| 372 | /* PWM un-tristate */ |
| 373 | cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); |
| 374 | if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { |
| 375 | val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); |
| 376 | val &= ~PINMUX_PWM_TRISTATE; |
| 377 | mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); |
| 378 | } |
| 379 | |
| 380 | /* release cluster idle lock */ |
| 381 | tegra_fc_ccplex_pgexit_unlock(); |
| 382 | } |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 383 | } |
| 384 | |
| 385 | /* |
| 386 | * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's |
| 387 | * used for power management and boot purposes. Inform the BPMP that |
| 388 | * we have completed the cluster power up. |
| 389 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 390 | tegra_fc_lock_active_cluster(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 391 | |
| 392 | return PSCI_E_SUCCESS; |
| 393 | } |
| 394 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 395 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 396 | { |
| 397 | int cpu = mpidr & MPIDR_CPU_MASK; |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 398 | uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| 399 | |
| 400 | /* Deassert CPU reset signals */ |
| 401 | mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 402 | |
| 403 | /* Turn on CPU using flow controller or PMC */ |
| 404 | if (cpu_powergate_mask[cpu] == 0) { |
| 405 | tegra_pmc_cpu_on(cpu); |
| 406 | cpu_powergate_mask[cpu] = 1; |
| 407 | } else { |
| 408 | tegra_fc_cpu_on(cpu); |
| 409 | } |
| 410 | |
| 411 | return PSCI_E_SUCCESS; |
| 412 | } |
| 413 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 414 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 415 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 416 | tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 417 | return PSCI_E_SUCCESS; |
| 418 | } |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 419 | |
| 420 | int tegra_soc_prepare_system_reset(void) |
| 421 | { |
| 422 | /* |
| 423 | * Set System Clock (SCLK) to POR default so that the clock source |
| 424 | * for the PMC APB clock would not be changed due to system reset. |
| 425 | */ |
| 426 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 427 | SCLK_BURST_POLICY_DEFAULT); |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 428 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); |
| 429 | |
| 430 | /* Wait 1 ms to make sure clock source/device logic is stabilized. */ |
| 431 | mdelay(1); |
| 432 | |
| 433 | return PSCI_E_SUCCESS; |
| 434 | } |