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Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
Varun Wadekarb8776152016-03-03 13:52:52 -08002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +05305 */
6
Varun Wadekarcad7b082015-12-28 18:12:59 -08007#include <arch_helpers.h>
8#include <assert.h>
Varun Wadekar94701ff2016-05-23 11:47:34 -07009#include <bl31.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080010#include <bl_common.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053011#include <console.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080012#include <context.h>
13#include <context_mgmt.h>
Varun Wadekar4debe052016-05-18 13:39:16 -070014#include <cortex_a57.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080015#include <debug.h>
16#include <denver.h>
17#include <interrupt_mgmt.h>
Varun Wadekar47ddd002016-03-28 16:00:02 -070018#include <mce.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080019#include <platform.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053020#include <tegra_def.h>
Varun Wadekar5887c102016-07-19 11:29:40 -070021#include <tegra_platform.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080022#include <tegra_private.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053023#include <xlat_tables.h>
24
Varun Wadekar1384a162017-06-05 14:54:46 -070025DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
Varun Wadekar4debe052016-05-18 13:39:16 -070026extern uint64_t tegra_enable_l2_ecc_parity_prot;
27
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080028/*******************************************************************************
Varun Wadekar43dad672017-01-31 14:53:37 -080029 * Tegra186 CPU numbers in cluster #0
30 *******************************************************************************
31 */
32#define TEGRA186_CLUSTER0_CORE2 2
33#define TEGRA186_CLUSTER0_CORE3 3
34
35/*******************************************************************************
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080036 * The Tegra power domain tree has a single system level power domain i.e. a
37 * single root node. The first entry in the power domain descriptor specifies
38 * the number of power domains at the highest power level.
39 *******************************************************************************
40 */
41const unsigned char tegra_power_domain_tree_desc[] = {
42 /* No of root nodes */
43 1,
44 /* No of clusters */
45 PLATFORM_CLUSTER_COUNT,
46 /* No of CPU cores - cluster0 */
47 PLATFORM_MAX_CPUS_PER_CLUSTER,
48 /* No of CPU cores - cluster1 */
49 PLATFORM_MAX_CPUS_PER_CLUSTER
50};
51
Varun Wadekar921b9062015-08-25 17:03:14 +053052/*
53 * Table of regions to map using the MMU.
54 */
55static const mmap_region_t tegra_mmap[] = {
56 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
57 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekara0f26972016-03-11 17:18:51 -080058 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
59 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053060 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
61 MT_DEVICE | MT_RW | MT_SECURE),
62 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
63 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar9db0ad12016-07-12 10:04:28 -070064 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
65 MT_DEVICE | MT_RW | MT_SECURE),
66 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
67 MT_DEVICE | MT_RW | MT_SECURE),
68 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
Varun Wadekar921b9062015-08-25 17:03:14 +053069 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar4debe052016-05-18 13:39:16 -070070 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
71 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053072 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
73 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb8776152016-03-03 13:52:52 -080074 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
75 MT_DEVICE | MT_RW | MT_SECURE),
76 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
77 MT_DEVICE | MT_RW | MT_SECURE),
78 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
79 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekare60f1bf2016-02-17 10:10:50 -080080 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
81 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053082 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
83 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb8776152016-03-03 13:52:52 -080084 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
85 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053086 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
87 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekard64db962016-09-23 14:28:16 -070088 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */
89 MT_DEVICE | MT_RW | MT_SECURE),
Pritesh Raithatha0de6e532017-01-24 13:49:46 +053090 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053091 MT_DEVICE | MT_RW | MT_SECURE),
92 {0}
93};
94
95/*******************************************************************************
96 * Set up the pagetables as per the platform memory map & initialize the MMU
97 ******************************************************************************/
98const mmap_region_t *plat_get_mmio_map(void)
99{
100 /* MMIO space */
101 return tegra_mmap;
102}
103
104/*******************************************************************************
105 * Handler to get the System Counter Frequency
106 ******************************************************************************/
Varun Wadekaref8a4fe2016-06-02 14:26:13 -0700107unsigned int plat_get_syscnt_freq2(void)
Varun Wadekar921b9062015-08-25 17:03:14 +0530108{
Varun Wadekar20c94292016-01-04 10:57:45 -0800109 return 31250000;
Varun Wadekar921b9062015-08-25 17:03:14 +0530110}
111
112/*******************************************************************************
113 * Maximum supported UART controllers
114 ******************************************************************************/
115#define TEGRA186_MAX_UART_PORTS 7
116
117/*******************************************************************************
118 * This variable holds the UART port base addresses
119 ******************************************************************************/
120static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
121 0, /* undefined - treated as an error case */
122 TEGRA_UARTA_BASE,
123 TEGRA_UARTB_BASE,
124 TEGRA_UARTC_BASE,
125 TEGRA_UARTD_BASE,
126 TEGRA_UARTE_BASE,
127 TEGRA_UARTF_BASE,
128 TEGRA_UARTG_BASE,
129};
130
131/*******************************************************************************
132 * Retrieve the UART controller base to be used as the console
133 ******************************************************************************/
134uint32_t plat_get_console_from_id(int id)
135{
136 if (id > TEGRA186_MAX_UART_PORTS)
137 return 0;
138
139 return tegra186_uart_addresses[id];
140}
Varun Wadekarcad7b082015-12-28 18:12:59 -0800141
Varun Wadekar4debe052016-05-18 13:39:16 -0700142/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */
143#define TEGRA186_VER_A02P 0x1201
144
145/*******************************************************************************
146 * Handler for early platform setup
147 ******************************************************************************/
148void plat_early_platform_setup(void)
149{
150 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
Varun Wadekar5887c102016-07-19 11:29:40 -0700151 uint32_t chip_subrev, val;
Varun Wadekar4debe052016-05-18 13:39:16 -0700152
153 /* sanity check MCE firmware compatibility */
154 mce_verify_firmware_version();
155
156 /*
157 * Enable ECC and Parity Protection for Cortex-A57 CPUs
158 * for Tegra A02p SKUs
159 */
160 if (impl != DENVER_IMPL) {
161
162 /* get the major, minor and sub-version values */
Varun Wadekar4debe052016-05-18 13:39:16 -0700163 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) &
164 SUBREVISION_MASK;
165
166 /* prepare chip version number */
Varun Wadekar5887c102016-07-19 11:29:40 -0700167 val = (tegra_get_chipid_major() << 12) |
168 (tegra_get_chipid_minor() << 8) |
169 chip_subrev;
Varun Wadekar4debe052016-05-18 13:39:16 -0700170
171 /* enable L2 ECC for Tegra186 A02P and beyond */
172 if (val >= TEGRA186_VER_A02P) {
173
174 val = read_l2ctlr_el1();
Varun Wadekar1384a162017-06-05 14:54:46 -0700175 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
Varun Wadekar4debe052016-05-18 13:39:16 -0700176 write_l2ctlr_el1(val);
177
178 /*
179 * Set the flag to enable ECC/Parity Protection
180 * when we exit System Suspend or Cluster Powerdn
181 */
182 tegra_enable_l2_ecc_parity_prot = 1;
183 }
184 }
185}
186
Varun Wadekarcad7b082015-12-28 18:12:59 -0800187/* Secure IRQs for Tegra186 */
188static const irq_sec_cfg_t tegra186_sec_irqs[] = {
189 {
190 TEGRA186_TOP_WDT_IRQ,
191 TEGRA186_SEC_IRQ_TARGET_MASK,
192 INTR_TYPE_EL3,
193 },
194 {
195 TEGRA186_AON_WDT_IRQ,
196 TEGRA186_SEC_IRQ_TARGET_MASK,
197 INTR_TYPE_EL3,
198 },
199};
200
201/*******************************************************************************
202 * Initialize the GIC and SGIs
203 ******************************************************************************/
204void plat_gic_setup(void)
205{
206 tegra_gic_setup(tegra186_sec_irqs,
207 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
208
209 /*
210 * Initialize the FIQ handler only if the platform supports any
211 * FIQ interrupt sources.
212 */
213 if (sizeof(tegra186_sec_irqs) > 0)
214 tegra_fiq_handler_setup();
215}
Varun Wadekar94701ff2016-05-23 11:47:34 -0700216
217/*******************************************************************************
218 * Return pointer to the BL31 params from previous bootloader
219 ******************************************************************************/
220bl31_params_t *plat_get_bl31_params(void)
221{
222 uint32_t val;
223
224 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
225
226 return (bl31_params_t *)(uintptr_t)val;
227}
228
229/*******************************************************************************
230 * Return pointer to the BL31 platform params from previous bootloader
231 ******************************************************************************/
232plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
233{
234 uint32_t val;
235
236 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
237
238 return (plat_params_from_bl2_t *)(uintptr_t)val;
239}
Varun Wadekar43dad672017-01-31 14:53:37 -0800240
241/*******************************************************************************
242 * This function implements a part of the critical interface between the psci
243 * generic layer and the platform that allows the former to query the platform
244 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
245 * in case the MPIDR is invalid.
246 ******************************************************************************/
247int plat_core_pos_by_mpidr(u_register_t mpidr)
248{
249 unsigned int cluster_id, cpu_id, pos;
250
251 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
252 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
253
254 /*
255 * Validate cluster_id by checking whether it represents
256 * one of the two clusters present on the platform.
257 */
258 if (cluster_id >= PLATFORM_CLUSTER_COUNT)
259 return PSCI_E_NOT_PRESENT;
260
261 /*
262 * Validate cpu_id by checking whether it represents a CPU in
263 * one of the two clusters present on the platform.
264 */
265 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
266 return PSCI_E_NOT_PRESENT;
267
268 /* calculate the core position */
269 pos = cpu_id + (cluster_id << 2);
270
271 /* check for non-existent CPUs */
272 if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3)
273 return PSCI_E_NOT_PRESENT;
274
275 return pos;
276}