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Yann Gautier9aea69e2018-07-24 17:13:36 +02001/*
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01002 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
Yann Gautier9aea69e2018-07-24 17:13:36 +02003 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
Yann Gautier9aea69e2018-07-24 17:13:36 +02007#include <assert.h>
Yann Gautier9aea69e2018-07-24 17:13:36 +02008#include <errno.h>
Yann Gautier9aea69e2018-07-24 17:13:36 +02009#include <stdint.h>
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010010#include <stdio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <arch.h>
13#include <arch_helpers.h>
14#include <common/debug.h>
Andre Przywaracc99f3f2020-03-26 12:51:21 +000015#include <common/fdt_wrappers.h>
Yann Gautiera205a5c2021-08-30 15:06:54 +020016#include <drivers/clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <drivers/delay_timer.h>
Yann Gautier4d429472019-02-14 11:15:20 +010018#include <drivers/st/stm32mp_clkfunc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <drivers/st/stm32mp1_rcc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <dt-bindings/clock/stm32mp1-clksrc.h>
22#include <lib/mmio.h>
Yann Gautiere4a3c352019-02-14 10:53:33 +010023#include <lib/spinlock.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <lib/utils_def.h>
Nicolas Le Bayondab197a2019-11-13 11:46:31 +010025#include <libfdt.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000026#include <plat/common/platform.h>
27
Nicolas Le Bayondab197a2019-11-13 11:46:31 +010028#include <platform_def.h>
29
Yann Gautier2299d572019-02-14 11:14:39 +010030#define MAX_HSI_HZ 64000000
Yann Gautiere4a3c352019-02-14 10:53:33 +010031#define USB_PHY_48_MHZ 48000000
Yann Gautier9aea69e2018-07-24 17:13:36 +020032
Yann Gautier2299d572019-02-14 11:14:39 +010033#define TIMEOUT_US_200MS U(200000)
34#define TIMEOUT_US_1S U(1000000)
Yann Gautier9aea69e2018-07-24 17:13:36 +020035
Yann Gautier2299d572019-02-14 11:14:39 +010036#define PLLRDY_TIMEOUT TIMEOUT_US_200MS
37#define CLKSRC_TIMEOUT TIMEOUT_US_200MS
38#define CLKDIV_TIMEOUT TIMEOUT_US_200MS
39#define HSIDIV_TIMEOUT TIMEOUT_US_200MS
40#define OSCRDY_TIMEOUT TIMEOUT_US_1S
Yann Gautier9aea69e2018-07-24 17:13:36 +020041
Yann Gautier5f2e8742019-05-17 15:57:56 +020042const char *stm32mp_osc_node_label[NB_OSC] = {
43 [_LSI] = "clk-lsi",
44 [_LSE] = "clk-lse",
45 [_HSI] = "clk-hsi",
46 [_HSE] = "clk-hse",
47 [_CSI] = "clk-csi",
48 [_I2S_CKIN] = "i2s_ckin",
49};
50
Yann Gautier9aea69e2018-07-24 17:13:36 +020051enum stm32mp1_parent_id {
52/* Oscillators are defined in enum stm32mp_osc_id */
53
54/* Other parent source */
55 _HSI_KER = NB_OSC,
56 _HSE_KER,
57 _HSE_KER_DIV2,
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +020058 _HSE_RTC,
Yann Gautier9aea69e2018-07-24 17:13:36 +020059 _CSI_KER,
60 _PLL1_P,
61 _PLL1_Q,
62 _PLL1_R,
63 _PLL2_P,
64 _PLL2_Q,
65 _PLL2_R,
66 _PLL3_P,
67 _PLL3_Q,
68 _PLL3_R,
69 _PLL4_P,
70 _PLL4_Q,
71 _PLL4_R,
72 _ACLK,
73 _PCLK1,
74 _PCLK2,
75 _PCLK3,
76 _PCLK4,
77 _PCLK5,
78 _HCLK6,
79 _HCLK2,
80 _CK_PER,
81 _CK_MPU,
Yann Gautiered342322019-02-15 17:33:27 +010082 _CK_MCU,
Yann Gautiere4a3c352019-02-14 10:53:33 +010083 _USB_PHY_48,
Yann Gautier9aea69e2018-07-24 17:13:36 +020084 _PARENT_NB,
85 _UNKNOWN_ID = 0xff,
86};
87
Yann Gautiere4a3c352019-02-14 10:53:33 +010088/* Lists only the parent clock we are interested in */
Yann Gautier9aea69e2018-07-24 17:13:36 +020089enum stm32mp1_parent_sel {
Yann Gautiere4a3c352019-02-14 10:53:33 +010090 _I2C12_SEL,
91 _I2C35_SEL,
92 _STGEN_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +020093 _I2C46_SEL,
Yann Gautiere4a3c352019-02-14 10:53:33 +010094 _SPI6_SEL,
Yann Gautier9d8bbcd2019-05-07 18:49:33 +020095 _UART1_SEL,
Yann Gautiere4a3c352019-02-14 10:53:33 +010096 _RNG1_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +020097 _UART6_SEL,
98 _UART24_SEL,
99 _UART35_SEL,
100 _UART78_SEL,
101 _SDMMC12_SEL,
102 _SDMMC3_SEL,
103 _QSPI_SEL,
104 _FMC_SEL,
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200105 _AXIS_SEL,
106 _MCUS_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200107 _USBPHY_SEL,
108 _USBO_SEL,
Etienne Carriere04132612019-12-08 08:20:12 +0100109 _MPU_SEL,
Yann Gautierfaa9bcf2021-08-31 18:23:13 +0200110 _CKPER_SEL,
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100111 _RTC_SEL,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200112 _PARENT_SEL_NB,
113 _UNKNOWN_SEL = 0xff,
114};
115
Etienne Carriere04132612019-12-08 08:20:12 +0100116/* State the parent clock ID straight related to a clock */
117static const uint8_t parent_id_clock_id[_PARENT_NB] = {
118 [_HSE] = CK_HSE,
119 [_HSI] = CK_HSI,
120 [_CSI] = CK_CSI,
121 [_LSE] = CK_LSE,
122 [_LSI] = CK_LSI,
123 [_I2S_CKIN] = _UNKNOWN_ID,
124 [_USB_PHY_48] = _UNKNOWN_ID,
125 [_HSI_KER] = CK_HSI,
126 [_HSE_KER] = CK_HSE,
127 [_HSE_KER_DIV2] = CK_HSE_DIV2,
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +0200128 [_HSE_RTC] = _UNKNOWN_ID,
Etienne Carriere04132612019-12-08 08:20:12 +0100129 [_CSI_KER] = CK_CSI,
130 [_PLL1_P] = PLL1_P,
131 [_PLL1_Q] = PLL1_Q,
132 [_PLL1_R] = PLL1_R,
133 [_PLL2_P] = PLL2_P,
134 [_PLL2_Q] = PLL2_Q,
135 [_PLL2_R] = PLL2_R,
136 [_PLL3_P] = PLL3_P,
137 [_PLL3_Q] = PLL3_Q,
138 [_PLL3_R] = PLL3_R,
139 [_PLL4_P] = PLL4_P,
140 [_PLL4_Q] = PLL4_Q,
141 [_PLL4_R] = PLL4_R,
142 [_ACLK] = CK_AXI,
143 [_PCLK1] = CK_AXI,
144 [_PCLK2] = CK_AXI,
145 [_PCLK3] = CK_AXI,
146 [_PCLK4] = CK_AXI,
147 [_PCLK5] = CK_AXI,
148 [_CK_PER] = CK_PER,
149 [_CK_MPU] = CK_MPU,
150 [_CK_MCU] = CK_MCU,
151};
152
153static unsigned int clock_id2parent_id(unsigned long id)
154{
155 unsigned int n;
156
157 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) {
158 if (parent_id_clock_id[n] == id) {
159 return n;
160 }
161 }
162
163 return _UNKNOWN_ID;
164}
165
Yann Gautier9aea69e2018-07-24 17:13:36 +0200166enum stm32mp1_pll_id {
167 _PLL1,
168 _PLL2,
169 _PLL3,
170 _PLL4,
171 _PLL_NB
172};
173
174enum stm32mp1_div_id {
175 _DIV_P,
176 _DIV_Q,
177 _DIV_R,
178 _DIV_NB,
179};
180
181enum stm32mp1_clksrc_id {
182 CLKSRC_MPU,
183 CLKSRC_AXI,
Yann Gautiered342322019-02-15 17:33:27 +0100184 CLKSRC_MCU,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200185 CLKSRC_PLL12,
186 CLKSRC_PLL3,
187 CLKSRC_PLL4,
188 CLKSRC_RTC,
189 CLKSRC_MCO1,
190 CLKSRC_MCO2,
191 CLKSRC_NB
192};
193
194enum stm32mp1_clkdiv_id {
195 CLKDIV_MPU,
196 CLKDIV_AXI,
Yann Gautiered342322019-02-15 17:33:27 +0100197 CLKDIV_MCU,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200198 CLKDIV_APB1,
199 CLKDIV_APB2,
200 CLKDIV_APB3,
201 CLKDIV_APB4,
202 CLKDIV_APB5,
203 CLKDIV_RTC,
204 CLKDIV_MCO1,
205 CLKDIV_MCO2,
206 CLKDIV_NB
207};
208
209enum stm32mp1_pllcfg {
210 PLLCFG_M,
211 PLLCFG_N,
212 PLLCFG_P,
213 PLLCFG_Q,
214 PLLCFG_R,
215 PLLCFG_O,
216 PLLCFG_NB
217};
218
219enum stm32mp1_pllcsg {
220 PLLCSG_MOD_PER,
221 PLLCSG_INC_STEP,
222 PLLCSG_SSCG_MODE,
223 PLLCSG_NB
224};
225
226enum stm32mp1_plltype {
227 PLL_800,
228 PLL_1600,
229 PLL_TYPE_NB
230};
231
232struct stm32mp1_pll {
233 uint8_t refclk_min;
234 uint8_t refclk_max;
235 uint8_t divn_max;
236};
237
238struct stm32mp1_clk_gate {
239 uint16_t offset;
240 uint8_t bit;
241 uint8_t index;
242 uint8_t set_clr;
Yann Gautierb2edbc32021-10-27 18:16:59 +0200243 uint8_t secure;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100244 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */
245 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */
Yann Gautier9aea69e2018-07-24 17:13:36 +0200246};
247
248struct stm32mp1_clk_sel {
249 uint16_t offset;
250 uint8_t src;
251 uint8_t msk;
252 uint8_t nb_parent;
253 const uint8_t *parent;
254};
255
256#define REFCLK_SIZE 4
257struct stm32mp1_clk_pll {
258 enum stm32mp1_plltype plltype;
259 uint16_t rckxselr;
260 uint16_t pllxcfgr1;
261 uint16_t pllxcfgr2;
262 uint16_t pllxfracr;
263 uint16_t pllxcr;
264 uint16_t pllxcsgr;
265 enum stm32mp_osc_id refclk[REFCLK_SIZE];
266};
267
Yann Gautiere4a3c352019-02-14 10:53:33 +0100268/* Clocks with selectable source and non set/clr register access */
Yann Gautierb2edbc32021-10-27 18:16:59 +0200269#define _CLK_SELEC(sec, off, b, idx, s) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200270 { \
271 .offset = (off), \
272 .bit = (b), \
273 .index = (idx), \
274 .set_clr = 0, \
Yann Gautierb2edbc32021-10-27 18:16:59 +0200275 .secure = (sec), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200276 .sel = (s), \
277 .fixed = _UNKNOWN_ID, \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200278 }
279
Yann Gautiere4a3c352019-02-14 10:53:33 +0100280/* Clocks with fixed source and non set/clr register access */
Yann Gautierb2edbc32021-10-27 18:16:59 +0200281#define _CLK_FIXED(sec, off, b, idx, f) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200282 { \
283 .offset = (off), \
284 .bit = (b), \
285 .index = (idx), \
286 .set_clr = 0, \
Yann Gautierb2edbc32021-10-27 18:16:59 +0200287 .secure = (sec), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200288 .sel = _UNKNOWN_SEL, \
289 .fixed = (f), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200290 }
291
Yann Gautiere4a3c352019-02-14 10:53:33 +0100292/* Clocks with selectable source and set/clr register access */
Yann Gautierb2edbc32021-10-27 18:16:59 +0200293#define _CLK_SC_SELEC(sec, off, b, idx, s) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200294 { \
295 .offset = (off), \
296 .bit = (b), \
297 .index = (idx), \
298 .set_clr = 1, \
Yann Gautierb2edbc32021-10-27 18:16:59 +0200299 .secure = (sec), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200300 .sel = (s), \
301 .fixed = _UNKNOWN_ID, \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200302 }
303
Yann Gautiere4a3c352019-02-14 10:53:33 +0100304/* Clocks with fixed source and set/clr register access */
Yann Gautierb2edbc32021-10-27 18:16:59 +0200305#define _CLK_SC_FIXED(sec, off, b, idx, f) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200306 { \
307 .offset = (off), \
308 .bit = (b), \
309 .index = (idx), \
310 .set_clr = 1, \
Yann Gautierb2edbc32021-10-27 18:16:59 +0200311 .secure = (sec), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200312 .sel = _UNKNOWN_SEL, \
313 .fixed = (f), \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200314 }
315
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200316#define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \
317 [_ ## _label ## _SEL] = { \
318 .offset = _rcc_selr, \
319 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \
Etienne Carrierec164ce22019-12-08 08:20:40 +0100320 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \
321 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200322 .parent = (_parents), \
323 .nb_parent = ARRAY_SIZE(_parents) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200324 }
325
Yann Gautiere4a3c352019-02-14 10:53:33 +0100326#define _CLK_PLL(idx, type, off1, off2, off3, \
327 off4, off5, off6, \
328 p1, p2, p3, p4) \
Yann Gautier9aea69e2018-07-24 17:13:36 +0200329 [(idx)] = { \
330 .plltype = (type), \
331 .rckxselr = (off1), \
332 .pllxcfgr1 = (off2), \
333 .pllxcfgr2 = (off3), \
334 .pllxfracr = (off4), \
335 .pllxcr = (off5), \
336 .pllxcsgr = (off6), \
337 .refclk[0] = (p1), \
338 .refclk[1] = (p2), \
339 .refclk[2] = (p3), \
340 .refclk[3] = (p4), \
341 }
342
Yann Gautiere4a3c352019-02-14 10:53:33 +0100343#define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
344
Yann Gautierb2edbc32021-10-27 18:16:59 +0200345#define SEC 1
346#define N_S 0
347
Yann Gautier9aea69e2018-07-24 17:13:36 +0200348static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
Yann Gautierb2edbc32021-10-27 18:16:59 +0200349 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK),
350 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
351 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK),
352 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
353 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
354 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
355 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
356 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
357 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK),
358 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
359 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100360
Yann Gautier56729672020-01-17 11:59:28 +0100361#if defined(IMAGE_BL32)
Yann Gautierb2edbc32021-10-27 18:16:59 +0200362 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1),
Yann Gautier56729672020-01-17 11:59:28 +0100363#endif
Yann Gautierb2edbc32021-10-27 18:16:59 +0200364 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
365 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
366 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
367 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
368 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
369 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
370 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
371 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
372 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
373 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100374
Yann Gautier56729672020-01-17 11:59:28 +0100375#if defined(IMAGE_BL32)
Yann Gautierb2edbc32021-10-27 18:16:59 +0200376 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
Yann Gautier56729672020-01-17 11:59:28 +0100377#endif
Yann Gautierb2edbc32021-10-27 18:16:59 +0200378 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100379
Yann Gautierb2edbc32021-10-27 18:16:59 +0200380 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID),
Yann Gautier3edc7c32019-05-20 19:17:08 +0200381
Yann Gautierb2edbc32021-10-27 18:16:59 +0200382 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
383 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
384 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100385
Yann Gautierb2edbc32021-10-27 18:16:59 +0200386 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
387 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
388 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
389 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
390 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
391 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5),
392 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5),
393 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5),
394 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5),
395 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5),
396 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100397
Yann Gautier56729672020-01-17 11:59:28 +0100398#if defined(IMAGE_BL32)
Yann Gautierb2edbc32021-10-27 18:16:59 +0200399 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
400 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
Yann Gautier56729672020-01-17 11:59:28 +0100401#endif
Yann Gautiere4a3c352019-02-14 10:53:33 +0100402
Yann Gautierb2edbc32021-10-27 18:16:59 +0200403 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
404 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
405 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
406 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
407 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
408 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
409 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
410 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
411 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
412 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
413 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100414
Yann Gautierb2edbc32021-10-27 18:16:59 +0200415 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5),
416 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5),
417 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5),
418 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL),
419 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100420
Yann Gautier56729672020-01-17 11:59:28 +0100421#if defined(IMAGE_BL2)
Yann Gautierb2edbc32021-10-27 18:16:59 +0200422 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
423 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
Yann Gautier56729672020-01-17 11:59:28 +0100424#endif
Yann Gautierb2edbc32021-10-27 18:16:59 +0200425 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
426 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
Yann Gautier56729672020-01-17 11:59:28 +0100427#if defined(IMAGE_BL32)
Yann Gautierb2edbc32021-10-27 18:16:59 +0200428 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
Yann Gautier56729672020-01-17 11:59:28 +0100429#endif
Yann Gautiere4a3c352019-02-14 10:53:33 +0100430
Yann Gautierb2edbc32021-10-27 18:16:59 +0200431 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL),
432 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
Yann Gautiere4a3c352019-02-14 10:53:33 +0100433};
434
435static const uint8_t i2c12_parents[] = {
436 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
437};
438
439static const uint8_t i2c35_parents[] = {
440 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
441};
442
443static const uint8_t stgen_parents[] = {
444 _HSI_KER, _HSE_KER
445};
446
447static const uint8_t i2c46_parents[] = {
448 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER
449};
450
451static const uint8_t spi6_parents[] = {
452 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q
453};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200454
Yann Gautiere4a3c352019-02-14 10:53:33 +0100455static const uint8_t usart1_parents[] = {
456 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER
457};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200458
Yann Gautiere4a3c352019-02-14 10:53:33 +0100459static const uint8_t rng1_parents[] = {
460 _CSI, _PLL4_R, _LSE, _LSI
461};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200462
Yann Gautiere4a3c352019-02-14 10:53:33 +0100463static const uint8_t uart6_parents[] = {
464 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
465};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200466
Yann Gautiere4a3c352019-02-14 10:53:33 +0100467static const uint8_t uart234578_parents[] = {
468 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
469};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200470
Yann Gautiere4a3c352019-02-14 10:53:33 +0100471static const uint8_t sdmmc12_parents[] = {
472 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER
473};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200474
Yann Gautiere4a3c352019-02-14 10:53:33 +0100475static const uint8_t sdmmc3_parents[] = {
476 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER
477};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200478
Yann Gautiere4a3c352019-02-14 10:53:33 +0100479static const uint8_t qspi_parents[] = {
480 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
481};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200482
Yann Gautiere4a3c352019-02-14 10:53:33 +0100483static const uint8_t fmc_parents[] = {
484 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
485};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200486
Etienne Carriere40c28e82019-12-19 10:03:23 +0100487static const uint8_t axiss_parents[] = {
488 _HSI, _HSE, _PLL2_P
Yann Gautier9aea69e2018-07-24 17:13:36 +0200489};
490
Etienne Carriere40c28e82019-12-19 10:03:23 +0100491static const uint8_t mcuss_parents[] = {
492 _HSI, _HSE, _CSI, _PLL3_P
Yann Gautiered342322019-02-15 17:33:27 +0100493};
494
Yann Gautiere4a3c352019-02-14 10:53:33 +0100495static const uint8_t usbphy_parents[] = {
496 _HSE_KER, _PLL4_R, _HSE_KER_DIV2
497};
498
499static const uint8_t usbo_parents[] = {
500 _PLL4_R, _USB_PHY_48
501};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200502
Etienne Carriere04132612019-12-08 08:20:12 +0100503static const uint8_t mpu_parents[] = {
504 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */
505};
506
507static const uint8_t per_parents[] = {
508 _HSI, _HSE, _CSI,
509};
510
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100511static const uint8_t rtc_parents[] = {
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +0200512 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100513};
514
Yann Gautier9aea69e2018-07-24 17:13:36 +0200515static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200516 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents),
517 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents),
518 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents),
519 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents),
520 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents),
521 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents),
522 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents),
Etienne Carriere04132612019-12-08 08:20:12 +0100523 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents),
Yann Gautierfaa9bcf2021-08-31 18:23:13 +0200524 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents),
Etienne Carrierebccc7d02019-12-08 08:22:31 +0100525 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents),
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200526 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents),
527 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents),
528 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents),
529 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents),
530 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents),
531 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents),
532 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents),
533 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents),
Etienne Carriere40c28e82019-12-19 10:03:23 +0100534 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents),
535 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents),
Yann Gautier9d8bbcd2019-05-07 18:49:33 +0200536 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents),
537 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents),
Yann Gautier9aea69e2018-07-24 17:13:36 +0200538};
539
540/* Define characteristic of PLL according type */
541#define DIVN_MIN 24
542static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
543 [PLL_800] = {
544 .refclk_min = 4,
545 .refclk_max = 16,
546 .divn_max = 99,
547 },
548 [PLL_1600] = {
549 .refclk_min = 8,
550 .refclk_max = 16,
551 .divn_max = 199,
552 },
553};
554
555/* PLLNCFGR2 register divider by output */
556static const uint8_t pllncfgr2[_DIV_NB] = {
557 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
558 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
Yann Gautiere4a3c352019-02-14 10:53:33 +0100559 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200560};
561
562static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100563 _CLK_PLL(_PLL1, PLL_1600,
564 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
565 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
566 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
567 _CLK_PLL(_PLL2, PLL_1600,
568 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
569 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
570 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
571 _CLK_PLL(_PLL3, PLL_800,
572 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
573 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
574 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID),
575 _CLK_PLL(_PLL4, PLL_800,
576 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
577 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
578 _HSI, _HSE, _CSI, _I2S_CKIN),
Yann Gautier9aea69e2018-07-24 17:13:36 +0200579};
580
581/* Prescaler table lookups for clock computation */
Yann Gautiered342322019-02-15 17:33:27 +0100582/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
583static const uint8_t stm32mp1_mcu_div[16] = {
584 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
585};
Yann Gautier9aea69e2018-07-24 17:13:36 +0200586
587/* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */
588#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
589#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
590static const uint8_t stm32mp1_mpu_apbx_div[8] = {
591 0, 1, 2, 3, 4, 4, 4, 4
592};
593
594/* div = /1 /2 /3 /4 */
595static const uint8_t stm32mp1_axi_div[8] = {
596 1, 2, 3, 4, 4, 4, 4, 4
597};
598
Etienne Carriere1368ada2020-05-13 11:49:49 +0200599static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = {
600 [_HSI] = "HSI",
601 [_HSE] = "HSE",
602 [_CSI] = "CSI",
603 [_LSI] = "LSI",
604 [_LSE] = "LSE",
605 [_I2S_CKIN] = "I2S_CKIN",
606 [_HSI_KER] = "HSI_KER",
607 [_HSE_KER] = "HSE_KER",
608 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +0200609 [_HSE_RTC] = "HSE_RTC",
Etienne Carriere1368ada2020-05-13 11:49:49 +0200610 [_CSI_KER] = "CSI_KER",
611 [_PLL1_P] = "PLL1_P",
612 [_PLL1_Q] = "PLL1_Q",
613 [_PLL1_R] = "PLL1_R",
614 [_PLL2_P] = "PLL2_P",
615 [_PLL2_Q] = "PLL2_Q",
616 [_PLL2_R] = "PLL2_R",
617 [_PLL3_P] = "PLL3_P",
618 [_PLL3_Q] = "PLL3_Q",
619 [_PLL3_R] = "PLL3_R",
620 [_PLL4_P] = "PLL4_P",
621 [_PLL4_Q] = "PLL4_Q",
622 [_PLL4_R] = "PLL4_R",
623 [_ACLK] = "ACLK",
624 [_PCLK1] = "PCLK1",
625 [_PCLK2] = "PCLK2",
626 [_PCLK3] = "PCLK3",
627 [_PCLK4] = "PCLK4",
628 [_PCLK5] = "PCLK5",
629 [_HCLK6] = "KCLK6",
630 [_HCLK2] = "HCLK2",
631 [_CK_PER] = "CK_PER",
632 [_CK_MPU] = "CK_MPU",
633 [_CK_MCU] = "CK_MCU",
634 [_USB_PHY_48] = "USB_PHY_48",
635};
636
Yann Gautiere4a3c352019-02-14 10:53:33 +0100637/* RCC clock device driver private */
638static unsigned long stm32mp1_osc[NB_OSC];
639static struct spinlock reg_lock;
640static unsigned int gate_refcounts[NB_GATES];
641static struct spinlock refcount_lock;
642
643static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx)
644{
645 return &stm32mp1_clk_gate[idx];
646}
Yann Gautier9aea69e2018-07-24 17:13:36 +0200647
Yann Gautieraf1e8f42021-10-27 18:21:11 +0200648#if defined(IMAGE_BL32)
649static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate)
650{
651 return gate->secure == N_S;
652}
653#endif
654
Yann Gautiere4a3c352019-02-14 10:53:33 +0100655static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx)
656{
657 return &stm32mp1_clk_sel[idx];
658}
Yann Gautier9aea69e2018-07-24 17:13:36 +0200659
Yann Gautiere4a3c352019-02-14 10:53:33 +0100660static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx)
661{
662 return &stm32mp1_clk_pll[idx];
663}
664
Yann Gautiere4a3c352019-02-14 10:53:33 +0100665static void stm32mp1_clk_lock(struct spinlock *lock)
666{
Yann Gautierf540a592019-05-22 19:13:51 +0200667 if (stm32mp_lock_available()) {
668 /* Assume interrupts are masked */
669 spin_lock(lock);
Yann Gautiere4a3c352019-02-14 10:53:33 +0100670 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100671}
672
673static void stm32mp1_clk_unlock(struct spinlock *lock)
674{
Yann Gautierf540a592019-05-22 19:13:51 +0200675 if (stm32mp_lock_available()) {
676 spin_unlock(lock);
Yann Gautiere4a3c352019-02-14 10:53:33 +0100677 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100678}
679
680bool stm32mp1_rcc_is_secure(void)
681{
682 uintptr_t rcc_base = stm32mp_rcc_base();
Etienne Carriere5e68f6b2020-02-05 10:03:27 +0100683 uint32_t mask = RCC_TZCR_TZEN;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100684
Etienne Carriere5e68f6b2020-02-05 10:03:27 +0100685 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100686}
687
Yann Gautiered342322019-02-15 17:33:27 +0100688bool stm32mp1_rcc_is_mckprot(void)
689{
690 uintptr_t rcc_base = stm32mp_rcc_base();
Etienne Carriere5e68f6b2020-02-05 10:03:27 +0100691 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT;
Yann Gautiered342322019-02-15 17:33:27 +0100692
Etienne Carriere5e68f6b2020-02-05 10:03:27 +0100693 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
Yann Gautiered342322019-02-15 17:33:27 +0100694}
695
Yann Gautiere4a3c352019-02-14 10:53:33 +0100696void stm32mp1_clk_rcc_regs_lock(void)
697{
698 stm32mp1_clk_lock(&reg_lock);
699}
700
701void stm32mp1_clk_rcc_regs_unlock(void)
702{
703 stm32mp1_clk_unlock(&reg_lock);
704}
705
706static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200707{
708 if (idx >= NB_OSC) {
709 return 0;
710 }
711
Yann Gautiere4a3c352019-02-14 10:53:33 +0100712 return stm32mp1_osc[idx];
Yann Gautier9aea69e2018-07-24 17:13:36 +0200713}
714
Yann Gautiere4a3c352019-02-14 10:53:33 +0100715static int stm32mp1_clk_get_gated_id(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200716{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100717 unsigned int i;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200718
Yann Gautiere4a3c352019-02-14 10:53:33 +0100719 for (i = 0U; i < NB_GATES; i++) {
720 if (gate_ref(i)->index == id) {
Yann Gautier9aea69e2018-07-24 17:13:36 +0200721 return i;
722 }
723 }
724
Yann Gautierc9343812021-09-07 09:05:44 +0200725 ERROR("%s: clk id %lu not found\n", __func__, id);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200726
727 return -EINVAL;
728}
729
Yann Gautiere4a3c352019-02-14 10:53:33 +0100730static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200731{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100732 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200733}
734
Yann Gautiere4a3c352019-02-14 10:53:33 +0100735static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200736{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100737 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200738}
739
Yann Gautiere4a3c352019-02-14 10:53:33 +0100740static int stm32mp1_clk_get_parent(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200741{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100742 const struct stm32mp1_clk_sel *sel;
Etienne Carriere04132612019-12-08 08:20:12 +0100743 uint32_t p_sel;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200744 int i;
745 enum stm32mp1_parent_id p;
746 enum stm32mp1_parent_sel s;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100747 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200748
Etienne Carriere04132612019-12-08 08:20:12 +0100749 /* Few non gateable clock have a static parent ID, find them */
750 i = (int)clock_id2parent_id(id);
751 if (i != _UNKNOWN_ID) {
752 return i;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200753 }
754
Yann Gautiere4a3c352019-02-14 10:53:33 +0100755 i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200756 if (i < 0) {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100757 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200758 }
759
Yann Gautiere4a3c352019-02-14 10:53:33 +0100760 p = stm32mp1_clk_get_fixed_parent(i);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200761 if (p < _PARENT_NB) {
762 return (int)p;
763 }
764
Yann Gautiere4a3c352019-02-14 10:53:33 +0100765 s = stm32mp1_clk_get_sel(i);
766 if (s == _UNKNOWN_SEL) {
Yann Gautier9aea69e2018-07-24 17:13:36 +0200767 return -EINVAL;
768 }
Yann Gautiere4a3c352019-02-14 10:53:33 +0100769 if (s >= _PARENT_SEL_NB) {
770 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200771 }
772
Yann Gautiere4a3c352019-02-14 10:53:33 +0100773 sel = clk_sel_ref(s);
Etienne Carrierec164ce22019-12-08 08:20:40 +0100774 p_sel = (mmio_read_32(rcc_base + sel->offset) &
775 (sel->msk << sel->src)) >> sel->src;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100776 if (p_sel < sel->nb_parent) {
777 return (int)sel->parent[p_sel];
778 }
Yann Gautier9aea69e2018-07-24 17:13:36 +0200779
780 return -EINVAL;
781}
782
Yann Gautiere4a3c352019-02-14 10:53:33 +0100783static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200784{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100785 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr);
786 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200787
Yann Gautiere4a3c352019-02-14 10:53:33 +0100788 return stm32mp1_clk_get_fixed(pll->refclk[src]);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200789}
790
791/*
792 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
793 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
794 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
795 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
796 */
Yann Gautiere4a3c352019-02-14 10:53:33 +0100797static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200798{
Yann Gautier9aea69e2018-07-24 17:13:36 +0200799 unsigned long refclk, fvco;
800 uint32_t cfgr1, fracr, divm, divn;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100801 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200802
Yann Gautiere4a3c352019-02-14 10:53:33 +0100803 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);
804 fracr = mmio_read_32(rcc_base + pll->pllxfracr);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200805
806 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
807 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
808
Yann Gautiere4a3c352019-02-14 10:53:33 +0100809 refclk = stm32mp1_pll_get_fref(pll);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200810
811 /*
812 * With FRACV :
813 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
814 * Without FRACV
815 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
816 */
817 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +0100818 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
819 RCC_PLLNFRACR_FRACV_SHIFT;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200820 unsigned long long numerator, denominator;
821
Yann Gautiere4a3c352019-02-14 10:53:33 +0100822 numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
823 numerator = refclk * numerator;
824 denominator = ((unsigned long long)divm + 1U) << 13;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200825 fvco = (unsigned long)(numerator / denominator);
826 } else {
827 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U));
828 }
829
830 return fvco;
831}
832
Yann Gautiere4a3c352019-02-14 10:53:33 +0100833static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,
Yann Gautier9aea69e2018-07-24 17:13:36 +0200834 enum stm32mp1_div_id div_id)
835{
Yann Gautiere4a3c352019-02-14 10:53:33 +0100836 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200837 unsigned long dfout;
838 uint32_t cfgr2, divy;
839
840 if (div_id >= _DIV_NB) {
841 return 0;
842 }
843
Yann Gautiere4a3c352019-02-14 10:53:33 +0100844 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200845 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
846
Yann Gautiere4a3c352019-02-14 10:53:33 +0100847 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200848
849 return dfout;
850}
851
Yann Gautiere4a3c352019-02-14 10:53:33 +0100852static unsigned long get_clock_rate(int p)
Yann Gautier9aea69e2018-07-24 17:13:36 +0200853{
854 uint32_t reg, clkdiv;
855 unsigned long clock = 0;
Yann Gautiere4a3c352019-02-14 10:53:33 +0100856 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +0200857
858 switch (p) {
859 case _CK_MPU:
860 /* MPU sub system */
Yann Gautiere4a3c352019-02-14 10:53:33 +0100861 reg = mmio_read_32(rcc_base + RCC_MPCKSELR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200862 switch (reg & RCC_SELR_SRC_MASK) {
863 case RCC_MPCKSELR_HSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100864 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200865 break;
866 case RCC_MPCKSELR_HSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100867 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200868 break;
869 case RCC_MPCKSELR_PLL:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100870 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200871 break;
872 case RCC_MPCKSELR_PLL_MPUDIV:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100873 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200874
Yann Gautiere4a3c352019-02-14 10:53:33 +0100875 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200876 clkdiv = reg & RCC_MPUDIV_MASK;
Gabriel Fernandez4d198742020-02-28 09:09:06 +0100877 clock >>= stm32mp1_mpu_div[clkdiv];
Yann Gautier9aea69e2018-07-24 17:13:36 +0200878 break;
879 default:
880 break;
881 }
882 break;
883 /* AXI sub system */
884 case _ACLK:
885 case _HCLK2:
886 case _HCLK6:
887 case _PCLK4:
888 case _PCLK5:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100889 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200890 switch (reg & RCC_SELR_SRC_MASK) {
891 case RCC_ASSCKSELR_HSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100892 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200893 break;
894 case RCC_ASSCKSELR_HSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100895 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200896 break;
897 case RCC_ASSCKSELR_PLL:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100898 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200899 break;
900 default:
901 break;
902 }
903
904 /* System clock divider */
Yann Gautiere4a3c352019-02-14 10:53:33 +0100905 reg = mmio_read_32(rcc_base + RCC_AXIDIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200906 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
907
908 switch (p) {
909 case _PCLK4:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100910 reg = mmio_read_32(rcc_base + RCC_APB4DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200911 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
912 break;
913 case _PCLK5:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100914 reg = mmio_read_32(rcc_base + RCC_APB5DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200915 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
916 break;
917 default:
918 break;
919 }
920 break;
Yann Gautiered342322019-02-15 17:33:27 +0100921 /* MCU sub system */
922 case _CK_MCU:
923 case _PCLK1:
924 case _PCLK2:
925 case _PCLK3:
926 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR);
927 switch (reg & RCC_SELR_SRC_MASK) {
928 case RCC_MSSCKSELR_HSI:
929 clock = stm32mp1_clk_get_fixed(_HSI);
930 break;
931 case RCC_MSSCKSELR_HSE:
932 clock = stm32mp1_clk_get_fixed(_HSE);
933 break;
934 case RCC_MSSCKSELR_CSI:
935 clock = stm32mp1_clk_get_fixed(_CSI);
936 break;
937 case RCC_MSSCKSELR_PLL:
938 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
939 break;
940 default:
941 break;
942 }
943
944 /* MCU clock divider */
945 reg = mmio_read_32(rcc_base + RCC_MCUDIVR);
946 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
947
948 switch (p) {
949 case _PCLK1:
950 reg = mmio_read_32(rcc_base + RCC_APB1DIVR);
951 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
952 break;
953 case _PCLK2:
954 reg = mmio_read_32(rcc_base + RCC_APB2DIVR);
955 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
956 break;
957 case _PCLK3:
958 reg = mmio_read_32(rcc_base + RCC_APB3DIVR);
959 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
960 break;
961 case _CK_MCU:
962 default:
963 break;
964 }
965 break;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200966 case _CK_PER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100967 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200968 switch (reg & RCC_SELR_SRC_MASK) {
969 case RCC_CPERCKSELR_HSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100970 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200971 break;
972 case RCC_CPERCKSELR_HSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100973 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200974 break;
975 case RCC_CPERCKSELR_CSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100976 clock = stm32mp1_clk_get_fixed(_CSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200977 break;
978 default:
979 break;
980 }
981 break;
982 case _HSI:
983 case _HSI_KER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100984 clock = stm32mp1_clk_get_fixed(_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200985 break;
986 case _CSI:
987 case _CSI_KER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100988 clock = stm32mp1_clk_get_fixed(_CSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200989 break;
990 case _HSE:
991 case _HSE_KER:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100992 clock = stm32mp1_clk_get_fixed(_HSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +0200993 break;
994 case _HSE_KER_DIV2:
Yann Gautiere4a3c352019-02-14 10:53:33 +0100995 clock = stm32mp1_clk_get_fixed(_HSE) >> 1;
Yann Gautier9aea69e2018-07-24 17:13:36 +0200996 break;
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +0200997 case _HSE_RTC:
998 clock = stm32mp1_clk_get_fixed(_HSE);
999 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U;
1000 break;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001001 case _LSI:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001002 clock = stm32mp1_clk_get_fixed(_LSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001003 break;
1004 case _LSE:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001005 clock = stm32mp1_clk_get_fixed(_LSE);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001006 break;
1007 /* PLL */
1008 case _PLL1_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001009 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001010 break;
1011 case _PLL1_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001012 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001013 break;
1014 case _PLL1_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001015 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001016 break;
1017 case _PLL2_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001018 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001019 break;
1020 case _PLL2_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001021 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001022 break;
1023 case _PLL2_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001024 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001025 break;
1026 case _PLL3_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001027 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001028 break;
1029 case _PLL3_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001030 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001031 break;
1032 case _PLL3_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001033 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001034 break;
1035 case _PLL4_P:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001036 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001037 break;
1038 case _PLL4_Q:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001039 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001040 break;
1041 case _PLL4_R:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001042 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001043 break;
1044 /* Other */
1045 case _USB_PHY_48:
Yann Gautiere4a3c352019-02-14 10:53:33 +01001046 clock = USB_PHY_48_MHZ;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001047 break;
1048 default:
1049 break;
1050 }
1051
1052 return clock;
1053}
1054
Yann Gautiere4a3c352019-02-14 10:53:33 +01001055static void __clk_enable(struct stm32mp1_clk_gate const *gate)
1056{
1057 uintptr_t rcc_base = stm32mp_rcc_base();
1058
Etienne Carriere8a668892019-12-08 08:21:08 +01001059 VERBOSE("Enable clock %u\n", gate->index);
1060
Yann Gautiere4a3c352019-02-14 10:53:33 +01001061 if (gate->set_clr != 0U) {
1062 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));
1063 } else {
1064 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));
1065 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001066}
1067
1068static void __clk_disable(struct stm32mp1_clk_gate const *gate)
1069{
1070 uintptr_t rcc_base = stm32mp_rcc_base();
1071
Etienne Carriere8a668892019-12-08 08:21:08 +01001072 VERBOSE("Disable clock %u\n", gate->index);
1073
Yann Gautiere4a3c352019-02-14 10:53:33 +01001074 if (gate->set_clr != 0U) {
1075 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,
1076 BIT(gate->bit));
1077 } else {
1078 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));
1079 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001080}
1081
1082static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate)
1083{
1084 uintptr_t rcc_base = stm32mp_rcc_base();
1085
1086 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);
1087}
1088
Etienne Carriere481aa002019-12-08 08:21:44 +01001089/* Oscillators and PLLs are not gated at runtime */
1090static bool clock_is_always_on(unsigned long id)
1091{
1092 switch (id) {
1093 case CK_HSE:
1094 case CK_CSI:
1095 case CK_LSI:
1096 case CK_LSE:
1097 case CK_HSI:
1098 case CK_HSE_DIV2:
1099 case PLL1_Q:
1100 case PLL1_R:
1101 case PLL2_P:
1102 case PLL2_Q:
1103 case PLL2_R:
1104 case PLL3_P:
1105 case PLL3_Q:
1106 case PLL3_R:
Yann Gautierb39a1522020-09-16 16:41:55 +02001107 case CK_AXI:
1108 case CK_MPU:
1109 case CK_MCU:
HE Shushanc47c8162021-07-12 23:04:10 +02001110 case RTC:
Etienne Carriere481aa002019-12-08 08:21:44 +01001111 return true;
1112 default:
1113 return false;
1114 }
1115}
1116
Yann Gautierad730b52022-01-19 13:57:49 +01001117static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001118{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001119 const struct stm32mp1_clk_gate *gate;
Etienne Carriere481aa002019-12-08 08:21:44 +01001120 int i;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001121
Etienne Carriere481aa002019-12-08 08:21:44 +01001122 if (clock_is_always_on(id)) {
1123 return;
1124 }
1125
1126 i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001127 if (i < 0) {
Yann Gautierc9343812021-09-07 09:05:44 +02001128 ERROR("Clock %lu can't be enabled\n", id);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001129 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001130 }
1131
Yann Gautiere4a3c352019-02-14 10:53:33 +01001132 gate = gate_ref(i);
Yann Gautierad730b52022-01-19 13:57:49 +01001133
1134 if (!with_refcnt) {
1135 __clk_enable(gate);
1136 return;
1137 }
Yann Gautieraf1e8f42021-10-27 18:21:11 +02001138
1139#if defined(IMAGE_BL32)
1140 if (gate_is_non_secure(gate)) {
1141 /* Enable non-secure clock w/o any refcounting */
1142 __clk_enable(gate);
1143 return;
1144 }
1145#endif
Yann Gautiere4a3c352019-02-14 10:53:33 +01001146
1147 stm32mp1_clk_lock(&refcount_lock);
1148
Yann Gautierad730b52022-01-19 13:57:49 +01001149 if (gate_refcounts[i] == 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001150 __clk_enable(gate);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001151 }
1152
Yann Gautierad730b52022-01-19 13:57:49 +01001153 gate_refcounts[i]++;
1154 if (gate_refcounts[i] == UINT_MAX) {
1155 ERROR("Clock %lu refcount reached max value\n", id);
1156 panic();
1157 }
1158
Yann Gautiere4a3c352019-02-14 10:53:33 +01001159 stm32mp1_clk_unlock(&refcount_lock);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001160}
1161
Yann Gautierad730b52022-01-19 13:57:49 +01001162static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001163{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001164 const struct stm32mp1_clk_gate *gate;
Etienne Carriere481aa002019-12-08 08:21:44 +01001165 int i;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001166
Etienne Carriere481aa002019-12-08 08:21:44 +01001167 if (clock_is_always_on(id)) {
1168 return;
1169 }
1170
1171 i = stm32mp1_clk_get_gated_id(id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001172 if (i < 0) {
Yann Gautierc9343812021-09-07 09:05:44 +02001173 ERROR("Clock %lu can't be disabled\n", id);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001174 panic();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001175 }
1176
Yann Gautiere4a3c352019-02-14 10:53:33 +01001177 gate = gate_ref(i);
Yann Gautierad730b52022-01-19 13:57:49 +01001178
1179 if (!with_refcnt) {
1180 __clk_disable(gate);
1181 return;
1182 }
Yann Gautieraf1e8f42021-10-27 18:21:11 +02001183
1184#if defined(IMAGE_BL32)
1185 if (gate_is_non_secure(gate)) {
1186 /* Don't disable non-secure clocks */
1187 return;
1188 }
1189#endif
Yann Gautiere4a3c352019-02-14 10:53:33 +01001190
1191 stm32mp1_clk_lock(&refcount_lock);
1192
Yann Gautierad730b52022-01-19 13:57:49 +01001193 if (gate_refcounts[i] == 0U) {
1194 ERROR("Clock %lu refcount reached 0\n", id);
1195 panic();
1196 }
1197 gate_refcounts[i]--;
1198
1199 if (gate_refcounts[i] == 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001200 __clk_disable(gate);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001201 }
1202
Yann Gautiere4a3c352019-02-14 10:53:33 +01001203 stm32mp1_clk_unlock(&refcount_lock);
1204}
1205
Yann Gautiera205a5c2021-08-30 15:06:54 +02001206static int stm32mp_clk_enable(unsigned long id)
Yann Gautiere4a3c352019-02-14 10:53:33 +01001207{
1208 __stm32mp1_clk_enable(id, true);
Yann Gautiera205a5c2021-08-30 15:06:54 +02001209
1210 return 0;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001211}
1212
Yann Gautiera205a5c2021-08-30 15:06:54 +02001213static void stm32mp_clk_disable(unsigned long id)
Yann Gautiere4a3c352019-02-14 10:53:33 +01001214{
1215 __stm32mp1_clk_disable(id, true);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001216}
1217
Yann Gautiera205a5c2021-08-30 15:06:54 +02001218static bool stm32mp_clk_is_enabled(unsigned long id)
Yann Gautiere4a3c352019-02-14 10:53:33 +01001219{
Etienne Carriere481aa002019-12-08 08:21:44 +01001220 int i;
1221
1222 if (clock_is_always_on(id)) {
1223 return true;
1224 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001225
Etienne Carriere481aa002019-12-08 08:21:44 +01001226 i = stm32mp1_clk_get_gated_id(id);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001227 if (i < 0) {
1228 panic();
1229 }
1230
1231 return __clk_is_enabled(gate_ref(i));
1232}
1233
Yann Gautiera205a5c2021-08-30 15:06:54 +02001234static unsigned long stm32mp_clk_get_rate(unsigned long id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001235{
Yann Gautiera205a5c2021-08-30 15:06:54 +02001236 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautiere4a3c352019-02-14 10:53:33 +01001237 int p = stm32mp1_clk_get_parent(id);
Yann Gautiera205a5c2021-08-30 15:06:54 +02001238 uint32_t prescaler, timpre;
1239 unsigned long parent_rate;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001240
1241 if (p < 0) {
1242 return 0;
1243 }
1244
Yann Gautiera205a5c2021-08-30 15:06:54 +02001245 parent_rate = get_clock_rate(p);
1246
1247 switch (id) {
1248 case TIM2_K:
1249 case TIM3_K:
1250 case TIM4_K:
1251 case TIM5_K:
1252 case TIM6_K:
1253 case TIM7_K:
1254 case TIM12_K:
1255 case TIM13_K:
1256 case TIM14_K:
1257 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) &
1258 RCC_APBXDIV_MASK;
1259 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) &
1260 RCC_TIMGXPRER_TIMGXPRE;
1261 break;
1262
1263 case TIM1_K:
1264 case TIM8_K:
1265 case TIM15_K:
1266 case TIM16_K:
1267 case TIM17_K:
1268 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) &
1269 RCC_APBXDIV_MASK;
1270 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) &
1271 RCC_TIMGXPRER_TIMGXPRE;
1272 break;
1273
1274 default:
1275 return parent_rate;
1276 }
1277
1278 if (prescaler == 0U) {
1279 return parent_rate;
1280 }
1281
1282 return parent_rate * (timpre + 1U) * 2U;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001283}
1284
Yann Gautiere4a3c352019-02-14 10:53:33 +01001285static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001286{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001287 uintptr_t address = stm32mp_rcc_base() + offset;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001288
Yann Gautiere4a3c352019-02-14 10:53:33 +01001289 if (enable) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001290 mmio_setbits_32(address, mask_on);
1291 } else {
1292 mmio_clrbits_32(address, mask_on);
1293 }
1294}
1295
Yann Gautiere4a3c352019-02-14 10:53:33 +01001296static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001297{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001298 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR;
1299 uintptr_t address = stm32mp_rcc_base() + offset;
1300
1301 mmio_write_32(address, mask_on);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001302}
1303
Yann Gautiere4a3c352019-02-14 10:53:33 +01001304static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001305{
Yann Gautier2299d572019-02-14 11:14:39 +01001306 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001307 uint32_t mask_test;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001308 uintptr_t address = stm32mp_rcc_base() + offset;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001309
Yann Gautiere4a3c352019-02-14 10:53:33 +01001310 if (enable) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001311 mask_test = mask_rdy;
1312 } else {
1313 mask_test = 0;
1314 }
1315
Yann Gautier2299d572019-02-14 11:14:39 +01001316 timeout = timeout_init_us(OSCRDY_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001317 while ((mmio_read_32(address) & mask_rdy) != mask_test) {
Yann Gautier2299d572019-02-14 11:14:39 +01001318 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001319 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001320 mask_rdy, address, enable, mmio_read_32(address));
1321 return -ETIMEDOUT;
1322 }
1323 }
1324
1325 return 0;
1326}
1327
Yann Gautiere4a3c352019-02-14 10:53:33 +01001328static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001329{
1330 uint32_t value;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001331 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001332
Yann Gautiere4a3c352019-02-14 10:53:33 +01001333 if (digbyp) {
1334 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001335 }
1336
Yann Gautiere4a3c352019-02-14 10:53:33 +01001337 if (bypass || digbyp) {
1338 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);
1339 }
1340
Yann Gautier9aea69e2018-07-24 17:13:36 +02001341 /*
1342 * Warning: not recommended to switch directly from "high drive"
1343 * to "medium low drive", and vice-versa.
1344 */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001345 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>
Yann Gautier9aea69e2018-07-24 17:13:36 +02001346 RCC_BDCR_LSEDRV_SHIFT;
1347
1348 while (value != lsedrv) {
1349 if (value > lsedrv) {
1350 value--;
1351 } else {
1352 value++;
1353 }
1354
Yann Gautiere4a3c352019-02-14 10:53:33 +01001355 mmio_clrsetbits_32(rcc_base + RCC_BDCR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001356 RCC_BDCR_LSEDRV_MASK,
1357 value << RCC_BDCR_LSEDRV_SHIFT);
1358 }
1359
Yann Gautiere4a3c352019-02-14 10:53:33 +01001360 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001361}
1362
Yann Gautiere4a3c352019-02-14 10:53:33 +01001363static void stm32mp1_lse_wait(void)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001364{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001365 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001366 VERBOSE("%s: failed\n", __func__);
1367 }
1368}
1369
Yann Gautiere4a3c352019-02-14 10:53:33 +01001370static void stm32mp1_lsi_set(bool enable)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001371{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001372 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION);
1373
1374 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001375 VERBOSE("%s: failed\n", __func__);
1376 }
1377}
1378
Yann Gautiere4a3c352019-02-14 10:53:33 +01001379static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001380{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001381 uintptr_t rcc_base = stm32mp_rcc_base();
1382
1383 if (digbyp) {
1384 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001385 }
1386
Yann Gautiere4a3c352019-02-14 10:53:33 +01001387 if (bypass || digbyp) {
1388 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1389 }
1390
1391 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON);
1392 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001393 VERBOSE("%s: failed\n", __func__);
1394 }
1395
1396 if (css) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001397 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001398 }
Lionel Debieved78bd852019-07-02 18:03:34 +02001399
1400#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
1401 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) &&
1402 (!(digbyp || bypass))) {
1403 panic();
1404 }
1405#endif
Yann Gautier9aea69e2018-07-24 17:13:36 +02001406}
1407
Yann Gautiere4a3c352019-02-14 10:53:33 +01001408static void stm32mp1_csi_set(bool enable)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001409{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001410 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION);
1411 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001412 VERBOSE("%s: failed\n", __func__);
1413 }
1414}
1415
Yann Gautiere4a3c352019-02-14 10:53:33 +01001416static void stm32mp1_hsi_set(bool enable)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001417{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001418 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION);
1419 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001420 VERBOSE("%s: failed\n", __func__);
1421 }
1422}
1423
Yann Gautiere4a3c352019-02-14 10:53:33 +01001424static int stm32mp1_set_hsidiv(uint8_t hsidiv)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001425{
Yann Gautier2299d572019-02-14 11:14:39 +01001426 uint64_t timeout;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001427 uintptr_t rcc_base = stm32mp_rcc_base();
1428 uintptr_t address = rcc_base + RCC_OCRDYR;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001429
Yann Gautiere4a3c352019-02-14 10:53:33 +01001430 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001431 RCC_HSICFGR_HSIDIV_MASK,
1432 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
1433
Yann Gautier2299d572019-02-14 11:14:39 +01001434 timeout = timeout_init_us(HSIDIV_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001435 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001436 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001437 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001438 address, mmio_read_32(address));
1439 return -ETIMEDOUT;
1440 }
1441 }
1442
1443 return 0;
1444}
1445
Yann Gautiere4a3c352019-02-14 10:53:33 +01001446static int stm32mp1_hsidiv(unsigned long hsifreq)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001447{
1448 uint8_t hsidiv;
1449 uint32_t hsidivfreq = MAX_HSI_HZ;
1450
1451 for (hsidiv = 0; hsidiv < 4U; hsidiv++) {
1452 if (hsidivfreq == hsifreq) {
1453 break;
1454 }
1455
1456 hsidivfreq /= 2U;
1457 }
1458
1459 if (hsidiv == 4U) {
1460 ERROR("Invalid clk-hsi frequency\n");
1461 return -1;
1462 }
1463
1464 if (hsidiv != 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001465 return stm32mp1_set_hsidiv(hsidiv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001466 }
1467
1468 return 0;
1469}
1470
Yann Gautiere4a3c352019-02-14 10:53:33 +01001471static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,
1472 unsigned int clksrc,
1473 uint32_t *pllcfg, int plloff)
1474{
1475 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1476 uintptr_t rcc_base = stm32mp_rcc_base();
1477 uintptr_t pllxcr = rcc_base + pll->pllxcr;
1478 enum stm32mp1_plltype type = pll->plltype;
1479 uintptr_t clksrc_address = rcc_base + (clksrc >> 4);
1480 unsigned long refclk;
1481 uint32_t ifrge = 0U;
Andre Przywara2d5690c2020-03-26 11:50:33 +00001482 uint32_t src, value, fracv = 0;
1483 void *fdt;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001484
1485 /* Check PLL output */
1486 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) {
1487 return false;
1488 }
1489
1490 /* Check current clksrc */
1491 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK;
1492 if (src != (clksrc & RCC_SELR_SRC_MASK)) {
1493 return false;
1494 }
1495
1496 /* Check Div */
1497 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;
1498
1499 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
1500 (pllcfg[PLLCFG_M] + 1U);
1501
1502 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1503 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1504 return false;
1505 }
1506
1507 if ((type == PLL_800) && (refclk >= 8000000U)) {
1508 ifrge = 1U;
1509 }
1510
1511 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1512 RCC_PLLNCFGR1_DIVN_MASK;
1513 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1514 RCC_PLLNCFGR1_DIVM_MASK;
1515 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1516 RCC_PLLNCFGR1_IFRGE_MASK;
1517 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {
1518 return false;
1519 }
1520
1521 /* Fractional configuration */
Andre Przywara2d5690c2020-03-26 11:50:33 +00001522 if (fdt_get_address(&fdt) == 1) {
1523 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
1524 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001525
1526 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1527 value |= RCC_PLLNFRACR_FRACLE;
1528 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {
1529 return false;
1530 }
1531
1532 /* Output config */
1533 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1534 RCC_PLLNCFGR2_DIVP_MASK;
1535 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1536 RCC_PLLNCFGR2_DIVQ_MASK;
1537 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1538 RCC_PLLNCFGR2_DIVR_MASK;
1539 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {
1540 return false;
1541 }
1542
1543 return true;
1544}
1545
1546static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001547{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001548 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1549 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001550
Yann Gautierd0dcbaa2019-06-04 15:55:37 +02001551 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1552 mmio_clrsetbits_32(pllxcr,
1553 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1554 RCC_PLLNCR_DIVREN,
1555 RCC_PLLNCR_PLLON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001556}
1557
Yann Gautiere4a3c352019-02-14 10:53:33 +01001558static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001559{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001560 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1561 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
Yann Gautier2299d572019-02-14 11:14:39 +01001562 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001563
Yann Gautier9aea69e2018-07-24 17:13:36 +02001564 /* Wait PLL lock */
1565 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001566 if (timeout_elapsed(timeout)) {
Yann Gautier4ce04cc2022-02-28 11:34:05 +01001567 ERROR("PLL%u start failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001568 pll_id, pllxcr, mmio_read_32(pllxcr));
1569 return -ETIMEDOUT;
1570 }
1571 }
1572
1573 /* Start the requested output */
1574 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1575
1576 return 0;
1577}
1578
Yann Gautiere4a3c352019-02-14 10:53:33 +01001579static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001580{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001581 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1582 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
Yann Gautier2299d572019-02-14 11:14:39 +01001583 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001584
1585 /* Stop all output */
1586 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1587 RCC_PLLNCR_DIVREN);
1588
1589 /* Stop PLL */
1590 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON);
1591
Yann Gautier2299d572019-02-14 11:14:39 +01001592 timeout = timeout_init_us(PLLRDY_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001593 /* Wait PLL stopped */
1594 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001595 if (timeout_elapsed(timeout)) {
Yann Gautier4ce04cc2022-02-28 11:34:05 +01001596 ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001597 pll_id, pllxcr, mmio_read_32(pllxcr));
1598 return -ETIMEDOUT;
1599 }
1600 }
1601
1602 return 0;
1603}
1604
Yann Gautiere4a3c352019-02-14 10:53:33 +01001605static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001606 uint32_t *pllcfg)
1607{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001608 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1609 uintptr_t rcc_base = stm32mp_rcc_base();
Yann Gautier9aea69e2018-07-24 17:13:36 +02001610 uint32_t value;
1611
1612 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1613 RCC_PLLNCFGR2_DIVP_MASK;
1614 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1615 RCC_PLLNCFGR2_DIVQ_MASK;
1616 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1617 RCC_PLLNCFGR2_DIVR_MASK;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001618 mmio_write_32(rcc_base + pll->pllxcfgr2, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001619}
1620
Yann Gautiere4a3c352019-02-14 10:53:33 +01001621static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001622 uint32_t *pllcfg, uint32_t fracv)
1623{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001624 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1625 uintptr_t rcc_base = stm32mp_rcc_base();
1626 enum stm32mp1_plltype type = pll->plltype;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001627 unsigned long refclk;
1628 uint32_t ifrge = 0;
1629 uint32_t src, value;
1630
Yann Gautiere4a3c352019-02-14 10:53:33 +01001631 src = mmio_read_32(rcc_base + pll->rckxselr) &
Yann Gautier9aea69e2018-07-24 17:13:36 +02001632 RCC_SELR_REFCLK_SRC_MASK;
1633
Yann Gautiere4a3c352019-02-14 10:53:33 +01001634 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
Yann Gautier9aea69e2018-07-24 17:13:36 +02001635 (pllcfg[PLLCFG_M] + 1U);
1636
1637 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1638 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1639 return -EINVAL;
1640 }
1641
1642 if ((type == PLL_800) && (refclk >= 8000000U)) {
1643 ifrge = 1U;
1644 }
1645
1646 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1647 RCC_PLLNCFGR1_DIVN_MASK;
1648 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1649 RCC_PLLNCFGR1_DIVM_MASK;
1650 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1651 RCC_PLLNCFGR1_IFRGE_MASK;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001652 mmio_write_32(rcc_base + pll->pllxcfgr1, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001653
1654 /* Fractional configuration */
1655 value = 0;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001656 mmio_write_32(rcc_base + pll->pllxfracr, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001657
1658 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001659 mmio_write_32(rcc_base + pll->pllxfracr, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001660
1661 value |= RCC_PLLNFRACR_FRACLE;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001662 mmio_write_32(rcc_base + pll->pllxfracr, value);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001663
Yann Gautiere4a3c352019-02-14 10:53:33 +01001664 stm32mp1_pll_config_output(pll_id, pllcfg);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001665
1666 return 0;
1667}
1668
Yann Gautiere4a3c352019-02-14 10:53:33 +01001669static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001670{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001671 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001672 uint32_t pllxcsg = 0;
1673
1674 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1675 RCC_PLLNCSGR_MOD_PER_MASK;
1676
1677 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1678 RCC_PLLNCSGR_INC_STEP_MASK;
1679
1680 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1681 RCC_PLLNCSGR_SSCG_MODE_MASK;
1682
Yann Gautiere4a3c352019-02-14 10:53:33 +01001683 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg);
Yann Gautierd0dcbaa2019-06-04 15:55:37 +02001684
1685 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr,
1686 RCC_PLLNCR_SSCG_CTRL);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001687}
1688
Yann Gautiere4a3c352019-02-14 10:53:33 +01001689static int stm32mp1_set_clksrc(unsigned int clksrc)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001690{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001691 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
Yann Gautier2299d572019-02-14 11:14:39 +01001692 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001693
Yann Gautiere4a3c352019-02-14 10:53:33 +01001694 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001695 clksrc & RCC_SELR_SRC_MASK);
1696
Yann Gautier2299d572019-02-14 11:14:39 +01001697 timeout = timeout_init_us(CLKSRC_TIMEOUT);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001698 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001699 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001700 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc,
1701 clksrc_address, mmio_read_32(clksrc_address));
Yann Gautier9aea69e2018-07-24 17:13:36 +02001702 return -ETIMEDOUT;
1703 }
1704 }
1705
1706 return 0;
1707}
1708
Yann Gautiere4a3c352019-02-14 10:53:33 +01001709static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001710{
Yann Gautier2299d572019-02-14 11:14:39 +01001711 uint64_t timeout;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001712
1713 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK,
1714 clkdiv & RCC_DIVR_DIV_MASK);
1715
Yann Gautier2299d572019-02-14 11:14:39 +01001716 timeout = timeout_init_us(CLKDIV_TIMEOUT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001717 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) {
Yann Gautier2299d572019-02-14 11:14:39 +01001718 if (timeout_elapsed(timeout)) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001719 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001720 clkdiv, address, mmio_read_32(address));
1721 return -ETIMEDOUT;
1722 }
1723 }
1724
1725 return 0;
1726}
1727
Yann Gautiere4a3c352019-02-14 10:53:33 +01001728static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001729{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001730 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001731
1732 /*
1733 * Binding clksrc :
1734 * bit15-4 offset
1735 * bit3: disable
1736 * bit2-0: MCOSEL[2:0]
1737 */
1738 if ((clksrc & 0x8U) != 0U) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001739 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001740 } else {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001741 mmio_clrsetbits_32(clksrc_address,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001742 RCC_MCOCFG_MCOSRC_MASK,
1743 clksrc & RCC_MCOCFG_MCOSRC_MASK);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001744 mmio_clrsetbits_32(clksrc_address,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001745 RCC_MCOCFG_MCODIV_MASK,
1746 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001747 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001748 }
1749}
1750
Yann Gautiere4a3c352019-02-14 10:53:33 +01001751static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001752{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001753 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001754
1755 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) ||
1756 (clksrc != (uint32_t)CLK_RTC_DISABLED)) {
1757 mmio_clrsetbits_32(address,
1758 RCC_BDCR_RTCSRC_MASK,
Yann Gautier74aa83a2021-04-06 13:41:19 +02001759 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001760
1761 mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
1762 }
1763
1764 if (lse_css) {
1765 mmio_setbits_32(address, RCC_BDCR_LSECSSON);
1766 }
1767}
1768
Yann Gautiere4a3c352019-02-14 10:53:33 +01001769static void stm32mp1_pkcs_config(uint32_t pkcs)
Yann Gautier9aea69e2018-07-24 17:13:36 +02001770{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001771 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001772 uint32_t value = pkcs & 0xFU;
1773 uint32_t mask = 0xFU;
1774
1775 if ((pkcs & BIT(31)) != 0U) {
1776 mask <<= 4;
1777 value <<= 4;
1778 }
1779
1780 mmio_clrsetbits_32(address, mask, value);
1781}
1782
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01001783static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg,
1784 uint32_t *fracv, uint32_t *csg,
1785 bool *csg_set)
1786{
1787 void *fdt;
1788 int ret;
1789
1790 if (fdt_get_address(&fdt) == 0) {
1791 return -FDT_ERR_NOTFOUND;
1792 }
1793
1794 ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB,
1795 pllcfg);
1796 if (ret < 0) {
1797 return -FDT_ERR_NOTFOUND;
1798 }
1799
1800 *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
1801
1802 ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB,
1803 csg);
1804
1805 *csg_set = (ret == 0);
1806
1807 if (ret == -FDT_ERR_NOTFOUND) {
1808 ret = 0;
1809 }
1810
1811 return ret;
1812}
1813
Yann Gautier9aea69e2018-07-24 17:13:36 +02001814int stm32mp1_clk_init(void)
1815{
Yann Gautiere4a3c352019-02-14 10:53:33 +01001816 uintptr_t rcc_base = stm32mp_rcc_base();
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01001817 uint32_t pllfracv[_PLL_NB];
1818 uint32_t pllcsg[_PLL_NB][PLLCSG_NB];
Yann Gautier9aea69e2018-07-24 17:13:36 +02001819 unsigned int clksrc[CLKSRC_NB];
1820 unsigned int clkdiv[CLKDIV_NB];
1821 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1822 int plloff[_PLL_NB];
1823 int ret, len;
1824 enum stm32mp1_pll_id i;
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01001825 bool pllcsg_set[_PLL_NB];
1826 bool pllcfg_valid[_PLL_NB];
Yann Gautier9aea69e2018-07-24 17:13:36 +02001827 bool lse_css = false;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001828 bool pll3_preserve = false;
1829 bool pll4_preserve = false;
1830 bool pll4_bootrom = false;
Yann Gautierf9af3bc2018-11-09 15:57:18 +01001831 const fdt32_t *pkcs_cell;
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001832 void *fdt;
Patrick Delaunay64e1b2c2020-09-04 17:39:12 +02001833 int stgen_p = stm32mp1_clk_get_parent(STGEN_K);
1834 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K);
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001835
1836 if (fdt_get_address(&fdt) == 0) {
Yann Gautier360e0e92020-09-16 16:40:34 +02001837 return -FDT_ERR_NOTFOUND;
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001838 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001839
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001840 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB,
1841 clksrc);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001842 if (ret < 0) {
1843 return -FDT_ERR_NOTFOUND;
1844 }
1845
Andre Przywaracc99f3f2020-03-26 12:51:21 +00001846 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB,
1847 clkdiv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001848 if (ret < 0) {
1849 return -FDT_ERR_NOTFOUND;
1850 }
1851
1852 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1853 char name[12];
1854
Yann Gautier4ce04cc2022-02-28 11:34:05 +01001855 snprintf(name, sizeof(name), "st,pll@%u", i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001856 plloff[i] = fdt_rcc_subnode_offset(name);
1857
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01001858 pllcfg_valid[i] = fdt_check_node(plloff[i]);
1859 if (!pllcfg_valid[i]) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001860 continue;
1861 }
1862
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01001863 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i],
1864 &pllfracv[i], pllcsg[i],
1865 &pllcsg_set[i]);
1866 if (ret != 0) {
1867 return ret;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001868 }
1869 }
1870
Yann Gautiere4a3c352019-02-14 10:53:33 +01001871 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1872 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001873
1874 /*
1875 * Switch ON oscillator found in device-tree.
1876 * Note: HSI already ON after BootROM stage.
1877 */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001878 if (stm32mp1_osc[_LSI] != 0U) {
1879 stm32mp1_lsi_set(true);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001880 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001881 if (stm32mp1_osc[_LSE] != 0U) {
Gabriel Fernandez5177ea22020-05-15 08:00:03 +02001882 const char *name = stm32mp_osc_node_label[_LSE];
Yann Gautiere4a3c352019-02-14 10:53:33 +01001883 bool bypass, digbyp;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001884 uint32_t lsedrv;
1885
Gabriel Fernandez5177ea22020-05-15 08:00:03 +02001886 bypass = fdt_clk_read_bool(name, "st,bypass");
1887 digbyp = fdt_clk_read_bool(name, "st,digbypass");
1888 lse_css = fdt_clk_read_bool(name, "st,css");
1889 lsedrv = fdt_clk_read_uint32_default(name, "st,drive",
Yann Gautier9aea69e2018-07-24 17:13:36 +02001890 LSEDRV_MEDIUM_HIGH);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001891 stm32mp1_lse_enable(bypass, digbyp, lsedrv);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001892 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001893 if (stm32mp1_osc[_HSE] != 0U) {
Gabriel Fernandez5177ea22020-05-15 08:00:03 +02001894 const char *name = stm32mp_osc_node_label[_HSE];
Yann Gautiere4a3c352019-02-14 10:53:33 +01001895 bool bypass, digbyp, css;
Yann Gautier9aea69e2018-07-24 17:13:36 +02001896
Gabriel Fernandez5177ea22020-05-15 08:00:03 +02001897 bypass = fdt_clk_read_bool(name, "st,bypass");
1898 digbyp = fdt_clk_read_bool(name, "st,digbypass");
1899 css = fdt_clk_read_bool(name, "st,css");
Yann Gautiere4a3c352019-02-14 10:53:33 +01001900 stm32mp1_hse_enable(bypass, digbyp, css);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001901 }
1902 /*
1903 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1904 * => switch on CSI even if node is not present in device tree
1905 */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001906 stm32mp1_csi_set(true);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001907
1908 /* Come back to HSI */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001909 ret = stm32mp1_set_clksrc(CLK_MPU_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001910 if (ret != 0) {
1911 return ret;
1912 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001913 ret = stm32mp1_set_clksrc(CLK_AXI_HSI);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001914 if (ret != 0) {
1915 return ret;
1916 }
Yann Gautiered342322019-02-15 17:33:27 +01001917 ret = stm32mp1_set_clksrc(CLK_MCU_HSI);
1918 if (ret != 0) {
1919 return ret;
1920 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02001921
Yann Gautiere4a3c352019-02-14 10:53:33 +01001922 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &
1923 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) {
Yann Gautierfffc76e2022-03-04 11:08:47 +01001924 if (pllcfg_valid[_PLL3]) {
1925 pll3_preserve =
1926 stm32mp1_check_pll_conf(_PLL3,
Yann Gautiere4a3c352019-02-14 10:53:33 +01001927 clksrc[CLKSRC_PLL3],
1928 pllcfg[_PLL3],
1929 plloff[_PLL3]);
Yann Gautierfffc76e2022-03-04 11:08:47 +01001930 }
1931
1932 if (pllcfg_valid[_PLL4]) {
1933 pll4_preserve =
1934 stm32mp1_check_pll_conf(_PLL4,
Yann Gautiere4a3c352019-02-14 10:53:33 +01001935 clksrc[CLKSRC_PLL4],
1936 pllcfg[_PLL4],
1937 plloff[_PLL4]);
Yann Gautierfffc76e2022-03-04 11:08:47 +01001938 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001939 }
Patrick Delaunay64e1b2c2020-09-04 17:39:12 +02001940 /* Don't initialize PLL4, when used by BOOTROM */
1941 if ((stm32mp_get_boot_itf_selected() ==
1942 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) &&
1943 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) {
1944 pll4_bootrom = true;
1945 pll4_preserve = true;
1946 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001947
Yann Gautier9aea69e2018-07-24 17:13:36 +02001948 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01001949 if (((i == _PLL3) && pll3_preserve) ||
1950 ((i == _PLL4) && pll4_preserve)) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02001951 continue;
Yann Gautiere4a3c352019-02-14 10:53:33 +01001952 }
1953
1954 ret = stm32mp1_pll_stop(i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001955 if (ret != 0) {
1956 return ret;
1957 }
1958 }
1959
1960 /* Configure HSIDIV */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001961 if (stm32mp1_osc[_HSI] != 0U) {
1962 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001963 if (ret != 0) {
1964 return ret;
1965 }
Lionel Debievedeef9692019-12-04 21:50:19 +01001966
1967 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K));
Yann Gautier9aea69e2018-07-24 17:13:36 +02001968 }
1969
1970 /* Select DIV */
1971 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
Yann Gautiere4a3c352019-02-14 10:53:33 +01001972 mmio_write_32(rcc_base + RCC_MPCKDIVR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02001973 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK);
Yann Gautiere4a3c352019-02-14 10:53:33 +01001974 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001975 if (ret != 0) {
1976 return ret;
1977 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001978 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001979 if (ret != 0) {
1980 return ret;
1981 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001982 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001983 if (ret != 0) {
1984 return ret;
1985 }
Yann Gautiered342322019-02-15 17:33:27 +01001986 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);
1987 if (ret != 0) {
1988 return ret;
1989 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001990 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001991 if (ret != 0) {
1992 return ret;
1993 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001994 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001995 if (ret != 0) {
1996 return ret;
1997 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01001998 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);
Yann Gautier9aea69e2018-07-24 17:13:36 +02001999 if (ret != 0) {
2000 return ret;
2001 }
2002
2003 /* No ready bit for RTC */
Yann Gautiere4a3c352019-02-14 10:53:33 +01002004 mmio_write_32(rcc_base + RCC_RTCDIVR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02002005 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK);
2006
2007 /* Configure PLLs source */
Yann Gautiere4a3c352019-02-14 10:53:33 +01002008 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002009 if (ret != 0) {
2010 return ret;
2011 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01002012
2013 if (!pll3_preserve) {
2014 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]);
2015 if (ret != 0) {
2016 return ret;
2017 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02002018 }
2019
Yann Gautiere4a3c352019-02-14 10:53:33 +01002020 if (!pll4_preserve) {
2021 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]);
2022 if (ret != 0) {
2023 return ret;
2024 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02002025 }
2026
2027 /* Configure and start PLLs */
2028 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01002029 if (((i == _PLL3) && pll3_preserve) ||
2030 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) {
2031 continue;
2032 }
2033
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01002034 if (!pllcfg_valid[i]) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02002035 continue;
2036 }
2037
Yann Gautiere4a3c352019-02-14 10:53:33 +01002038 if ((i == _PLL4) && pll4_bootrom) {
2039 /* Set output divider if not done by the Bootrom */
2040 stm32mp1_pll_config_output(i, pllcfg[i]);
2041 continue;
2042 }
2043
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01002044 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002045 if (ret != 0) {
2046 return ret;
2047 }
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01002048
2049 if (pllcsg_set[i]) {
2050 stm32mp1_pll_csg(i, pllcsg[i]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002051 }
2052
Yann Gautiere4a3c352019-02-14 10:53:33 +01002053 stm32mp1_pll_start(i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002054 }
2055 /* Wait and start PLLs ouptut when ready */
2056 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
Nicolas Le Bayondab197a2019-11-13 11:46:31 +01002057 if (!pllcfg_valid[i]) {
Yann Gautier9aea69e2018-07-24 17:13:36 +02002058 continue;
2059 }
2060
Yann Gautiere4a3c352019-02-14 10:53:33 +01002061 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002062 if (ret != 0) {
2063 return ret;
2064 }
2065 }
2066 /* Wait LSE ready before to use it */
Yann Gautiere4a3c352019-02-14 10:53:33 +01002067 if (stm32mp1_osc[_LSE] != 0U) {
2068 stm32mp1_lse_wait();
Yann Gautier9aea69e2018-07-24 17:13:36 +02002069 }
2070
2071 /* Configure with expected clock source */
Yann Gautiere4a3c352019-02-14 10:53:33 +01002072 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002073 if (ret != 0) {
2074 return ret;
2075 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01002076 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002077 if (ret != 0) {
2078 return ret;
2079 }
Yann Gautiered342322019-02-15 17:33:27 +01002080 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]);
2081 if (ret != 0) {
2082 return ret;
2083 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01002084 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002085
2086 /* Configure PKCK */
2087 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len);
2088 if (pkcs_cell != NULL) {
2089 bool ckper_disabled = false;
2090 uint32_t j;
Patrick Delaunay64e1b2c2020-09-04 17:39:12 +02002091 uint32_t usbreg_bootrom = 0U;
2092
2093 if (pll4_bootrom) {
2094 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR);
2095 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02002096
Yann Gautier9aea69e2018-07-24 17:13:36 +02002097 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) {
Yann Gautierf9af3bc2018-11-09 15:57:18 +01002098 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002099
2100 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) {
2101 ckper_disabled = true;
2102 continue;
2103 }
Yann Gautiere4a3c352019-02-14 10:53:33 +01002104 stm32mp1_pkcs_config(pkcs);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002105 }
2106
2107 /*
2108 * CKPER is source for some peripheral clocks
2109 * (FMC-NAND / QPSI-NOR) and switching source is allowed
2110 * only if previous clock is still ON
2111 * => deactivated CKPER only after switching clock
2112 */
2113 if (ckper_disabled) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01002114 stm32mp1_pkcs_config(CLK_CKPER_DISABLED);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002115 }
Patrick Delaunay64e1b2c2020-09-04 17:39:12 +02002116
2117 if (pll4_bootrom) {
2118 uint32_t usbreg_value, usbreg_mask;
2119 const struct stm32mp1_clk_sel *sel;
2120
2121 sel = clk_sel_ref(_USBPHY_SEL);
2122 usbreg_mask = (uint32_t)sel->msk << sel->src;
2123 sel = clk_sel_ref(_USBO_SEL);
2124 usbreg_mask |= (uint32_t)sel->msk << sel->src;
2125
2126 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) &
2127 usbreg_mask;
2128 usbreg_bootrom &= usbreg_mask;
2129 if (usbreg_bootrom != usbreg_value) {
2130 VERBOSE("forbidden new USB clk path\n");
2131 VERBOSE("vs bootrom on USB boot\n");
2132 return -FDT_ERR_BADVALUE;
2133 }
2134 }
Yann Gautier9aea69e2018-07-24 17:13:36 +02002135 }
2136
2137 /* Switch OFF HSI if not found in device-tree */
Yann Gautiere4a3c352019-02-14 10:53:33 +01002138 if (stm32mp1_osc[_HSI] == 0U) {
2139 stm32mp1_hsi_set(false);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002140 }
Lionel Debievedeef9692019-12-04 21:50:19 +01002141
2142 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K));
Yann Gautier9aea69e2018-07-24 17:13:36 +02002143
2144 /* Software Self-Refresh mode (SSR) during DDR initilialization */
Yann Gautiere4a3c352019-02-14 10:53:33 +01002145 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,
Yann Gautier9aea69e2018-07-24 17:13:36 +02002146 RCC_DDRITFCR_DDRCKMOD_MASK,
2147 RCC_DDRITFCR_DDRCKMOD_SSR <<
2148 RCC_DDRITFCR_DDRCKMOD_SHIFT);
2149
2150 return 0;
2151}
2152
2153static void stm32mp1_osc_clk_init(const char *name,
Yann Gautier9aea69e2018-07-24 17:13:36 +02002154 enum stm32mp_osc_id index)
2155{
2156 uint32_t frequency;
2157
Yann Gautiere4a3c352019-02-14 10:53:33 +01002158 if (fdt_osc_read_freq(name, &frequency) == 0) {
2159 stm32mp1_osc[index] = frequency;
Yann Gautier9aea69e2018-07-24 17:13:36 +02002160 }
2161}
2162
2163static void stm32mp1_osc_init(void)
2164{
Yann Gautier9aea69e2018-07-24 17:13:36 +02002165 enum stm32mp_osc_id i;
2166
2167 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) {
Yann Gautiere4a3c352019-02-14 10:53:33 +01002168 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i);
Yann Gautier9aea69e2018-07-24 17:13:36 +02002169 }
2170}
Etienne Carriere1368ada2020-05-13 11:49:49 +02002171
2172#ifdef STM32MP_SHARED_RESOURCES
2173/*
2174 * Get the parent ID of the target parent clock, for tagging as secure
2175 * shared clock dependencies.
2176 */
2177static int get_parent_id_parent(unsigned int parent_id)
2178{
2179 enum stm32mp1_parent_sel s = _UNKNOWN_SEL;
2180 enum stm32mp1_pll_id pll_id;
2181 uint32_t p_sel;
2182 uintptr_t rcc_base = stm32mp_rcc_base();
2183
2184 switch (parent_id) {
2185 case _ACLK:
2186 case _PCLK4:
2187 case _PCLK5:
2188 s = _AXIS_SEL;
2189 break;
2190 case _PLL1_P:
2191 case _PLL1_Q:
2192 case _PLL1_R:
2193 pll_id = _PLL1;
2194 break;
2195 case _PLL2_P:
2196 case _PLL2_Q:
2197 case _PLL2_R:
2198 pll_id = _PLL2;
2199 break;
2200 case _PLL3_P:
2201 case _PLL3_Q:
2202 case _PLL3_R:
2203 pll_id = _PLL3;
2204 break;
2205 case _PLL4_P:
2206 case _PLL4_Q:
2207 case _PLL4_R:
2208 pll_id = _PLL4;
2209 break;
2210 case _PCLK1:
2211 case _PCLK2:
2212 case _HCLK2:
2213 case _HCLK6:
2214 case _CK_PER:
2215 case _CK_MPU:
2216 case _CK_MCU:
2217 case _USB_PHY_48:
2218 /* We do not expect to access these */
2219 panic();
2220 break;
2221 default:
2222 /* Other parents have no parent */
2223 return -1;
2224 }
2225
2226 if (s != _UNKNOWN_SEL) {
2227 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s);
2228
2229 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &
2230 sel->msk;
2231
2232 if (p_sel < sel->nb_parent) {
2233 return (int)sel->parent[p_sel];
2234 }
2235 } else {
2236 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
2237
2238 p_sel = mmio_read_32(rcc_base + pll->rckxselr) &
2239 RCC_SELR_REFCLK_SRC_MASK;
2240
2241 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) {
2242 return (int)pll->refclk[p_sel];
2243 }
2244 }
2245
2246 VERBOSE("No parent selected for %s\n",
2247 stm32mp1_clk_parent_name[parent_id]);
2248
2249 return -1;
2250}
2251
2252static void secure_parent_clocks(unsigned long parent_id)
2253{
2254 int grandparent_id;
2255
2256 switch (parent_id) {
2257 case _PLL3_P:
2258 case _PLL3_Q:
2259 case _PLL3_R:
2260 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
2261 break;
2262
2263 /* These clocks are always secure when RCC is secure */
2264 case _ACLK:
2265 case _HCLK2:
2266 case _HCLK6:
2267 case _PCLK4:
2268 case _PCLK5:
2269 case _PLL1_P:
2270 case _PLL1_Q:
2271 case _PLL1_R:
2272 case _PLL2_P:
2273 case _PLL2_Q:
2274 case _PLL2_R:
2275 case _HSI:
2276 case _HSI_KER:
2277 case _LSI:
2278 case _CSI:
2279 case _CSI_KER:
2280 case _HSE:
2281 case _HSE_KER:
2282 case _HSE_KER_DIV2:
Gabriel Fernandez4e3a51a2021-07-27 15:39:16 +02002283 case _HSE_RTC:
Etienne Carriere1368ada2020-05-13 11:49:49 +02002284 case _LSE:
2285 break;
2286
2287 default:
2288 VERBOSE("Cannot secure parent clock %s\n",
2289 stm32mp1_clk_parent_name[parent_id]);
2290 panic();
2291 }
2292
2293 grandparent_id = get_parent_id_parent(parent_id);
2294 if (grandparent_id >= 0) {
2295 secure_parent_clocks(grandparent_id);
2296 }
2297}
2298
2299void stm32mp1_register_clock_parents_secure(unsigned long clock_id)
2300{
2301 int parent_id;
2302
2303 if (!stm32mp1_rcc_is_secure()) {
2304 return;
2305 }
2306
2307 switch (clock_id) {
2308 case PLL1:
2309 case PLL2:
2310 /* PLL1/PLL2 are always secure: nothing to do */
2311 break;
2312 case PLL3:
2313 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
2314 break;
2315 case PLL4:
2316 ERROR("PLL4 cannot be secured\n");
2317 panic();
2318 break;
2319 default:
2320 /* Others are expected gateable clock */
2321 parent_id = stm32mp1_clk_get_parent(clock_id);
2322 if (parent_id < 0) {
2323 INFO("No parent found for clock %lu\n", clock_id);
2324 } else {
2325 secure_parent_clocks(parent_id);
2326 }
2327 break;
2328 }
2329}
2330#endif /* STM32MP_SHARED_RESOURCES */
Yann Gautier9aea69e2018-07-24 17:13:36 +02002331
Yann Gautierc7f9e962019-05-20 14:39:26 +02002332static void sync_earlyboot_clocks_state(void)
2333{
Etienne Carriere2a756c22019-12-08 08:23:35 +01002334 unsigned int idx;
2335 const unsigned long secure_enable[] = {
2336 AXIDCG,
2337 BSEC,
2338 DDRC1, DDRC1LP,
2339 DDRC2, DDRC2LP,
2340 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP,
2341 DDRPHYC, DDRPHYCLP,
Lionel Debievecfa88cc2019-09-02 18:15:45 +02002342 RTCAPB,
Etienne Carriere2a756c22019-12-08 08:23:35 +01002343 TZC1, TZC2,
2344 TZPC,
2345 STGEN_K,
2346 };
2347
2348 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) {
2349 stm32mp_clk_enable(secure_enable[idx]);
2350 }
Yann Gautierc7f9e962019-05-20 14:39:26 +02002351}
2352
Yann Gautiera205a5c2021-08-30 15:06:54 +02002353static const struct clk_ops stm32mp_clk_ops = {
2354 .enable = stm32mp_clk_enable,
2355 .disable = stm32mp_clk_disable,
2356 .is_enabled = stm32mp_clk_is_enabled,
2357 .get_rate = stm32mp_clk_get_rate,
2358 .get_parent = stm32mp1_clk_get_parent,
2359};
2360
Yann Gautier9aea69e2018-07-24 17:13:36 +02002361int stm32mp1_clk_probe(void)
2362{
Lionel Debieve3c0fbfe2020-12-15 10:35:59 +01002363#if defined(IMAGE_BL32)
2364 if (!fdt_get_rcc_secure_state()) {
2365 mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U);
2366 }
2367#endif
2368
Yann Gautier9aea69e2018-07-24 17:13:36 +02002369 stm32mp1_osc_init();
2370
Yann Gautierc7f9e962019-05-20 14:39:26 +02002371 sync_earlyboot_clocks_state();
2372
Yann Gautiera205a5c2021-08-30 15:06:54 +02002373 clk_register(&stm32mp_clk_ops);
2374
Yann Gautier9aea69e2018-07-24 17:13:36 +02002375 return 0;
2376}